AD5251BRUZ50_技术文档

Dual 64-/256-Position I²C Nonvolatile

Memory Digital Potentiometers

Data Sheet

AD5251/AD5252

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AD5251: Dual 64-position resolution

AD5252: Dual 256-position resolution

1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Nonvolatile memory¹stores wiper setting w/write protection

Power-on refreshed with EEMEM settings in 300 µs typ

EEMEM rewrite time = 540 µs typ

Resistance tolerance stored in nonvolatile memory

12 extra bytes in EEMEM for user-defined information

I²C-compatible serial interface

Direct read/write access of RDAC²and EEMEM registers

Predefined linear increment/decrement commands

Predefined 6 dB step change commands

Synchronous or asynchronous dual-channel update

Wiper setting readback

RDAC EEMEM

V

RDAC1

DD

A1

W1

B1

RDAC1

REGIS-

TER

EEMEM

POWER-ON

REFRESH

RAB

TOL

V

SS

DGND

WP

DATA

RDAC3

A3

W3

B3

SCL

SDA

RDAC3

REGIS-

TER

2

I C

SERIAL

INTERFACE

CONTROL

AD0

AD1

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

AD5251/

AD5252

POWER-

ON RESET

CONTROL LOGIC

Figure 1.

4 MHz bandwidth—1 kΩ version

Single supply 2.7 V to 5.5 V

Dual supply 2.25 V to 2.75 V

2 slave address decoding bits allow operation of 4 devices

100-year typical data retention, T_A= 55°C

Operating temperature: –40°C to +105°C

The AD5251/AD5252 allow the host I²C controllers to write

any of the 64-/256-step wiper settings in the RDAC registers

and store them in the EEMEM. Once the settings are stored,

they are restored automatically to the RDAC registers at system

power-on; the settings can also be restored dynamically.

The AD5251/AD5252 provide additional increment,

decrement, +6 dB step change, and –6 dB step change in

synchronous or asynchronous channel update mode. The

increment and decrement functions allow stepwise linear

adjustments, with a 6 dB step change equivalent to doubling

or halving the RDAC wiper setting. These functions are useful

for steep-slope, nonlinear adjustments, such as white LED

brightness and audio volume control.

APPLICATIONS

Mechanical potentiometer replacement

General-purpose DAC replacement

LCD panel V_COMadjustment

White LED brightness adjustment

RF base station power amp bias control

Programmable gain and offset control

Programmable voltage-to-current conversion

Programmable power supply

The AD5251/AD5252 have a patented resistance-tolerance

storing function that allows the user to access the EEMEM and

obtain the absolute end-to-end resistance values of the RDACs

for precision applications.

Sensor calibrations

GENERAL DESCRIPTION

The AD5251/AD5252 are dual-channel, I²C®, nonvolatile mem-

ory, digitally controlled potentiometers with 64/256 positions,

respectively. These devices perform the same electronic adjust-

ment functions as mechanical potentiometers, trimmers, and

variable resistors. The parts’ versatile programmability allows

multiple modes of operation, including read/write access in the

RDAC and EEMEM registers, increment/decrement of resistance,

resistance changes in 6 dB scales, wiper setting readback, and

extra EEMEM for storing user-defined information, such as

memory data for other components, look-up table, or system

identification information.

The AD5251/AD5252 are available in TSSOP-14 packages in

1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are

guaranteed to operate over the –40°C to +105°C extended

industrial temperature range.

¹The terms nonvolatile memory and EEMEM are used interchangeably.

²The terms digital potentiometer and RDAC are used interchangeably.

Rev. D

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rightsof third parties that may result fromits use. Specifications subject to change without notice. No

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Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5251/AD5252

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 21

Linear Increment/Decrement Commands ............................. 21

6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21

Digital Input/Output Configuration........................................ 22

Multiple Devices on One Bus ................................................... 22

Terminal Voltage Operation Range ......................................... 22

Power-Up and Power-Down Sequences.................................. 22

Layout and Power Supply Biasing............................................ 23

Digital Potentiometer Operation ............................................. 23

Programmable Rheostat Operation......................................... 23

Programmable Potentiometer Operation ............................... 24

Applications Information .............................................................. 25

LCD Panel V_COMAdjustment.................................................... 25

Current-Sensing Amplifier ....................................................... 25

Adjustable High Power LED Driver ........................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

1 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5

Interface Timing Characteristics................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

I²C Interface..................................................................................... 14

I²C Interface General Description............................................ 14

I²C Interface Detail Description............................................... 15

I²C-Compatible 2-Wire Serial Bus........................................... 20

REVISION HISTORY

9/12—Rev. C to Rev. D

Changed Temperature Range from –40°C to +85°C to –40°C

to +105°C (Throughout).................................................................. 1

9/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Figure 6 ......................................................................... 10

Changes to Figure 28...................................................................... 15

Changes to Figure 29...................................................................... 17

Changes to RDAC/EEMEM Quick Commands Section .......... 18

Changes to EEMEM Write Protection Section .......................... 18

Changes to Figure 37...................................................................... 22

Deleted Table 13 and Table 14 ...................................................... 23

Change to Figure 42 ....................................................................... 24

Change to Figure 46 ....................................................................... 25

Changes to Ordering Guide.......................................................... 27

Changed

Leakage Current from 5 µA to 8 µA, Table 1........ 4

WP

Changed

Leakage Current from 5 µA to 8 µA, Table 2........ 5

WP

Changes to Figure 11 and Figure 12............................................. 11

12/11—Rev. B to Rev. C

Changes to Theory of Operation Section.................................... 21

Changes to Ordering Guide .......................................................... 27

10/09—Rev. A to Rev. B

Changes to Figure 15...................................................................... 12

Changes to Figure 27...................................................................... 15

6/04—Revision 0: Initial Version

Rev. D | Page 2 of 28

Data Sheet

AD5251/AD5252

ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

V_DD= 3 V 10% or 5 V 10%, V_SS= 0 V or V_DD/V_SS

=

2.5 V 10%, V_A= V_DD, V_B= 0 V, –40°C < T_A< +105°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

DC CHARACTERISTICS—

RHEOSTAT MODE

Resolution

N

AD5251

AD5252

6

8

Bits

LSB

%

Resistor Differential Nonlinearity²

R-DNL

R_WB, R_WA= NC, V_DD= 5.5 V, AD5251

R_WB, R_WA= NC, V_DD= 5.5 V, AD5252

R_WB, R_WA= NC, V_DD= 2.7 V, AD5251

R_WB, R_WA= NC, V_DD= 2.7 V, AD5252

R_WB, R_WA= NC, V_DD= 5.5 V, AD5251

R_WB, R_WA= NC, V_DD= 5.5 V, AD5252

R_WB, R_WA= NC, V_DD= 2.7 V, AD5251

R_WB, R_WA= NC, V_DD= 2.7 V, AD5252

T_A= 25°C

–0.5

–1.00

–0.75

–1.5

–0.5

–2.0

–1.0

–2

0.2

0.25

0.30

0.3

0.2

0.5

+0.5

+1.00

+0.75

+1.5

+0.5

+2.0

+4.0

+14

+30

Resistor Nonlinearity²

R-INL

+2.5

+9

Nominal Resistor Tolerance

Resistance Temperature Coefficient (ΔR_AB/R_AB) × 10⁶/ΔT

Wiper Resistance

ΔR_AB/R_AB

–30

650

75

200

0.15

ppm/°C

Ω

R_W

I_W= 1 V/R, V_DD= 5 V

I_W= 1 V/R, V_DD= 3 V

130

300

Channel-Resistance Matching

ΔR_AB1/ΔR_AB3

%

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

Differential Nonlinearity³

DNL

INL

AD5251

AD5252

AD5251

AD5252

–0.5

–1.00

–0.5

–2.0

0.1

0.25

0.2

0.5

25

–3

–11

–4

–16

3

11

4

15

+0.5

+1.00

+0.5

+2.0

LSB

ppm/°C

LSB

Integral Nonlinearity³

Voltage Divider Tempco

Full-Scale Error

(ΔV_W/V_W) × 10⁶/ΔT

V_WFSE

Code = half scale

Code = full scale, V_DD= 5.5 V, AD5251

Code = full scale, V_DD= 5.5 V, AD5252

Code = full scale, V_DD= 2.7 V, AD5251

Code = full scale, V_DD= 2.7 V, AD5252

Code = zero scale, V_DD= 5.5 V, AD5251

Code = zero scale, V_DD= 5.5 V, AD5252

Code = zero scale, V_DD= 2.7 V, AD5251

Code = zero scale, V_DD= 2.7 V, AD5252

–5

–16

−6

–23

0

5

16

6

Zero-Scale Error

V_WZSE

20

RESISTOR TERMINALS

Voltage Range⁴

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

pF

Capacitance⁵A, B

f = 1 kHz, measured to GND,

code = half scale

f = 1 kHz, measured to GND,

code = half scale

85

Capacitance⁵W

C_W

I_CM

95

pF

µA

Common-Mode Leakage Current

V_A= V_B= V_DD/2

0.01

1

Rev. D | Page 3 of 28

AD5251/AD5252

Data Sheet

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High

V_IH

V_DD= 5 V, V_SS= 0 V

2.4

V

V_DD/V_SS= 2.7 V/0 V or V_DD/V_SS= 2.5 V 2.1

V_DD= 5 V, V_SS= 0 V

V

µA

Input Logic Low

V_IL

V_OH

V_OL

I_WP

I_A0

I_I

0.8

Output Logic High (SDA)

Output Logic Low (SDA)

WP Leakage Current

A0 Leakage Current

Input Leakage Current

(Other than WP and A0)

R_PULL-UP= 2.2 kΩ to V_DD= 5 V, V_SS= 0 V

WP = V_DD

4.9

0.4

8

A0 = GND

V_IN= 0 V or V_DD

3

1

Input Capacitance⁵

C_I

5

pF

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

V_DD

V_DD/V_SS

I_DD

V_SS= 0 V

2.7

2.25

5.5

2.75

15

–15

V

µA

V_IH= V_DDor V_IL= GND

V_IH= V_DDor V_IL= GND, V_DD= 2.5 V,

V_SS= –2.5 V

5

–5

I_SS

EEMEM Data Storing Mode Current

I_{DD_STORE}

I_{DD_RESTORE}

V_IH= V_DDor V_IL= GND

35

2.5

mA

EEMEM Data Restoring Mode

Current⁶

Power Dissipation⁷

P_DISS

PSS

V_IH= V_DD= 5 V or V_IL= GND

ΔV_DD= 5 V 10%

0.075

mW

Power Supply Sensitivity

−0.025 +0.010 +0.025 %/%

ΔV_DD= 3 V 10%

–0.04

+0.02

+0.04

%/%

DYNAMIC CHARACTERISTICS^{5, 8}

Bandwidth –3 dB

Total Harmonic Distortion

V_WSettling Time

BW

THD

t_S

R_AB= 1 kΩ

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= V_DD, V_B= 0 V

R_WB= 500 Ω, f = 1 kHz

(thermal noise only)

4

MHz

%

µs

0.05

0.2

3

Resistor Noise Voltage

e_{N_WB}

nV/√Hz

Digital Crosstalk

Analog Coupling

C_T

V_A= V_DD, V_B= 0 V, measure V_Wwith

adjacent RDAC making full-scale

change

Signal input at A1 and measure the

output at W3, f = 1 kHz

–80

–72

dB

C_AT

¹Typical values represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V_DD

2.7 V, I_W= V_DD/R for both V_DD= 3 V and V_DD= 5 V.

=

³INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁴Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

⁵Guaranteed by design and not subject to production test.

⁶Command 0 NOP should be activated after Command 1 to minimize I_{DD_READ}current consumption.

⁷P_DISSis calculated from I_DD× V_DD= 5 V.

⁸All dynamic characteristics use V_DD= 5 V.

Rev. D | Page 4 of 28

Data Sheet

AD5251/AD5252

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

V_DD= +3 V 10% or +5 V 10%, V_SS= 0 V or V_DD/V_SS= 2.5 V 10%, V_A= V_DD, V_B= 0 V, –40°C < T_A< +105°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

DC CHARACTERISTICS—

RHEOSTAT MODE

Resolution

N

AD5251

AD5252

6

8

Bits

LSB

%

Resistor Differential Nonlinearity²R-DNL

R_WB, R_WA= NC, AD5251

R_WB, R_WA= NC, AD5252

R_WB, R_WA= NC, AD5251

R_WB, R_WA= NC, AD5252

T_A= 25°C

−0.75

−1.00

−0.75

−2.5

0.10

0.25

1.0

+0.75

+1.00

+0.75

+2.5

+20

Resistor Nonlinearity²

R-INL

Nominal Resistor Tolerance

Resistance Temperature

Coefficient

ΔR_AB/R_AB

(ΔR_AB/R_AB) × 10⁶/ΔT

−20

650

ppm/°C

Wiper Resistance

R_W

I_W= 1 V/R, V_DD= 5 V

I_W= 1 V/R, V_DD= 3 V

R_AB= 10 kΩ, 50 kΩ

R_AB= 100 kΩ

75

130

300

Ω

%

200

0.15

0.05

Channel-Resistance Matching

ΔR_AB1/ΔR_AB2

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

Differential Nonlinearity³

DNL

INL

AD5251

AD5252

AD5251

AD5252

−0.5

−1.0

−0.50

−1.5

0.1

0.3

0.15

0.5

+0.5

+1.0

+0.50

+1.5

LSB

Integral Nonlinearity³

Voltage Divider

Temperature Coefficient

Full-Scale Error

Zero-Scale Error

(ΔV_W/V_W) × 10⁶/ΔT

V_WFSE

Code = half scale

15

ppm/°C

Code = full scale, AD5251

Code = full scale, AD5252

Code = zero scale, AD5251

Code = zero scale, AD5252

−1.0

−3

0

−0.3

−1

0.3

1.2

0

1.0

3.0

LSB

V_WZSE

0

RESISTOR TERMINALS

Voltage Range⁴

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

pF

Capacitance⁵A, B

f = 1 kHz, measured to GND,

code = half scale

f = 1 kHz, measured to GND,

code = half scale

85

Capacitance⁵W

C_W

95

pF

µA

Common-Mode Leakage Current I_CM

DIGITAL INPUTS AND OUTPUTS

V_A= V_B= V_DD/2

0.01

1.00

Input Logic High

V_IH

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or V_DD/V_SS= 2.5 V

V_DD= 5 V, V_SS= 0 V

V_DD/V_SS= +2.7 V/0 V or V_DD/V_SS= 2.5 V

R_PULL-UP= 2.2 kΩ to V_DD= 5 V, V_SS= 0 V

WP = V_DD

2.4

2.1

V

µA

Input Logic Low

V_IL

0.8

0.6

Output Logic High (SDA)

Output Logic Low (SDA)

WP Leakage Current

A0 Leakage Current

Input Leakage Current

(Other than WP and A0)

V_OH

V_OL

I_WP

I_A0

I_I

4.9

0.4

8

A0 = GND

V_IN= 0 V or V_DD

3

1

Input Capacitance⁵

C_I

5

pF

Rev. D | Page 5 of 28

AD5251/AD5252

Data Sheet

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

V_DD

V_DD/V_SS

I_DD

V_SS= 0 V

2.7

2.25

5.5

2.75

15

−15

V

µA

V_IH= V_DDor V_IL= GND

V_IH= V_DDor V_IL= GND, V_DD= 2.5 V,

V_SS= −2.5 V

5

−5

I_SS

EEMEM Data Storing Mode

Current

I_{DD_STORE}

V_IH= V_DDor V_IL= GND, T_A= 0°C to 105°C

35

mA

mW

EEMEM Data Restoring Mode

I_{DD_RESTORE}

V_IH= V_DDor V_IL= GND, T_A= 0°C to 105°C

2.5

Current⁶

Power Dissipation⁷

P_DISS

PSS

V_IH= V_DD= 5 V or V_IL= GND

ΔV_DD= 5 V 10%

ΔV_DD= 3 V 10%

0.075

Power Supply Sensitivity

−0.005 +0.002

−0.010 +0.002

+0.005 %/%

+0.010 %/%

DYNAMIC CHARACTERISTICS^{5, 8}

–3 dB Bandwidth

Total Harmonic Distortion

V_WSettling Time

BW

THD_W

t_S

R_AB= 10 kΩ/50 kΩ/100 kΩ

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= V_DD, V_B= 0 V,

400/80/40

0.05

1.5/7/14

kHz

%

µs

R_AB= 10 kΩ/50 kΩ/100 kΩ

Resistor Noise Voltage

Digital Crosstalk

e_{N_WB}

R_AB= 10 kΩ/50 kΩ/100 kΩ,

code = midscale, f = 1 kHz

(thermal noise only)

V_A= V_DD, V_B= 0 V, measure V_Wwith

adjacent RDAC making full-scale

change

9/20/29

−80

nV/√Hz

C_T

dB

Analog Coupling

C_AT

Signal input at A1 and measure

output at W3, f = 1 kHz

−72

¹Typical values represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V_DD= 2.7 V,

I_W= V_DD/R for both V_DD= 3 V and V_DD= 5 V.

³INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider, similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of 1 LSB maximum are guaranteed monotonic operating conditions.

⁴Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

⁶Command 0 NOP should be activated after Command 1 to minimize I_{DD_READ}current consumption.

⁷P_DISSis calculated from I_DD× V_DD= 5 V.

⁸All dynamic characteristics use V_DD= 5 V.

Rev. D | Page 6 of 28

Data Sheet

AD5251/AD5252

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with t_R= t_F= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching

characteristics are measured using both V_DD= 3 V and 5 V.

Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)¹

Parameter

Symbol

Conditions

Min Typ Max

Unit

INTERFACE TIMING

SCL Clock Frequency

t_BUFBus-Free Time Between Stop and Start

t_HD;STAHold Time (Repeated Start)

f_SCL

t₁

t₂

400

kHz

µs

1.3

0.6

After this period, the first clock pulse is

generated.

t_LOWLow Period of SCL Clock

t₃

1.3

0.6

µs

ns

µs

t_HIGHHigh Period of SCL Clock

t_SU;STASet-up Time for Start Condition

t_HD;DATData Hold Time

t₄

t₅

t₆

0

0.9

t_SU;DATData Set-up Time

t₇

100

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSet-up Time for Stop Condition

t₈

300

t₉

t₁₀

0.6

EEMEM Data Storing Time

EEMEM Data Restoring Time at Power-On²

t_{EEMEM_STORE}

26

300

ms

µs

t_{EEMEM_RESTORE1}V_DDrise time dependent. Measure

without decoupling capacitors at V_DD

and V_SS.

EEMEM Data Restoring Time upon Restore

Command or Reset Operation²

EEMEM Data Rewritable Time (Delay Time

After Power-On or Reset Before EEMEM

Can Be Written)

t_{EEMEM_RESTORE2}V_DD= 5 V.

300

540

µs

t_{EEMEM_REWRITE}

FLASH/EE MEMORY RELIABILITY

Endurance³

Data Retention⁴

100

k cycles

Years

100

¹Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.

²During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.

³Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000

cycles.

⁴Retention lifetime equivalent at junction temperature T_J= 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature in Flash/EE memory.

Rev. D | Page 7 of 28

AD5251/AD5252

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

−0.3 V, +7 V

+0.3 V, −7 V

7 V

V_A, V_B, V_Wto GND

Maximum Current

I_WB, I_WAPulsed

I_WBContinuous (R_WB≤ 1 kΩ, A Open)¹

I_WAContinuous (R_WA≤ 1 kΩ, B Open)¹

V_SS, V_DD

20 mA

5 mA

ESD CAUTION

I_ABContinuous

5 mA/ 500 µA/

100 µA/ 50 µA

(R_AB= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)¹

Digital Inputs and Output Voltage to GND 0 V, 7 V

Operating Temperature Range

Maximum Junction Temperature (T_JMAX

Storage Temperature Range

Lead Temperature (Soldering, 10 sec)

Vapor Phase (60 sec)

−40°C to +105°C

150°C

−65°C to +150°C

300°C

215°C

)

Infrared (15 sec)

TSSOP-14 Thermal Resistance²θ_JA

220°C

136°C/W

¹Maximum terminal current is bound by the maximum applied voltage across

any two of the A, B, and W terminals at a given resistance, the maximum

current handling of the switches, and the maximum power dissipation of the

package. V_DD= 5 V.

²Package power dissipation = (T_JMAX− T_A)/θ_JA

.

Rev. D | Page 8 of 28

Data Sheet

AD5251/AD5252

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

V

14

13

12

11

W3

B3

DD

AD0

WP

W1

B1

AD5251/

AD5252

A3

AD1

TOP VIEW

(Not to Scale)

10 DGND

9

8

A1

SCL

SDA

V

SS

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or 2.7 V for dual supply, where

1

V_DD

V

_DD– V_SS≤ 5.5 V. V_DDmust be able to source 35 mA for 26 ms when storing data to EEMEM.

2

3

4

5

6

7

AD0

WP

W1

B1

A1

SDA

I²C Device Address 0. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.

Write Protect, Active Low. V_WP≤ V_DD+ 0.3 V.

Wiper Terminal of RDAC1. V_SS≤ V_W1≤ V_DD.¹

B Terminal of RDAC1. V_SS≤ V_B1≤ V_DD.¹

A Terminal of RDAC1. V_SS≤ V_A1≤ V_DD.¹

Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first.

Open-drain MOSFET requires pull-up resistor.

8

9

V_SS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V_DD– V_SS≤ +5.5 V. If

V_SSis used in dual supply, V_SSmust be able to sink 35 mA for 26 ms when storing data to EEMEM.

Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. V_SCL≤ (V_DD+ 0.3 V).

Pull-up resistor is recommended for SCL to ensure minimum power.

SCL

10

11

12

13

14

DGND

AD1

A3

B3

W3

Digital Ground. Connect to system analog ground at a single point.

I²C Device Address 1. AD0 and AD1 allow four AD5251/AD5252 devices to be addressed.

A Terminal of RDAC3. V_SS≤ V_A3≤ V_DD.¹

B Terminal of RDAC3. V_SS≤ V_B3≤ V_DD.¹

Wiper Terminal of RDAC3. V_SS≤ V_W3≤ V_DD.¹

¹For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

Rev. D | Page 9 of 28

AD5251/AD5252

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

1.0

0.8

T

= –40°C, +25°C, +85°C, +125°C

A

0.6

T

= –40°C, +25°C, +85°C, +125°C

A

0.4

0.2

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 3. R-INL vs. Code

Figure 6. DNL vs. Code

10

8

1.0

0.8

T

= –40°C, +25°C, +85°C, +125°C

A

I

@ V = 5.5V

DD

6

0.6

4

0.4

2

0.2

I

@ V = 2.7V

DD

0

–2

–4

–6

–8

–10

–0.2

–0.4

–0.6

–0.8

–1.0

I

@ V = 2.7V, V = –2.7V

DD SS

SS

–40

–20

0

20

40

60

80

100

120

0

32

64

96

128

160

192

224

256

TEMPERATURE (°C)

CODE (Decimal)

Figure 4. R-DNL vs. Code

Figure 7. Supply Current vs. Temperature

1.0

0.8

10

T

= –40°C, +25°C, +85°C, +125°C

A

V

= 5.5V

DD

0.6

1

0.1

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0.01

V

= 2.7V

DD

0.001

0.0001

0

32

64

96

128

160

192

224

256

0

1

2

3

4

5

6

CODE (Decimal)

DIGITAL INPUT VOLTAGE (V)

Figure 5. INL vs. Code

Figure 8. Supply Current vs. Digital Input Voltage, T_A= 25°C

Rev. D | Page 10 of 28

Data Sheet

AD5251/AD5252

240

220

200

180

160

140

120

100

80

50

45

40

35

30

25

20

15

10

5

DATA = 0x00

V

= 5V

DD

T

= –40°C TO +85°C

= V

DD

= 0V

A

V

T

= 2.7V

= 25C

DD

V

A

B

A

V

T

= 5.5V

= 25C

DD

A

100kΩ

10kΩ

60

40

20

50kΩ

0

1

2

3

4

5

6

0

32

64

96

128

160

192

224

256

V

(V)

BIAS

CODE (Decimal)

Figure 9. Wiper Resistance vs. V_BIAS

Figure 12. AD5252 Potentiometer Mode Tempco ∆V_WB/∆T vs. Code

0

6

4

0xFF

–6

0x80

0x40

–12

0x20

–18

–24

–30

–36

–42

–48

–54

–60

0x10

2

0

0x08

0x04

0x02

–2

–4

–6

0x01

0x00

10

100

1k

10k

100k

1M

10M

–40

–20

0

20

40

60

80

100

120

FREQUENCY (Hz)

TEMPERATURE (C)

Figure 13. AD5252 Gain vs. Frequency vs. Code, R_AB= 1 kΩ, T_A= 25°C

Figure 10. Change of R_WBvs. Temperature

1000

950

900

850

800

750

700

650

600

550

500

0

0xFF

V

= 5V

–6

DD

0x80

T

= –40°C TO +85°C

= V

DD

= 0V

A

–12

V

A

B

0x40

–18

0x20

–24

0x10

10kΩ

–30

0x08

100kΩ

0x04

–36

50kΩ

–42

0x01

–48

0x00

0x02

–54

–60

0

32

64

96

128

160

192

224

256

10

100

1k

10k

100k

1M

10M

CODE (Decimal)

FREQUENCY (Hz)

Figure 11. AD5252 Rheostat Mode Tempco ∆R_WB/∆T vs. Code

Figure 14. AD5252 Gain vs. Frequency vs. Code, R_AB= 10 kΩ , T_A= 25°C

Rev. D | Page 11 of 28

AD5251/AD5252

Data Sheet

0

–6

1.2

1.0

0.8

0.6

0.4

0.2

0

0xFF

T

= 25°C

A

0x80

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x40

0x20

0x10

V

= 5.5V

DD

0x08

0x04

0x02

0x01

V

= 2.7V

DD

0x00

1

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

CLOCK FREQUENCY (Hz)

Figure 15. AD5252 Gain vs. Frequency vs. Code, R_AB= 50 kΩ , T_A= 25°C

Figure 18. Supply Current vs. Digital Input Clock Frequency

0

0x80

0x40

0xFF

CLK

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

V

= 5V

DD

0x20

0x10

0x08

0x04

0x02

0x01

V

W

DIGITAL FEEDTHROUGH

0x00

10

100

1k

10k

100k

1M

10M

400ns/DIV

FREQUENCY (Hz)

Figure 16. AD5252 Gain vs. Frequency vs. Code, R_AB= 100 kΩ , T_A= 25°C

Figure 19. Clock Feedthrough and Midscale Transition Glitch

100

V

= 5.5V

DD

80

60

100k

1k

V

DD

(NO DE-

COUPLING

CAPS)

40

10k

RESTORE RDAC1

SETTING TO 0x3F

20

MIDSCALE

PRESET

V

(0x3F

WB1

0

STORED

IN EEMEM)

RESTORE RDAC3

SETTING TO 0x3F

–20

–40

–60

–80

–100

50k



MIDSCALE

PRESET

V

WB3

(0x3F

STORED

IN EEMEM)

V

= VA1 = VA3 = 3.3V

DD

GND = VB1 = VB3

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 17. AD5252 ΔR_ABvs. Code, T_A= 25°C

Figure 20. t_{EEMEM_RESTORE}of RDAC0 and RDAC3

Rev. D | Page 12 of 28

Data Sheet

AD5251/AD5252

6

5

4

3

6

5

4

3

2

1

0

R

= 1kΩ

R

= 1kΩ

AB

V

T

= V = OPEN

B

= 25°C

V

= V = OPEN

A B

= 25°C

A

T

A

R

= 10kΩ

R

= 10kΩ

2

1

0

AB

R

= 50kΩ

R

= 50kΩ

AB

R

= 100kΩ

R

= 100kΩ

AB

0

8

16

24

32

40

48

56

64

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 21. AD5251 I_{WB_MAX}vs. Code

Figure 22. AD5252 I_{WB_MAX}vs. Code

Rev. D | Page 13 of 28

AD5251/AD5252

I²C INTERFACE

Data Sheet

t₂

t₈

t₆

t₉

SCL

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

SDA

t₁

P

S

P

Figure 23. I²C Interface Timing Diagram

I²C INTERFACE GENERAL DESCRIPTION

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

P = STOP CONDITION

A = ACKNOWLEDGE (SDA LOW)

A = NOT ACKNOWLEDGE (SDA HIGH)

R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW

SLAVE ADDRESS

INSTRUCTIONS

(8-BIT)

DATA

(8-BIT)

S

R/W

A

A/A

P

(7-BIT)

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

0 WRITE

Figure 24. I²C—Master Writing Data to Slave

SLAVE ADDRESS

(7-BIT)

DATA

(8-BIT)

DATA

(8-BIT)

S

R/W

A

P

DATA TRANSFERRED

1 READ

(N BYTES + ACKNOWLEDGE)

Figure 25. I²C—Master Reading Data from Slave

SLAVE ADDRESS

(7-BIT)

A/A

S

R/W

A

DATA

S

SLAVE ADDRESS

R/W

A

DATA

P

READ OR WRITE

(N BYTES +

ACKNOWLEDGE)

REPEATED START

READ

OR WRITE

(N BYTES +

ACKNOWLEDGE)

DIRECTION OF TRANSFER MAY

CHANGE AT THIS POINT

Figure 26. I²C—Combined Write/Read

Rev. D | Page 14 of 28

Data Sheet

AD5251/AD5252

I²C INTERFACE DETAIL DESCRIPTION

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

P = STOP CONDITION

A = ACKNOWLEDGE (SDA LOW)

A = NOT ACKNOWLEDGE (SDA HIGH)

R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW

CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTERACCESS BIT, LOGIC LOW

EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW

A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S

0

1

0

1

A

D

1

A

D

0

A

CMD/

REG

0

EE/

RDAC

A

4

A

3

A

2

A

1

A

0

A

DATA

A/

A

P

SLAVE ADDRESS

INSTRUCTIONS

AND ADDRESS

(1 BYTE +

ACKNOWLEDGE)

0 WRITE

0 REG

Figure 27. Single Write Mode

A/

A

S

0

1

0

1

A

D

1

A

D

0

A

CMD/

REG

0

EE/

RDAC

A

4

A

3

A

2

A

1

A

0

A

RDAC1

DATA

A

X

A

RDAC3

DATA

P

DATA

RDAC SLAVE ADDRESS

RDAC INSTRUCTIONS

AND ADDRESS

(N BYTES +

ACKNOWLEDGE)

0 WRITE

0 REG

Figure 28. Consecutive Write Mode

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/ = 0, CMD/

= 0, EE/ = 0)

RDAC

W

REG

A4

0

:

A3

0

:

A2

0

1

:

A1

0

1

0

:

A0

0

1

0

1

0

:

RDAC

Reserved

RDAC1

Reserved

RDAC3

Reserved

:

Data Byte Description

6-/8-bit wiper setting (2 MSB of AD5251 are X)

:

0

1

Reserved

Rev. D | Page 15 of 28

AD5251/AD5252

Data Sheet

RDAC/EEMEM Write

Table 7. Addresses for Writing (Storing) RDAC Settings

and User-Defined Data to EEMEM Registers

(R/ = 0, CMD/

= 0, EE/ = 1)

Setting the wiper position requires an RDAC write operation.

The single write operation is shown in Figure 27, and the

consecutive write operation is shown in Figure 28. In the

W

REG

RDAC

consecutive write operation, if the

is selected and the

A4 A3 A2 A1 A0 Data Byte Description

RDAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

address starts at 00001, the first data byte goes to RDAC1 and

the second data byte goes to RDAC3. The RDAC address is

shown in Table 6.

Store RDAC1 setting to EEMEM1¹

Reserved

Store RDAC3 setting to EEMEM3¹

Store user data to EEMEM4

Store user data to EEMEM5

Store user data to EEMEM6

Store user data to EEMEM7

Store user data to EEMEM8

Store user data to EEMEM9

Store user data to EEMEM10

Store user data to EEMEM11

Store user data to EEMEM12

Store user data to EEMEM13

Store user data to EEMEM14

Store user data to EEMEM15

While the RDAC wiper setting is controlled by a specific RDAC

register, each RDAC register corresponds to a specific EEMEM

location, which provides nonvolatile wiper storage functionality.

The addresses are shown in Table 7. The single and consecutive

write operations also apply to EEMEM write operations.

There are 12 nonvolatile memory locations: EEMEM4 to

EEMEM15. Users can store a total of 12 bytes of information,

such as memory data for other components, look-up tables, or

system identification information.

In a write operation to the EEMEM registers, the device disables

the I²C interface during the internal write cycle. Acknowledge

polling is required to determine the completion of the write

cycle. See the EEMEM Write-Acknowledge Polling section.

1

Users can store any of the 64 RDAC settings directly to the EEMEM for

AD5251, or any of the 256 RDAC settings directly to the EEMEM for the

AD5252. This is not limited to current RDAC wiper setting.

RDAC/EEMEM Read

Table 8. Addresses for Reading (Restoring) RDAC Settings

and User Data from EEMEM

The AD5251/AD5252 provide two different RDAC or EEMEM

read operations. For example, Figure 29 shows the method of

reading the RDAC0 to RDAC3 contents without specifying the

address, assuming Address RDAC0 was already selected in the

previous operation. If an RDAC_N address other than RDAC0

was previously selected, readback starts with Address N, followed

by N + 1, and so on.

(R/ = 1, CMD/

= 0, EE/ = 1)

W

REG

RDAC

A4 A3 A2 A1 A0 Data Byte Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

Read RDAC1 setting from EEMEM1

Reserved

Read RDAC3 setting from EEMEM3

Read user data from EEMEM4

Read user data from EEMEM5

Read user data from EEMEM6

Read user data from EEMEM7

Read user data from EEMEM8

Read user data from EEMEM9

Read user data from EEMEM10

Read user data from EEMEM11

Read user data from EEMEM12

Read user data from EEMEM13

Read user data from EEMEM14

Read user data from EEMEM15

Figure 30 illustrates a random RDAC or EEMEM read

operation. This operation allows users to specify which RDAC

or EEMEM register is read by issuing a dummy write command

to change the RDAC address pointer and then proceeding with

the RDAC read operation at the new address location.

Rev. D | Page 16 of 28

Data Sheet

AD5251/AD5252

S

0

1

0

1

A

D

1

A

D

0

1

A

RDAC1

A

X

A

RDAC3

P

A/

A

EEMEM OR REGISTER DATA

DATA

EEMEM OR REGISTER DATA

SLAVE ADDRESS

(N BYTES + ACKNOWLEDGE)

1 READ

Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)

S

SLAVE ADDRESS

0

A

INSTRUCTION AND

ADDRESS

A

S

SLAVE ADDRESS

1

A

RDAC OR

EEMEM DATA

A/A

P

(N BYTES + ACKNOWLEDGE)

0 WRITE

REPEATED START

1 READ

Figure 30. RDAC or EEMEM Random Read

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

P = STOP CONDITION

A = ACKNOWLEDGE (SDA LOW)

A = NOT ACKNOWLEDGE (SDA HIGH)

2

AD1, AD0 = I C DEVICE ADDRESS BITS; MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0

R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW

CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW

C3, C2, C1, C0 = COMMAND BITS

A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES

S

0

1

0

1

A

D

1

A

D

0

A

CMD/

REG

C

3

C

2

C

1

C

0

A

2

A

1

A

0

A

P

RDAC SLAVE ADDRESS

0 WRITE

1 CMD

Figure 31. RDAC Quick Command Write (Dummy Write)

Rev. D | Page 17 of 28

AD5251/AD5252

Data Sheet

for the decimal portion of tolerance. As shown in Table 10

RDAC/EEMEM Quick Commands

and Figure 32, for example, if the rated R_ABis 10 kΩ and the

data readback from Address 11000 shows 0001 1100 and

Address 11001 shows 0000 1111, then RDAC0 tolerance can be

calculated as

The AD5251/AD5252 feature 12 quick commands that facilitate

easy manipulation of RDAC wiper settings and provide RDAC-

to-EEMEM storing and restoring functions. The command

format is shown in Figure 31, and the command descriptions

are shown in Table 9.

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

8 LSB: 0000 1111 = 15 × 2^–8= 0.06

Tolerance = 28.06% and, therefore,

When using a quick command, issuing a third byte is not needed,

but is allowed. The quick commands reset and store RDAC to

EEMEM require acknowledge polling to determine whether the

command has finished executing.

R_{AB_ACTUAL}= 12.806 kΩ

EEMEM Write-Acknowledge Polling

R_ABTolerance Stored in Read-Only Memory

After each write operation to the EEMEM registers, an

internal write cycle begins. The I²C interface of the device is

disabled. To determine if the internal write cycle is complete

and the I²C interface is enabled, interface polling can be

executed. I²C interface polling can be conducted by sending a

start condition, followed by the slave address and the write bit.

If the I²C interface responds with an ACK, the write cycle is

complete and the interface is ready to proceed with further

operations. Other-wise, I²C interface polling can be repeated

until it succeeds. Command 2 and Command 7 also require

acknowledge polling.

The AD5251/AD5252 feature patented R_ABtolerances storage in

the nonvolatile memory. The tolerance of each channel is stored

in the memory during the factory production and can be read

by users at any time. The knowledge of the stored tolerance,

which is the average of R_ABover all codes (see Figure 16), allows

users to predict R_ABaccurately. This feature is valuable for

precision, rheostat mode, and open-loop applications in which

knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory and are

expressed as percentages. Each tolerance is stored in two memory

locations (see Table 10 ). The tolerance data is expressed in sign

magnitude binary format stored in two bytes; an example is

shown in Figure 32. For the first byte in Register N, the MSB

is designated for the sign (0 = + and 1 = –) and the 7 LSB is

designated for the integer portion of the tolerance. For the

second byte in Register N + 1, all eight data bits are designated

EEMEM Write Protection

Setting the

pin to logic low after EEMEM programming

WP

protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read

operations function as normal.

Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/

= 1, A2 = 0)

REG

C3

0

1

:

C2

0

1

0

1

:

C1

0

1

0

1

0

1

0

:

C0

0

1

0

1

0

1

0

1

0

1

0

1

0

:

Command Description

NOP

Restore EEMEM (A1, A0) to RDAC (A1, A0)¹

Store RDAC (A1, A0) to EEMEM (A1, A0)

Decrement RDAC (A1, A0) 6 dB

Decrement all RDACs 6 dB

Decrement RDAC (A1, A0) one step

Decrement all RDACs one step

Reset: restore EEMEMs to all RDACs

Increment RDACs (A1, A0) 6 dB

Increment all RDACs 6 dB

Increment RDACs (A1, A0) one step

Increment all RDACs one step

Reserved

:

1

Reserved

¹This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

Rev. D | Page 18 of 28

Data Sheet

AD5251/AD5252

Table 10. Address Table for Reading Tolerance (CMD/

= 0, EE/

= 1, A4 = 1)

RDAC

REG

A4

0

:

A3

0

:

A2

0

:

A1

0

:

A0

0

:

Data Byte Description

Reserved

:

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

Sign and 7-bit integer values of RDAC1 tolerance (read only)

8-bit decimal value of RDAC1 tolerance (read only)

Reserved

Sign and 7-bit integer values of RDAC3 tolerance (read only)

8-bit decimal value of RDAC3 tolerance (read only)

A

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

–6

D1

–7

D0

–8

6

5

4

3

2

1

0

–1

2

–2

2

–3

2

–4

2

–5

2

SIGN

2

7 BITS FOR INTEGER NUMBER

8 BITS FOR DECIMAL NUMBER

Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit Is Percent, Only Data Bytes Are Shown)

Rev. D | Page 19 of 28

AD5251/AD5252

Data Sheet

I²C-COMPATIBLE 2-WIRE SERIAL BUS

1

9

1

9

1

9

SCL

0

1

0

1

AD1

R/W

X

D4 D3 D2 D1

AD0

D7 D6 D5

D0

SDA

ACK. BY

AD525x

ACK. BY

AD525x

ACK. BY

AD525x

START BY

MASTER

STOP BY

MASTER

FRAME 1

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

Figure 33. General I²C Write Pattern

1

9

1

9

SCL

D1 D0

0

1

0

1

AD1

AD0

R/W

D7 D6 D5 D4 D3 D2

SDA

ACK. BY

AD525x

NO ACK. BY

MASTER

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

RDAC REGISTER

START BY

MASTER

Figure 34. General I²C Read Pattern

the addresses of the EEMEM and RDAC registers (see

Figure 27 and Figure 28). When MSB = 1 or when the device

is in CMD mode, the four bits following the MSB are C3 to

C1, which correspond to 12 predefined EEMEM controls

and quick commands; there are also four factory-reserved

commands. The 3 LSB—A2, A1, and A0—are addresses,

but only 001 and 011 are used for RDAC1 and RDAC3,

respectively (see Figure 31). After acknowledging the

instruction byte, the last byte in the write mode is the data

byte. Data is transmitted over the serial bus in sequences of

nine clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high period

of SCL (see Figure 33).

The first byte of the AD5251/AD5252 is a slave address byte

(see Figure 33 and Figure 34). It has a 7-bit slave address and an

R/ bit. The 5 MSB of the slave address is 01011, and the next

W

2 LSB is determined by the states of the AD1 and AD0 pins.

AD1 and AD0 allow the user to place up to four

AD5251/AD5252 devices on one bus.

AD5251/AD5252 can be controlled via an I²C-compatible serial

bus and are connected to this bus as slave devices. The 2-wire

I²C serial bus protocol (see Figure 33 and Figure 34) follows:

1. The master initiates a data transfer by establishing a start

condition, such that SDA goes from high to low while SCL

is high (see Figure 33). The following byte is the slave address

byte, which consists of the 5 MSB of a slave address defined

as 01011. The next two bits are AD1 and AD0, I²C device

address bits. Depending on the states of their AD1 and

AD0 bits, four AD5251/AD5252 devices can be addressed

3. In current read mode, the RDAC0 data byte immediately

follows the acknowledgment of the slave address byte.

After an acknowledgement, RDAC1 follows, then RDAC2,

and so on. (There is a slight difference in write mode,

where the last eight data bits representing RDAC3 data are

followed by a no acknowledge bit.) Similarly, the transitions

on the SDA line must occur during the low period of SCL

and remain stable during the high period of SCL (see

Figure 34). Another reading method, random read

method, is shown in Figure 30.

on the same bus. The last LSB, the R/ bit, determines

W

whether data is read from or written to the slave device.

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is called an acknowledge bit). At

this stage, all other devices on the bus remain idle while

the selected device waits for data to be written to or read

from its serial register.

4. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line that

occurs while SCL is high. In write mode, the master pulls

the SDA line high during the 10^thclock pulse to establish a

stop condition (see Figure 33). In read mode, the master

issues a no acknowledge for the ninth clock pulse, that is,

the SDA line remains high. The master brings the SDA line

low before the 10^thclock pulse and then brings the SDA

line high to establish a stop condition (see Figure 34).

2. In the write mode (except when restoring EEMEM to the

RDAC register), there is an instruction byte that follows

the slave address byte. The MSB of the instruction byte is

labeled CMD/

. MSB = 1 enables CMD, the command

REG

instruction byte; MSB = 0 enables general register writing.

The third MSB in the instruction byte, labeled EE/

,

RDAC

is true when MSB = 0 or when the device is in general

writing mode. EE enables the EEMEM register, and REG

enables the RDAC register. The 5 LSB, A4 to A0, designates

Rev. D | Page 20 of 28

Data Sheet

AD5251/AD5252

THEORY OF OPERATION

The AD5251/AD5252 are dual-channel digital potentiometers

in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear

resistance step adjustments. The AD5251/AD5252 employ

double-gate CMOS EEPROM technology, which allows

resistance settings and user-defined data to be stored in the

EEMEM registers. The EEMEM is nonvolatile, such that

settings remain when power is removed. The RDAC wiper

settings are restored from the nonvolatile memory settings

during device power-up and can also be restored at any time

during operation.

In addition to the movement of data between RDAC and

EEMEM registers, the AD5251/AD5252 provide other shortcut

commands that facilitate programming, as shown in Table 11.

Table 11. Quick Commands

Command

Description

0

1

N O P.

Restore EEMEM content to RDAC. Users should

issue NOP immediately after this command to

conserve power.

2

3

4

5

Store RDAC register setting to EEMEM.

Decrement RDAC 6 dB (shift data bits right).

Decrement all RDACs 6 dB (shift all data bits right).

Decrement RDAC one step.

The AD5251/AD5252 resistor wiper positions are determined

by the RDAC register contents. The RDAC register acts like a

scratch-pad register, allowing unlimited changes of resistance

settings. RDAC register contents can be changed using the

device’s serial I²C interface. The format of the data-words and

the commands to program the RDAC registers are discussed in

the I²C Interface Detail Description section.

6

Decrement all RDACs one step.

7

8

9

10

Reset EEMEM contents to all RDACs.

Increment RDAC 6 dB (shift data bits left).

Increment all RDACs 6 dB (shift all data bits left).

Increment RDAC one step.

11

12 to 15

Increment all RDACs one step.

Reserved.

The four RDAC registers have corresponding EEMEM memory

locations that provide nonvolatile storage of resistor wiper position

settings. The AD5251/AD5252 provide commands to store the

RDAC register contents to their respective EEMEM memory

locations. During subsequent power-on sequences, the RDAC

registers are automatically loaded with the stored value.

LINEAR INCREMENT/DECREMENT COMMANDS

The increment and decrement commands (10, 11, 5, and 6) are

useful for linear step-adjustment applications. These commands

simplify microcontroller software coding by allowing the

controller to send just an increment or decrement command to

the AD5251/AD5252. The adjustments can be directed to a

single RDAC or to all four RDACs.

Whenever the EEMEM write operation is enabled, the device

activates the internal charge pump and raises the EEMEM cell

gate bias voltage to a high level; this essentially erases the current

content in the EEMEM register and allows subsequent storage

of the new content. Saving data to an EEMEM register consumes

about 35 mA of current and lasts approximately 26 ms. Because

of charge-pump operation, all RDAC channels may experience

noise coupling during the EEMEM writing operation.

6 dB ADJUSTMENTS

(DOUBLING/HALVING WIPER SETTING)

The AD5251/AD5252 accommodate 6 dB adjustments of

the RDAC wiper positions by shifting the register contents to

left/right for increment/decrement operations, respectively.

Command 3, Command 4, Command 8, and Command 9

can be used to increment or decrement the wiper positions in

6 dB steps synchronously or asynchronously.

The EEMEM restore time in power-up or during operation is

about 300 µs. Note that the power-up EEMEM refresh time

depends on how fast V_DDreaches its final value. As a result, any

supply voltage decoupling capacitors limits the EEMEM restore

time during power-up. For example, Figure 20 shows a power-

up profile of the V_DDwhere there is no decoupling capacitor and

the applied power is a digital signal. The device initially resets

the measured RDACs to midscale before restoring the EEMEM

contents. By default, EEMEM is loaded at midscale until a new

value is loaded. The omission of the decoupling capacitors

should only be considered when the fast restoring time is

absolutely needed in the application. In addition, users should

issue a NOP Command 0 immediately after using Command 1

to restore the EEMEM setting to RDAC, thereby minimizing

supply current dissipation. Reading user data directly from

EEMEM does not require a similar NOP command execution.

Incrementing the wiper position by +6 dB essentially doubles

the RDAC register value, whereas decrementing the wiper

position by –6 dB halves the register content. Internally, the

AD5251/AD5252 use shift registers to shift the bits left and

right to achieve a 6 dB increment or decrement. The maximum

number of adjustments is nine and eight steps for incrementing

from zero scale and decrementing from full scale, respectively.

These functions are useful for various audio/video level

adjustments, especially for white LED brightness settings in

which human visual responses are more sensitive to large

adjustments than to small adjustments.

Rev. D | Page 21 of 28

AD5251/AD5252

Data Sheet

Table 12. Multiple Devices Addressing

DIGITAL INPUT/OUTPUT CONFIGURATION

AD1

AD0

Device Addressed

SDA is a digital input/output with an open-drain MOSFET that

requires a pull-up resistor for proper communication. On the

0

1

0

1

0

1

U1

U2

U3

U4

other hand, SCL and

are digital inputs for which pull-up

WP

resistors are recommended to minimize the MOSFET cross-

conduction current when the driving signals are lower than

V_DD. SCL and

have ESD protection diodes, as shown in

WP

Figure 35 and Figure 36.

5V

R

P

can be permanently tied to V_DDwithout a pull-up resistor if

WP

the write-protect feature is not used. If

is left floating, an

WP

SDA

MASTER

internal current source pulls it low to enable write protection. In

applications in which the device is programmed infrequently,

this allows the part to default to write-protection mode after

any one-time factory programming or field calibration without

using an on-board pull-down resistor. Because there are

protection diodes on all inputs, the signal levels must not be

greater than V_DDto prevent forward biasing of the diodes.

SCL

5V

SDA SCL

AD1

AD0

AD1

U1

U2

U3

U4

AD0

Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus

TERMINAL VOLTAGE OPERATION RANGE

V

DD

The AD5251/AD5252 are designed with internal ESD diodes

for protection; these diodes also set the boundaries for the

terminal operating voltages. Positive signals present on

Terminal A, Terminal B, or Terminal W that exceed V_DDare

clamped by the forward-biased diode. Similarly, negative signals

on Terminal A, Terminal B, or Terminal W that are more

negative than V_SSare also clamped (see Figure 38). In practice,

users should not operate V_AB, V_WA, and V_WBto be higher than

the voltage across V_DDto V_SS, but V_AB, V_WA, and V_WBhave no

polarity constraint.

SCL

GND

Figure 35. SCL Digital Input

V

DD

V

DD

A

INPUTS

W

B

WP

V

SS

GND

Figure 38. Maximum Terminal Voltages Set by V_DDand V_SS

WP

Figure 36. Equivalent

Digital Input

POWER-UP AND POWER-DOWN SEQUENCES

MULTIPLE DEVICES ON ONE BUS

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 38), it is

important to power on V_DD/V_SSbefore applying any voltage to

these terminals. Otherwise, the diodes are forward biased such

that V_DD/V_SSare powered unintentionally and may affect the

user’s circuit. Similarly, V_DD/V_SSshould be powered down last.

The ideal power-up sequence is in the following order: GND,

V_DD, V_SS, digital inputs, and V_A/V_B/V_W. The order of powering

V_A, V_B, V_W, and the digital inputs is not important, as long as

they are powered after V_DD/V_SS.

The AD5251/AD5252 are equipped with two addressing pins,

AD1 and AD0, that allow up to four AD5251/AD5252 devices

to be operated on one I²C bus. To achieve this result, the states of

AD1 and AD0 on each device must first be defined. An example

is shown in Table 12 and Figure 37. In I²C programming, each

device is issued a different slave address—01011(AD1)(AD0)—

to complete the addressing.

Rev. D | Page 22 of 28

Data Sheet

AD5251/AD5252

SW

A

LAYOUT AND POWER SUPPLY BIASING

A

X

It is always a good practice to employ a compact, minimum

lead-length layout design. The leads to the input should be as

direct as possible, with a minimum conductor length. Ground

paths should have low resistance and low inductance.

N

SW(2 – 1)

W

X

R

S

RDAC

WIPER

N

SW(2 – 2)

REGISTER

AND

DECODER

Similarly, it is also good practice to bypass the power supplies

with quality capacitors. Low equivalent series resistance (ESR)

1 μF to 10 μF tantalum or electrolytic capacitors should be

applied at the supplies to minimize any transient disturbance

and filter low frequency ripple. Figure 39 illustrates the basic

supply-bypassing configuration for the AD5251/AD5252.

SW(1)

SW(0)

R

S

N

R

= R /2

AB

S

DIGITAL

SW

B

AD5251/AD5252

CIRCUITRY

OMITTED FOR

CLARITY

B

X

V

DD

V

DD

+

C1

C3

C4

Figure 40. Equivalent RDAC Structure

10F

0.1F

+

PROGRAMMABLE RHEOSTAT OPERATION

C2

10F

V

SS

V

If either the W-to-B or W-to-A terminal is used as a variable

resistor, the unused terminal can be opened or shorted with W;

such operation is called rheostat mode (see Figure 41). The

resistance tolerance can range 20%.

SS

GND

Figure 39. Power Supply-Bypassing Configuration

A

The ground pin of the AD5251/AD5252 is used primarily as a

digital ground reference. To minimize the digital ground

bounce, the AD5251/AD5252 ground terminal should be joined

remotely to the common ground (see Figure 39).

W

B

Figure 41. Rheostat Mode Configuration

DIGITAL POTENTIOMETER OPERATION

The nominal resistance of the AD5251/AD5252 has 64/256

contact points accessed by the wiper terminal, plus the B terminal

contact. The 6-/8-bit data-word in the RDAC register is decoded

to select one of the 64/256 settings. The wiper’s first connection

starts at the B terminal for Data 0x00. This B terminal connection

has a wiper contact resistance, R_W, of 75 Ω, regardless of the

nominal resistance. The second connection (the AD5251 10 kΩ

part) is the first tap point where R_WB= 231 Ω (R_WB= R_AB/64 +

R_W= 156 Ω + 75 Ω) for Data 0x01, and so on. Each LSB data

value increase moves the wiper up the resistor ladder until the

last tap point is reached at R_WB= 9893 Ω. See Figure 40 for a

simplified diagram of the equivalent RDAC circuit.

The structure of the RDAC is designed to emulate the

performance of a mechanical potentiometer. The RDAC

contains a string of resistor segments with an array of analog

switches that act as the wiper connection to the resistor array.

The number of points is the resolution of the device. For

example, the AD5251/AD5252 emulate 64/256 connection

points with 64/256 equal resistance, R_S, allowing them to

provide better than 1.5%/0.4% resolution.

Figure 40 provides an equivalent diagram of the connections

between the three terminals that make up one channel of the

RDAC. Switches SW_Aand SW_Bare always on, but only one of

switches SW(0) to SW(2^{N – 1}) can be on at a time (determined by

the setting decoded from the data bit). Because the switches are

nonideal, there is a 75 Ω wiper resistance, R_W. Wiper resistance

is a function of supply voltage and temperature: Lower supply

voltages and higher temperatures result in higher wiper

resistances. Consideration of wiper resistance dynamics is

important in applications in which accurate prediction of

output resistance is required.

The general equation that determines the digitally programmed

output resistance between W and B is

AD5251: R_WB(D) = (D/64) × R_AB+ 75 Ω

AD5252: R_WB(D) = (D/256) × R_AB+ 75 Ω

(1)

(2)

where:

D is the decimal equivalent of the data contained in the

RDAC latch.

R

_ABis the nominal end-to-end resistance.

Rev. D | Page 23 of 28

AD5251/AD5252

Data Sheet

100

PROGRAMMABLE POTENTIOMETER OPERATION

R

WB

WA

If all three terminals are used, the operation is called potenti-

ometer mode (see Figure 43); the most common configuration

is the voltage divider operation.

75

50

25

0

V

I

A

V

C

W

B

Figure 43. Potentiometer Mode Configuration

If the wiper resistance is ignored, the transfer function is simply

0

16

32

48

63

D (Code in Decimal)

D

64

AD5251: V_W

AD5252: V_W

=

×V_AB+V_B

(5)

(6)

Figure 42. AD5251 R_WA(D) and R_WB(D) vs. Decimal Code

D

256

×V_AB+V_B

Since the digital potentiometer is not ideal, a 75 Ω finite wiper

resistance is present that can easily be seen when the device is

programmed at zero scale. Because of the fine geometric and

interconnects employed by the device, care should be taken to

limit the current conduction between W and B to no more than

5 mA continuous for a total resistance of 1 kΩ or a pulse of

20 mA to avoid degradation or possible destruction of the

device. The maximum dc current for AD5251 and AD5252 are

shown in Figure 21and Figure 22, respectively.

A more accurate calculation that includes the wiper resistance

effect is

D

R_AB+ R_W

2^N

V_W(D) =

V_A

(7)

R_AB+ 2R_W

where 2^Nis the number of steps.

Similar to the mechanical potentiometer, the resistance of the

RDAC between Wiper W and Terminal A also produces a

digitally controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. The R_WA

starts at a maximum value and decreases as the data loaded into

the latch increases in value (see Figure 42). The general

equation for this operation is

Unlike in rheostat mode operation, where the tolerance is high,

potentiometer mode operation yields an almost ratiometric

function of D/2^Nwith a relatively small error contributed by the

R_Wterms. Therefore, the tolerance effect is almost cancelled.

Similarly, the ratiometric adjustment also reduces the

temperature coefficient effect to 50 ppm/°C, except at low value

codes where R_Wdominates.

AD5251: R_WA(D) = [(64 – D)/64] × R_AB+ 75 Ω

AD5252: R_WA(D) = [(256 – D)/256] × R_AB+ 75 Ω

The typical distribution of R_ABfrom channel-to-channel

matches is about 0.15% within a given device. On the other

hand, device-to-device matching is process-lot dependent with

(3)

(4)

Potentiometer mode operations include other applications, such

as op amp input, feedback-resistor networks, and other voltage-

scaling applications. The A, W, and B terminals can, in fact, be

input or output terminals, provided that |V_A|, |V_W|, and |V_B| do

not exceed V_DDto V_SS.

a

20% tolerance.

Rev. D | Page 24 of 28

Data Sheet

AD5251/AD5252

APPLICATIONS INFORMATION

LCD PANEL V_COMADJUSTMENT

U1

RDAC1

10kΩ

Large LCD panels usually require an adjustable V_COMvoltage

centered around 6 V to 8 V with 1 V swing and small steps

adjustment. This example represents common DAC appli-

cations where the window of adjustments is small and centered

at any level. High voltage and high resolution DACs can be

used, but it is far more cost-effective to use low voltage digital

potentiometers with level shifting, such as the AD5251 or

AD5252, to achieve the objective.

V

1

B

+5V

U2

V+

R

SENSE

0.1kΩ

AD8628

V

O

AD5252

V–

B

VREF

V

2

Assume a V_COMvoltage requirement of 6 V 1 V with a 20 mV

step adjustment, as shown in Figure 44. The AD5252 can be

configured in voltage divider mode with an op amp gain. With

20% tolerance accounted for by the AD5252, this circuit can

still be adjusted from 5 V to 7 V with an 8 mV/step in the

worst case.

RDAC3

10kΩ

Figure 45. Current-Sensing Amplifier

ADJUSTABLE HIGH POWER LED DRIVER

Figure 46 shows a circuit that can drive three or four high power

LEDs. The ADP1610 is an adjustable boost regulator that provides

adequate headroom and current for the LEDs. Because its FB pin

voltage is 1.2 V, the digital potentiometer AD5252 and the op amp

form an average gain of 12 feedback networks that servo the

sensing and feedback voltages. As a result, the voltage across

+14.4V

R1

350kΩ

±1%

U1

AD5252

+14.4V

R

_SETis regulated around 0.1 V, depending on the AD5252’s

setting. An adjustable LED current is

V

+5V

DD

R2

10kΩ

U2

6V ± 1V

V+

V–

±20%

V

COM

B

V_R

SET

I_LED

=

(9)

R_SET

R3

18.5kΩ

C1

2.2pF

R_SETshould be small enough to conserve power, but large enough

to limit the maximum LED current. R3 should be used in parallel

with the AD5252 to limit the LED current to an achievable range.

R5

1kΩ

R4

6kΩ

Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V 1 V Application

+5V

C2

10µF

U2

CURRENT-SENSING AMPLIFIER

L1

10µF

IN

ADP1610

The dual-channel, synchronous update, and channel-to-channel

resistance matching characteristics make the AD5251/AD5252

suitable for current-sensing applications, such as LED

brightness control. In the circuit shown in Figure 45, when

RDAC1 and RDAC3 are programmed to the same settings, it

can be shown that

D1

V

SD

SW

PWM

OUT

C3

10µF

FB

COMP

D1

D2

D3

R

SS

RT

GND

O

100kΩ

C

390pF

C

SS

10nF

D

V_o=

(

V₂−V₁

)

+V_REF

(8)

C8

0.1µF

+5V

2^N− D

U3

As a result, the current through a sense resistor connected

between V₁and V₂can be determined.

V+

AD8591

V–

R

SET

0.25kΩ

U1

The circuit can be programmed for use with systems that require

different sensitivities. If the op amp has very low offset and low

bias current, the major source of error comes from the digital

potentiometer channel-to-channel resistance mismatch, which

is typically 0.15%. The circuit accuracy is about 9 bits, which is

adequate for LED control and other general-purpose applications.

AD5252

U1

W

B

A

10kΩ

R2

1.1kΩ

R1

100Ω

R3

200Ω

Figure 46. High Power, Adjustable LED Driver

Rev. D | Page 25 of 28

AD5251/AD5252

Data Sheet

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. D | Page 26 of 28

Data Sheet

AD5251/AD5252

ORDERING GUIDE

Package

Option

Ordering

Quantity

Model^{1, 2}

Step

64

R_AB(kΩ)

1

Temperature Range

−40°C to +105°C

Package Description

14-Lead TSSOP

Evaluation Board

AD5251BRU1

AD5251BRU1-RL7

AD5251BRUZ1

RU-14

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

96

1,000

1

AD5251BRU10

10

50

100

1

AD5251BRU10-RL7

AD5251BRUZ10

AD5251BRU50-RL7

AD5251BRUZ50

AD5251BRU100-RL7

AD5251BRUZ100

AD5251BRUZ100-RL7

AD5252BRU1

AD5252BRU1-RL7

AD5252BRUZ1

AD5252BRUZ1-RL7

AD5252BRU10

AD5252BRU10-RL7

AD5252BRUZ10

AD5252BRUZ10-RL7

AD5252BRU50

AD5252BRU50-RL7

AD5252BRUZ50

AD5252BRUZ50-RL7

AD5252BRU100

AD5252BRU100-RL7

AD5252BRUZ100

AD5252BRUZ100-RL7

EVAL-AD5252SDZ

64

256

1

10

50

100

10

¹In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a

“#” marking for the Pb-free part. Line 3 shows the date code in YYWW.

²Z = RoHS Compliant Part.

Rev. D | Page 27 of 28

AD5251/AD5252

NOTES

Data Sheet

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D03823-0-9/12(D)

Rev. D | Page 28 of 28


型号：	AD5251BRUZ50
厂家：	ADI
描述：	Dual 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers 双64 / 256位I2C非易失性存储器数字电位器电位器存储
文件：	总28页 (文件大小：575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5251BRUZ50 [ADI]

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