AD5172BRMZ502_技术文档

256-Position, One-Time Programmable,

Dual-Channel, I²C Digital Potentiometers

AD5172/AD5173

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

A1

W1

B1

A2

W2

B2

2-channel, 256-position potentiometers

One-time programmable (OTP) set-and-forget resistance

setting provides a low cost alternative to EEMEM

Unlimited adjustments prior to OTP activation

OTP overwrite allows dynamic adjustments with user-

defined preset

FUSE

LINKS

V

DD

1

2

End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ

Compact 10-lead MSOP: 3 mm × 4.9 mm

Fast settling time: t_S= 5 μs typical on power-up

Full read/write of wiper register

Power-on preset to midscale

Extra package address decode pins: AD0 and AD1 (AD5173)

Single supply: 2.7 V to 5.5 V

RDAC

REGISTER 1

RDAC

REGISTER 2

GND

8

SDA

SCL

SERIAL INPUT

REGISTER

Figure 1. AD5172 Functional Block Diagram

Low temperature coefficient: 35 ppm/°C

Low power: I_DD= 6 μA maximum

W1

B1

W2

B2

Wide operating temperature: −40°C to +125°C

APPLICATIONS

FUSE

LINKS

Systems calibration

Electronics level setting

V

DD

1

2

Mechanical trimmers replacement in new designs

Permanent factory PCB setting

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

RDAC

REGISTER 1

RDAC

REGISTER 2

GND

AD0

AD1

ADDRESS

DECODE

8

RF amplifier biasing

Automotive electronics adjustment

Gain control and offset adjustment

SDA

SCL

SERIAL INPUT

REGISTER

Figure 2. AD5173 Functional Block Diagram

GENERAL DESCRIPTION

The AD5172/AD5173 are dual-channel, 256-position, one-time

programmable (OTP) digital potentiometers¹that employ fuse

link technology to achieve memory retention of resistance

settings. OTP is a cost-effective alternative to EEMEM for users

who do not need to program the digital potentiometer setting

in memory more than once. These devices perform the same

electronic adjustment function as mechanical potentiometers or

variable resistors but with enhanced resolution, solid-state reliabil-

ity, and superior low temperature coefficient performance.

before permanently setting the resistance value. During OTP

activation, a permanent blow fuse command freezes the wiper

position (analogous to placing epoxy on a mechanical trimmer).

Unlike traditional OTP digital potentiometers, the AD5172/

AD5173 have a unique temporary OTP overwrite feature that

allows for new adjustments even after a fuse is blown. However,

the OTP setting is restored during subsequent power-up condi-

tions. This allows users to treat these digital potentiometers as

volatile potentiometers with a programmable preset.

The AD5172/AD5173 are programmed using a 2-wire, I²C®-

compatible digital interface. Unlimited adjustments are allowed

¹The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5172/AD5173

TABLE OF CONTENTS

Features .............................................................................................. 1

Programming the Variable Resistor and Voltage................... 15

Programming the Potentiometer Divider............................... 16

ESD Protection ........................................................................... 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Power Supply Considerations................................................... 17

Layout Considerations............................................................... 18

I²C Interface .................................................................................... 19

Write Mode ................................................................................. 19

Read Mode .................................................................................. 19

I²C Controller Programming.................................................... 20

I²C-Compatible, 2-Wire Serial Bus.......................................... 21

Level Shifting for Different Voltage Operation...................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics: 2.5 kΩ ............................................... 3

Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ............. 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Test Circuits..................................................................................... 14

Theory of Operation ...................................................................... 15

One-Time Programming (OTP) .............................................. 15

REVISION HISTORY

4/09—Rev. G to Rev. H

Replaced I²C-Compatible, 2-Wire Serial Bus Section............... 21

Changes to Ordering Guide.......................................................... 23

6/06—Rev. C to Rev. D

Changes to Features ..........................................................................1

Changes to One-Time Programming (OTP) Section................ 15

Changes to Figure 44 and Figure 45............................................. 17

Changes to Power Supply Considerations Section .................... 18

Changes to Figure 46 and Figure 47............................................. 18

Changes to Device Programming Software Section.................. 19

Updated Outline Dimensions....................................................... 24

6/05—Rev. B to Rev. C

Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 ........3

Added Footnote 8 to Table 2............................................................5

Changes to Table 5 and Table 6 .......................................................9

Changes to Power Supply Considerations Section .................... 17

Changes to I²C-Compatible 2-Wire Serial Bus Section ............ 23

Added Level Shifting for Different Voltage Operation Section ......24

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide.......................................................... 25

10/04—Rev. A to Rev. B

Updated Format .................................................................Universal

Changes to Specifications.................................................................3

Changes to One-Time Programming (OTP) Section................ 13

Changes to Power Supply Considerations Section .................... 15

Changes to Figure 44 and Figure 45............................................. 15

Changes to Figure 46 and Figure 47............................................. 16

11/03—Rev. 0 to Rev. A

Changes to DC Characteristics—Rheostat Mode Parameter and

to DC Characteristics—Potentiometer Divider Mode Parameter,

Table 1 ................................................................................................ 3

12/08—Rev. F to Rev. G

Changes to OTP Supply Voltage Parameter, Table 1.................... 3

Changes to OTP Supply Voltage Parameter, Table 2.................... 5

Changes to Table 5 and Table 6....................................................... 8

Changes to One-Time Programming (OTP) Section................ 15

Changes to Power Supply Considerations Section, Figure 46,

and Figure 46 Caption.................................................................... 17

Changes to Ordering Guide .......................................................... 23

7/08—Rev. E to Rev. F

Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3

Updated Fuse Blow Condition to 400 ms Throughout ............... 5

1/08—Rev. D to Rev. E

Changes to Features.......................................................................... 1

Changes to General Description .................................................... 1

Changes to OTP Supply Voltage and OTP Supply Current in

Table 1 ................................................................................................ 3

Changes to OTP Supply Voltage and OTP Supply Current in

Table 2 ................................................................................................ 5

Added OTP Program Time in Table 3........................................... 6

Changes to Table 4............................................................................ 7

Changes to Table 5 and Table 6....................................................... 8

Inserted Figure 30........................................................................... 13

Replaced One-Time Programming (OTP) Section ................... 15

Replaced Power Supply Considerations Section ........................ 17

Deleted Device Programming Software Section........................ 20

Changes to Electrical Characteristics—2.5 kΩ..............................3

11/03—Revision 0: Initial Version

Rev. H | Page 2 of 24

AD5172/AD5173

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS: 2.5 kΩ

V_DD= 5 V 10%, or 3 V 10%ꢀ V_A= V_DDꢀ V_B= 0 Vꢀ −40°C < T_A< +125°Cꢀ unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB

(∆R_AB/R_AB)/∆T

R_WB

R_WB, V_A= no connect

T_A= 25°C

−2

−14

−2±

±±.1

±2

+2

+14

+55

LSB

%

ppm/°C

Ω

35

16±

Code = ±x±±, V_DD= 5 V

2±±

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

MODE⁴

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(ΔV_W/V_W)/ΔT

V_WFSE

V_WZSE

−1.5

−2

±±.1

±±.6

15

−5.5

4.5

+1.5

+2

LSB

ppm/°C

LSB

Code = ±x8±

Code = ±xFF

Code = ±x±±

−14

±

12

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁶

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance A, B⁷

f = 1 MHz, measured to

GND, code = ±x8±

f = 1 MHz, measured to

GND, code = ±x8±

45

6±

Capacitance W⁷

C_W

pF

Shutdown Supply Current⁸

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

I_{A_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

±.±1

1

μA

nA

Input Logic High⁹

V_IH

V_IL

V_DD= 5 V

±.7 V_DD

−±.5

V_DD+ ±.5

+±.3 V_DD

V

Input Logic Low⁹

AD± and AD1

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁷

V_IH

V_IL

I_IL

V_DD= 3 V

V_IN= ± V or 5 V

2.1

V

μA

pF

±.6

±1

C_IL

5

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage^{9, 1±}

Supply Current

OTP Supply Current^{9, 11, 12}

Power Dissipation¹³

Power Supply Sensitivity

V_{DD_RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.7

5.6

5.5

5.8

6

V

μA

mA

μW

%/%

T_A= 25°C

5.7

3.5

1±±

V_IH= 5 V or V_IL= ± V

V_{DD_OTP}= 5.± V, T_A= 25°C

V_IH= 5 V or V_IL= ± V, V_DD= 5 V

V_DD= 5 V ± 1±%,

code = midscale

33

PSS

±±.±2 ±±.±8

DYNAMIC CHARACTERISTICS¹⁴

Bandwidth, −3 dB

Total Harmonic Distortion

BW

THD_W

Code = ±x8±

V_A= 1 V rms, V_B= ± V,

f = 1 kHz

4.8

±.1

MHz

%

Rev. H | Page 3 of 24

AD5172/AD5173

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

V_WSettling Time

t_S

V_A= 5 V, V_B= ± V, ±1 LSB

error band

1

μs

Resistor Noise Voltage Density

e_{N_WB}

R_WB= 1.25 kΩ, R_S= ± Ω

3.2

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, V_B= ± V, wiper (V_W) = no connect.

⁴Specifications apply to all VRs.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= ± V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

⁷Guaranteed by design, but not subject to production test.

⁸Measured at Terminal A. Terminal A is open circuited in shutdown mode.

⁹The minimum voltage requirement on the V_IHis ±.7 V × V_DD. For example, V_IHminimum = 3.5 V when V_DD= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V_DD

.

However, care must be taken to ensure that the minimum V_IHis met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

^1±Different from the operating power supply; the power supply for OTP is used one time only.

¹¹Different from the operating current; the supply current for OTP lasts approximately 4±± ms for one time only.

¹²See Figure 3± for an energy plot during an OTP program.

13

P

is calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

DISS

¹⁴All dynamic characteristics use V_DD= 5 V.

ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ

V_DD= 5 V 10% or 3 V 10%ꢀ V_A= V_DDꢀ V_B= 0 Vꢀ −40°C < T_A< +125°Cꢀ unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

ΔR_AB

(ΔR_AB/R_AB)/ΔT

R_WB

R_WB, V_A= no connect

T_A= 25°C

−1

−2.5

−2±

±±.1

±±.25

+1

+2.5

+2±

LSB

%

ppm/°C

Ω

35

16±

Code = ±x±±, V_DD= 5 V

2±±

DC CHARACTERISTICS—POTENTIOMETER DIVIDER

MODE⁴

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(ΔV_W/V_W)/ΔT

V_WFSE

V_WZSE

−1

±±.1

±±.3

15

−1

1

+1

LSB

ppm/°C

LSB

Code = ±x8±

Code = ±xFF

Code = ±x±±

−2.5

±

2.5

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁶

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance A, B⁷

f = 1 MHz, measured to

GND, code = ±x8±

f = 1 MHz, measured to

GND, code = ±x8±

45

6±

Capacitance W⁷

C_W

pF

Shutdown Supply Current⁸

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

SDA and SCL

I_{A_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

±.±1

1

μA

nA

Input Logic High⁹

Input Logic Low⁹

V_IH

V_IL

V_DD= 5 V

±.7 V_DD

−±.5

V_DD+ ±.5

+±.3 V_DD

V

AD± and AD1

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁷

V_IH

V_IL

I_IL

V_DD= 3 V

V_IN= ± V or 5 V

2.1

V

μA

pF

±.6

±1

C_IL

5

Rev. H | Page 4 of 24

AD5172/AD5173

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage^{9, 1±}

Supply Current

OTP Supply Current^{9, 11, 12}

Power Dissipation¹³

V_{DD_RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.7

5.6

5.5

5.8

6

V

μA

mA

μW

T_A= 25°C

V_IH= 5 V or V_IL= ± V

V_{DD_OTP}= 5.± V, T_A= 25°C

V_IH= 5 V or V_IL= ± V,

V_DD= 5 V

5.7

3.5

1±±

33

Power Supply Sensitivity

PSS

V_DD= 5 V ± 1±%,

code = midscale

±±.±2

±±.±8

%/%

DYNAMIC CHARACTERISTICS¹⁴

Bandwidth, −3 dB

BW

R_AB= 1± kΩ, code = ±x8±

R_AB= 5± kΩ, code = ±x8±

R_AB= 1±± kΩ, code = ±x8±

V_A= 1 V rms, V_B= ± V,

f = 1 kHz, R_AB= 1± kΩ

V_A= 5 V, V_B= ± V, ±1 LSB

error band

R_WB= 5 kΩ, R_S= ± Ω

6±±

1±±

4±

kHz

%

Total Harmonic Distortion

V_WSettling Time

THD_W

t_S

±.1

2

9

μs

Resistor Noise Voltage Density

e_{N_WB}

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, V_B= ± V, wiper (V_W) = no connect.

⁴Specifications apply to all VRs.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= ± V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

⁷Guaranteed by design, but not subject to production test.

⁸Measured at Terminal A. Terminal A is open circuited in shutdown mode.

⁹The minimum voltage requirement on the V_IHis ±.7 V × V_DD. For example, V_IHminimum = 3.5 V when V_DD= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V_DD

.

However, care must be taken to ensure that the minimum V_IHis met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

^1±Different from the operating power supply; the power supply for OTP is used one time only.

¹¹Different from the operating current; the supply current for OTP lasts approximately 4±± ms for one time only.

¹²See Figure 3± for an energy plot during an OTP program.

13

P

is calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

DISS

¹⁴All dynamic characteristics use V_DD= 5 V.

Rev. H | Page 5 of 24

AD5172/AD5173

TIMING CHARACTERISTICS

V_DD= 5 V 10%, or 3 V 10%ꢀ V_A= V_DDꢀ V_B= 0 Vꢀ −40°C < T_A< +125°Cꢀ unless otherwise noted.

Table 3.

Parameter

I²C INTERFACE TIMING CHARACTERISTICS¹

Symbol

Conditions

Min

Typ

Max

Unit

SCL Clock Frequency

Bus-Free Time Between Stop and Start, t_BUF

Hold Time (Repeated Start), t_HD;STA

f_SCL

t₁

t₂

4±±

kHz

μs

1.3

±.6

After this period, the first clock

pulse is generated.

Low Period of SCL Clock, t_LOW

High Period of SCL Clock, t_HIGH

t₃

t₄

t₅

t₆

t₇

t₈

t₉

t_1±

t₁₁

1.3

±.6

μs

ns

μs

ms

Setup Time for Repeated Start Condition, t_SU;STA

2

Data Hold Time, t_HD;DAT

±.9

Data Setup Time, t_SU;DAT

1±±

±.6

Fall Time of Both SDA and SCL Signals, t_F

Rise Time of Both SDA and SCL Signals, t_R

Setup Time for Stop Condition, t_SU;STO

OTP Program Time

3±±

4±±

¹See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).

²The maximum t_HD;DAThas to be met only if the device does not stretch the low period (t_LOW) of the SCL signal.

Timing Diagram

t₂

t₈

t₆

t₉

SCL

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

SDA

t₁

P

S

P

Figure 3. I²C Interface Detailed Timing Diagram

Rev. H | Page 6 of 24

AD5172/AD5173

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Parameter

V_DDto GND

V_A, V_B, V_Wto GND

Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx¹

Pulsed

Continuous

Digital Inputs and Output Voltage to GND

Operating Temperature Range

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating onlyꢀ functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−±.3 V to +7 V

V_DD

±2± mA

±5 mA

± V to 7 V

−4±°C to +125°C

15±°C

Maximum Junction Temperature (T_JMAX

Storage Temperature Range

Reflow Soldering

)

ESD CAUTION

−65°C to +15±°C

Peak Temperature

26±°C

Time at Peak Temperature

Thermal Resistance²

2± sec to 4± sec

θ_JAfor 1±-Lead MSOP

2±±°C/W

¹The maximum terminal current is bound by the maximum current handling

of the switches, the maximum power dissipation of the package, and the

maximum applied voltage across any two of the A, B, and W terminals at a

given resistance.

²The package power dissipation is (T_JMAX− T_A)/θ_JA

.

Rev. H | Page 7 of 24

AD5172/AD5173

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

10 W1

B1

AD0

W2

1

2

3

4

5

10 W1

B1

A1

9

8

7

6

B2

9

8

7

6

B2

AD5172

TOP VIEW

(Not to Scale)

AD5173

TOP VIEW

(Not to Scale)

AD1

SDA

SCL

W2

A2

GND

SDA

SCL

V

DD

Figure 4. AD5172 Pin Configuration

Figure 5. AD5173 Pin Configuration

Table 5. AD5172 Pin Function Descriptions

Table 6. AD5173 Pin Function Descriptions

No. Mnemonic Description

1

2

3

4

5

B1

A1

W2

GND

V_DD

B1 Terminal. GND ≤ V_B1≤ V_DD.

A1 Terminal. GND ≤ V_A1≤ V_DD.

W2 Terminal. GND ≤ V_W2≤ V_DD.

Digital Ground.

Positive Power Supply. Specified for

operation from 2.7 V to 5.5 V. For OTP

programming, V_DDneeds to be a minimum

of 5.6 V but no more than 5.8 V and to be

capable of driving 1±± mA.

Serial Clock Input. Positive-edge triggered.

Requires a pull-up resistor. If this pin is driven

directly from a logic controller without a

pull-up resistor, ensure that the V_IHminimum

is ±.7 V × V_DD.

Serial Data Input/Output. Requires a pull-up

resistor. If this pin is driven directly from a

logic controller without a pull-up resistor,

ensure that the V_IHminimum is ±.7 V × V_DD.

1

2

B1

AD±

B1 Terminal. GND ≤ V_B1≤ V_DD.

Programmable Address Bit ± for Multiple

Package Decoding.

W2 Terminal. GND ≤ V_W2≤ V_DD.

Digital Ground.

Positive Power Supply. Specified for

operation from 2.7 V to 5.5 V. For OTP

programming, V_DDneeds to be a minimum

of 5.6 V but no more than 5.8 V and to be

capable of driving 1±± mA.

Serial Clock Input. Positive-edge triggered.

Requires a pull-up resistor. If this pin is driven

directly from a logic controller without a

pull-up resistor, ensure that the V_IHminimum

is ±.7 V × V_DD.

Serial Data Input/Output. Requires a pull-up

resistor. If this pin is driven directly from a

logic controller without a pull-up resistor,

ensure that the V_IHminimum is ±.7 V × V_DD.

Programmable Address Bit 1 for Multiple

Package Decoding.

B2 Terminal. GND ≤ V_B2≤ V_DD.

W1 Terminal. GND ≤ V_W1≤ V_DD.

3

4

5

W2

GND

V_DD

6

7

SCL

6

SCL

SDA

7

8

SDA

AD1

8

9

1±

A2

B2

W1

A2 Terminal. GND ≤ V_A2≤ V_DD.

B2 Terminal. GND ≤ V_B2≤ V_DD.

W1 Terminal. GND ≤ V_W1≤ V_DD.

9

1±

B2

W1

Rev. H | Page 8 of 24

AD5172/AD5173

TYPICAL PERFORMANCE CHARACTERISTICS

0.5

0.4

2.0

T

= 25°C

R

= 10kΩ

A

AB

R

= 10kΩ

AB

1.5

1.0

0.3

V

= 2.7V

DD

0.2

0.5

0.1

V

= 2.7V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0

V

= 5.5V

DD

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 6. R-INL vs. Code vs. Supply Voltages

Figure 9. DNL vs. Code vs. Temperature

1.0

0.8

0.5

0.4

T

R

= 25°C

T

R

= 25°C

A

= 10kΩ

AB

0.6

0.3

0.4

0.2

V

= 2.7V

DD

V

= 5.5V

0.2

DD

0.1

0

V

= 2.7V

–0.2

–0.4

–0.6

–0.8

–1.0

DD

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 10. INL vs. Code vs. Supply Voltages

Figure 7. R-DNL vs. Code vs. Supply Voltages

0.5

0.4

0.5

0.4

T

R

= 25°C

R

= 10kΩ

A

AB

= 10kΩ

AB

0.3

V

= 5.5V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0.2

0.1

V

= 2.7V

DD

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

V

= 2.7V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 8. INL vs. Code vs. Temperature

Figure 11. DNL vs. Code vs. Supply Voltages

Rev. H | Page 9 of 24

AD5172/AD5173

4.50

3.75

3.00

2.25

1.50

0.75

0

2.0

R

= 10kΩ

R

= 10kΩ

AB

1.5

1.0

V

= 2.7V

DD

= –40°C, +25°C, +85°C, +125°C

T

A

0.5

0

V

= 2.7V, V = 2.7V

A

DD

V

= 5.5V

DD

–0.5

–1.0

–1.5

–2.0

T

= –40°C, +25°C, +85°C, +125°C

A

V

= 5.5V, V = 5.0V

A

DD

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 12. R-INL vs. Code vs. Temperature

Figure 15. Zero-Scale Error vs. Temperature

0.5

0.4

10

R

= 10kΩ

AB

0.3

V

= 5V

DD

0.2

V

= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0.1

0

1

–0.1

–0.2

–0.3

–0.4

–0.5

= 3V

DD

0.1

–40

0

32

64

96

128

160

192

224

256

–7

26

59

92

125

TEMPERATURE (°C)

CODE (DECIMAL)

Figure 13. R-DNL vs. Code vs. Temperature

Figure 16. Supply Current vs. Temperature

120

100

80

2.0

1.5

R

= 10kΩ

R

= 10kΩ

AB

1.0

0.5

60

V

= 2.7V

DD

T

= –40°C TO +85°C, –40°C TO +125°C

A

0

V

= 5.5V, V = 5.0V

A

DD

40

V

= 5.5V

DD

–0.5

–1.0

–1.5

–2.0

T

= –40°C TO +85°C, –40°C TO +125°C

A

20

V

= 2.7V, V = 2.7V

A

DD

0

–20

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

CODE (DECIMAL)

Figure 14. Full-Scale Error vs. Temperature

Figure 17. Rheostat Mode Tempco ΔR_WB/ΔT vs. Code

Rev. H | Page 1± of 24

AD5172/AD5173

0

–6

50

40

R

= 10kΩ

AB

0x80

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

30

V

T

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

20

A

0x08

0x04

0x02

0x01

10

0

–10

–20

–30

V

= 5.5V

DD

T

= –40°C TO +85°C, –40°C TO +125°C

A

0

32

64

96

128

160

192

224

256

1k

10k

100k

1M

CODE (DECIMAL)

FREQUENCY (Hz)

Figure 18. AD5172 Potentiometer Mode Tempco ΔV_WB/ΔT vs. Code

Figure 21. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

0

–6

0x80

0x40

0x20

0x80

0x40

0x20

–6

–12

–18

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

–24

0x08

0x04

–30

–36

0x02 0x01

–42

–48

–54

–60

10k

100k

FREQUENCY (Hz)

1M

10M

1k

10k

100k

FREQUENCY (Hz)

1M

Figure 19. Gain vs. Frequency vs. Code, R_AB= 2.5 kΩ

Figure 22. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

0

–6

0

0x80

0x40

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

100kΩ

60kHz

0x20

0x10

0x08

0x04

50kΩ

120kHz

10kΩ

570kHz

2.5kΩ

2.2MHz

0x02

0x01

1k

10k

100k

1M

10M

1k

10k

100k

FREQUENCY (Hz)

1M

FREQUENCY (Hz)

Figure 23. −3 dB Bandwidth at Code = 0x80

Figure 20. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

Rev. H | Page 11 of 24

AD5172/AD5173

10

T

= 25°C

A

1

V

= 5.5V

DD

V

W2

0.1

V

= 2.7V

DD

W1

0.01

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 24. Supply Current vs. Digital Input Voltage

Figure 27. Analog Crosstalk

V

W

SCL

Figure 25. Digital Feedthrough

Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F

V

W2

W

V

SCL

W1

Figure 26. Digital Crosstalk

Figure 29. Large-Signal Settling Time

Rev. H | Page 12 of 24

AD5172/AD5173

T

CHANNEL 1

MAXIMUM:

103mA

CHANNEL 1

MINIMUM:

–1.98mA

1

CH1 20.0mA

M 200ns

A CH1

32.4mA

T

588.000ns

Figure 30. OTP Program Energy for Single Fuse

Rev. H | Page 13 of 24

AD5172/AD5173

TEST CIRCUITS

Figure 31 to Figure 38 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2).

A

DUT

A

V+ = V

DD

1LSB = V+/2

+5V

DUT

N

W

V

IN

W

V+

AD8610

–5V

V

OUT

OFFSET

GND

B

V

B

MS

2.5V

Figure 31. Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 35. Test Circuit for Gain vs. Frequency

NC

0.1V

R

=

SW

I

DUT

SW

CODE = 0x00

DUT

B

I

W

A

W

0.1V

I

B

SW

V

MS

GND TO V

DD

NC = NO CONNECT

Figure 36. Incremental On Resistance

Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL)

NC

DUT

V

DD

I

A

B

CM

W

DUT

I

= V /R

NOMINAL

DD

W

A

V

GND

W

V

W

CM

V

MS2

B

NC

NC = NO CONNECT

V

R

= [V

– V

]/I

W

MS2

MS1

W

MS1

Figure 33. Wiper Resistance

Figure 37. Common-Mode Leakage Current

A1

A2

V

DD

RDAC1

RDAC2

W2

V

A

W1

V+ = V ± 10%

DD

V

NC

OUT

DUT

ΔV

MS

V

IN

PSRR (dB) = 20 log

(

)

B2

V

DD

SS

DD

A

B1

Δ

V

%

MS

ΔV

W

V+

PSS (%/%) =

%

DD

B

V

MS

CTA = 20 log[V ]

/V

NC = NO CONNECT

OUT IN

Figure 38. Analog Crosstalk

Figure 34. Power Supply Sensitivity (PSS, PSSR)

Rev. H | Page 14 of 24

AD5172/AD5173

THEORY OF OPERATION

A

SCL

SDA

DECODER

MUX

DAC

REG

2

I C INTERFACE

W

B

COMPARATOR

FUSES

EN

FUSE

REG

ONE-TIME

PROGRAM/TEST

CONTROL BLOCK

Figure 39. Detailed Functional Block Diagram

The AD5172/AD5173 are 256-position, digitally controlled

variable resistors (VRs) that employ fuse link technology to

achieve memory retention of the resistance setting.

Table 7. Validation Status

E1

E0

Status

±

Ready for programming.

An internal power-on preset places the wiper at midscale

during power-on. If the OTP function is activated, the device

powers up at the user-defined permanent setting.

1

±

Fatal error. Some fuses are not blown. Do not retry.

Discard this unit.

Successful. No further programming is possible.

1

ONE-TIME PROGRAMMING (OTP)

PROGRAMMING THE VARIABLE RESISTOR AND

VOLTAGE

Rheostat Operation

Prior to OTP activation, the AD5172/AD5173 presets to midscale

during initial power-on. After the wiper is set to the desired

position, the resistance can be permanently set by programming

the T bit high, with the proper coding (see Table 8 and Table 9),

and one-time V_{DD_OTP}. The fuse link technology of the AD517x

family of digital potentiometers requires V_{DD_OTP}to be between

5.6 V and 5.8 V to blow the fuses to achieve a given nonvolatile

setting. However, during operation, V_DDcan be 2.7 V to 5.5 V. As a

result, an external supply is required for one-time programming.

The user is allowed only one attempt to blow the fuses. If the user

fails to blow the fuses during this attempt, the structure of the

fuses can change such that they may never be blown, regardless

of the energy applied during subsequent events. For details, see

the Power Supply Considerations section.

The nominal resistance of the RDAC between Terminal A and

Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.

The nominal resistance (R_AB) of the VR has 256 contact points

accessed by the wiper terminal and the B terminal contact. The

8-bit data in the RDAC latch is decoded to select one of the

256 possible settings.

A

W

B

Figure 40. Rheostat Mode Configuration

The device control circuit has two validation bits, E1 and E0,

that can be read back to check the programming status (see

Table 7). Users should always read back the validation bits to

ensure that the fuses are properly blown. After the fuses are

blown, all fuse latches are enabled upon subsequent power-onꢀ

therefore, the output corresponds to the stored setting. Figure 39

shows a detailed functional block diagram.

Assuming a 10 kΩ part is used, the first connection of the wiper

starts at the B terminal for Data 0x00. Because there is a 50 Ω

wiper contact resistance, such a connection yields a minimum

of 100 Ω (2 × 50 Ω) resistance between Terminal W and Ter-

minal B. The second connection is the first tap point, which

corresponds to 139 Ω (R_WB= R_AB/256 + 2 × R_W= 39 Ω + 2 ×

50 Ω) for Data 0x01. The third connection is the next tap point,

representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so

on. Each LSB data value increase moves the wiper up the resistor

ladder until the last tap point is reached at 10,100 Ω (R_AB+ 2 × R_W).

Rev. H | Page 15 of 24

AD5172/AD5173

A

When R_ABis 10 kΩ and the B terminal is open circuited, the

output resistance, R_WA, is set according to the RDAC latch

codes, as listed in Table 9.

R

S

R

D7

D6

D5

D4

D3

D2

D1

D0

S

Table 9. Codes and Corresponding R_WAResistance

D (Dec)

R_WA(Ω)

Output State

Full scale

Midscale

1 LSB

255

128

1

139

5±6±

9961

W

±

1±,±6±

Zero scale

Typical device-to-device matching is process-lot dependent

and can vary up to 30%. Because the resistance element is

processed using thin-film technology, the change in R_ABwith

temperature has a very low temperature coefficient of 35 ppm/°C.

R

RDAC

S

LATCH

AND

DECODER

B

PROGRAMMING THE POTENTIOMETER DIVIDER

Figure 41. AD5172/AD5173 Equivalent RDAC Circuit

Voltage Output Operation

The general equation that determines the digitally programmed

output resistance between W and B is

The digital potentiometer easily generates a voltage divider at

wiper to B and at wiper to A, proportional to the input voltage

at A to B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

D

128

R_WB(D) =

×R_AB+2×R_W

(1)

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

V

I

A

R

_ABis the end-to-end resistance.

W

V

O

R_Wis the wiper resistance contributed by the on resistance of

the internal switch.

B

In summary, if R_ABis 10 kΩ and the A terminal is open circuited,

the output resistance, R_WB, is set according to the RDAC latch

codes, as listed in Table 8.

Figure 42. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper to B, starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the vol-

tage applied across Terminal A and Terminal B divided by the

256 positions of the potentiometer divider. The general equation

defining the output voltage at V_Wwith respect to ground for any

valid input voltage applied to Terminal A and Terminal B is

Table 8. Codes and Corresponding R_WBResistance

D (Dec)

R_WB(Ω)

9961

5±6±

139

Output State

255

128

1

Full scale (R_AB– 1 LSB + R_W)

Midscale

1 LSB

±

1±±

Zero scale (wiper contact resistance)

D

256

256 − D

256

V_W(D) =

V_A+

V_B

(3)

Note that in the zero-scale condition, a finite wiper resistance of

100 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of

no more than 20 mA. Otherwise, degradation or possible destruc-

tion of the internal switch contact may occur.

A more accurate calculation, which includes the effect of wiper

resistance, V_W, is

R_WB(D)

R_AB

R_WA(D)

R_AB

V_W(D) =

V_A+

V_B

(4)

Similar to the mechanical potentiometer, the resistance of the

RDAC between Wiper W and Terminal A also produces a digi-

tally controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

Operation of the digital potentiometer in the divider mode

results in more accurate operation over temperature. Unlike in

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors, R_WAand R_WB, not on the absolute

values. Therefore, the temperature drift reduces to 15 ppm/°C.

256– D

128

R

_WA(D) =

×R_AB+ 2×R_W

(2)

Rev. H | Page 16 of 24

AD5172/AD5173

rack-mount power supply) must be rated at 5.6 V to 5.8 V and

must be able to provide a 100 mA transient current for 400 ms

for successful one-time programming. When programming

is completed, the V_{DD_OTP}supply must be removed to allow

normal operation at 2.7 V to 5.5 Vꢀ the device consumes only

microamps of current.

ESD PROTECTION

All digital inputs, SDA, SCL, AD0, and AD1, are protected with

a series input resistor and parallel Zener ESD structures, as

shown in Figure 43 and Figure 44.

340Ω

LOGIC

APPLY FOR OTP ONLY

5.7V

R1

GND

10kΩ

Figure 43. ESD Protection of Digital Pins

V

2.7V

DD

C1

10µF

C2

0.1µF

A, B, W

P1

P2

AD5172/

AD5173

P1 = P2 = FDV302P, NDS0610

GND

Figure 44. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply

The AD5172/AD5173 V_DDto GND power supply defines the

boundary conditions for proper 3-terminal digital potenti-

ometer operation. Supply signals present on Terminal A,

Terminal B, and Terminal W that exceed V_DDor GND are

clamped by the internal forward-biased diodes (see Figure 45).

For example, for those who operate their systems at 2.7 V, use of

the bidirectional, low threshold, P-channel MOSFETs is recom-

mended for the isolation of the supply. As shown in Figure 46,

this assumes that the 2.7 V system voltage is applied first and

that the P1 and P2 gates are pulled to ground, thus turning on

P1 and then P2. As a result, V_DDof the AD5172/AD5173

approaches 2.7 V. When the AD5172/AD5173 setting is found,

the factory tester applies the V_{DD_OTP}to both the V_DDand the

MOSFET gates, thus turning P1 and P2 off. To program the

AD5172/AD5173 while the 2.7 V source is protected, execute

the OTP command at this time. When the OTP is completed,

the tester withdraws the V_{DD_OTP}, and the setting of the AD5172

or AD5173 is fixed permanently.

V

DD

A

W

B

GND

Figure 45. Maximum Terminal Voltages Set by V_DDand GND

The AD5172/AD5173 achieve the OTP function by blowing

internal fuses. Always apply the 5.6 V to 5.8 V one-time pro-

gram voltage requirement at the first fuse programming attempt.

Failure to comply with this requirement may lead to changing

the fuse structures, rendering programming inoperable.

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 45), it

is important to power V_DD/GND before applying voltage to

Terminal A, Terminal B, and Terminal W. Otherwise, the diode

is forward-biased such that V_DDis powered unintentionally and

may affect the rest of the user’s circuit. The ideal power-up

sequence is GND, V_DD, digital inputs, and then V_A/V_B/V_W. The

relative order of powering V_A, V_B, V_W, and the digital inputs is

not important, as long as they are powered after V_DD/GND.

Care should be taken when SCL and SDA are driven from a low

voltage logic controller. Users must ensure that the logic high

level is between 0.7 V × V_DDand V_DD+ 0.5 V.

Poor PCB layout introduces parasitics that can affect fuse

programming. Therefore, it is recommended to add a 1 μF to

10 μF tantalum capacitor in parallel with a 1 nF ceramic capacitor

as close as possible to the VDD pin. The type and value chosen for

both capacitors are important. These capacitors work together to

provide both fast responsiveness and large supply current handling

with minimum supply droop during transients. As a result,

these capacitors increase the OTP programming success by not

inhibiting the proper energy needed to blow the internal fuses.

Additionally, C1 minimizes transient disturbance and low

frequency ripple, whereas C2 reduces high frequency noise

during normal operation.

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time pro-

gramming and normal operating voltage supplies are applied to

the same V_DDterminal of the device. The AD5172/AD5173

employ fuse link technology that requires 5.6 V to 5.8 V to blow

the internal fuses to achieve a given setting, but normal V_DDcan

be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation

between the supplies if V_DDis lower than the required V_{DD_OTP}

The fuse programming supply (either an on-board regulator or

.

Rev. H | Page 17 of 24

AD5172/AD5173

LAYOUT CONSIDERATIONS

In PCB layout, it is a good practice to employ compact, minimum

lead length design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths should

have low resistance and low inductance.

V

DD

+

C1

C2

10µF 0.1µF

AD5172

Note that the digital ground should also be joined remotely to

the analog ground at one point to minimize the ground bounce.

GND

Figure 47. Power Supply Bypassing

Rev. H | Page 18 of 24

AD5172/AD5173

I²C INTERFACE

WRITE MODE

Table 10. AD5172 Write Mode

W

S

0

1

0

1

A

A0 SD

T

0

OW

X

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Slave address byte

Instruction byte

Data byte

Table 11. AD5173 Write Mode

AD1 AD0

Slave address byte

W

S

0

1

0

1

A

A0 SD

T

0

OW

X

A

D7 D6 D5 D4 D3 D2 D1 D0

Instruction byte

Data byte

READ MODE

Table 12. AD5172 Read Mode

S

0

1

0

1

R

A

D7 D6 D5 D4 D3 D2 D1 D0

A

E1 E0

X

A

P

Slave address byte

Instruction byte

Data byte

Table 13. AD5173 Read Mode

AD1 AD0

Slave address byte

S

0

1

0

1

R

A

D7 D6 D5 D4 D3 D2 D1 D0

A

E1 E0

X

Instruction byte

Data byte

Table 14. SDA Bits Descriptions

Bit

Description

S

P

A

Start condition.

Stop condition.

Acknowledge.

AD±, AD1

X

Package pin-programmable address bits.

Don’t care.

W

R

Write.

Read.

A±

SD

RDAC subaddress select bit.

Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the

contents of the wiper register.

T

OTP programming bit. Logic 1 programs the wiper permanently.

OW

Overwrites the fuse setting and programs the digital potentiometer to a different setting. Upon

power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on

whether the fuse link was blown.

D7, D6, D5, D4, D3, D2, D1, D±

E1, E±

Data bits.

OTP validation bits.

±± = ready to program.

1± = fatal error. Some fuses not blown. Do not retry. Discard this unit.

11 = programmed successfully. No further adjustments are possible.

Rev. H | Page 19 of 24

AD5172/AD5173

I²C CONTROLLER PROGRAMMING

Write Bit Patterns

1

9

1

9

1

9

SCL

0

1

0

1

R/W

A0 SD

T

0

OW

X

D7 D6 D5 D4 D3 D2 D1 D0

SDA

ACK BY

AD5172

ACK BY

AD5172

ACK BY

AD5172

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 48. Writing to the RDAC Register—AD5172

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

A0 SD

T

0

OW

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5173

ACK BY

AD5173

ACK BY

AD5173

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 49. Writing to the RDAC Register—AD5173

Read Bit Patterns

1

9

1

9

1

9

SCL

SDA

0

1

0

1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0

X

NO ACK

BY MASTER

ACK BY

AD5172

ACK BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 50. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0

X

NO ACK

BY MASTER

ACK BY

AD5173

ACK BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 51. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173

Rev. H | Page 2± of 24

AD5172/AD5173

I²C-COMPATIBLE, 2-WIRE SERIAL BUS

This section describes how the 2-wire, I²C-compatible serial bus

protocol operates.

After acknowledging the instruction byte, the last byte in write

mode is the data byte. Data is transmitted over the serial bus in

sequences of nine clock pulses (eight data bits followed by an

acknowledge bit). The transitions on the SDA line must occur

during the low period of SCL and remain stable during the high

period of SCL (see Figure 3).

The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high (see Figure 48 and Figure 49).

The following byte is the slave address byte, which consists of

In read mode, the data byte follows immediately after the

acknowledgment of the slave address byte. Data is transmitted

over the serial bus in sequences of nine clock pulses (a slight

difference from the write mode, where there are eight data bits

followed by an acknowledge bit). Similarly, transitions on the

SDA line must occur during the low period of SCL and remain

stable during the high period of SCL (see Figure 50 and Figure 51).

W

the slave address followed by an R/ bit (this bit determines

whether data is read from or written to the slave device). The

AD5172 has a fixed slave address byte, whereas the AD5173

has two configurable address bits, AD0 and AD1 (see Figure 48

and Figure 49).

The slave whose address corresponds to the transmitted address

responds by pulling the SDA line low during the ninth clock

pulse (this is called the acknowledge bit). At this stage, all other

devices on the bus remain idle while the selected device waits

for data to be written to or read from its serial register. If the

Note that the channel of interest is the one that is previously

selected in write mode. If users need to read the RDAC values

of both channels, they must program the first channel in write

mode and then change to read mode to read the first channel

value. After that, the user must return to write mode with the

second channel selected and read the second channel value in

read mode. It is not necessary for users to issue the Frame 3

data byte in write mode for subsequent readback operations.

Refer to Figure 50 and Figure 51 for the programming format.

W

R/ bit is high, the master reads from the slave device. If the

W

R/ bit is low, the master writes to the slave device.

In write mode, the second byte is the instruction byte. The first

bit (MSB) of the instruction byte is the RDAC subaddress select

bit. Logic low selects Channel 1ꢀ logic high selects Channel 2.

Following the data byte, the validation byte contains two valida-

tion bits, E0 and E1 (see Table 7). These bits signify the status of

the one-time programming (see Figure 50 and Figure 51).

The second MSB, SD, is a shutdown bit. A logic high causes an

open circuit at Terminal A while shorting the wiper to Terminal B.

This operation yields almost 0 Ω in rheostat mode or 0 V in

potentiometer mode. It is important to note that the shutdown

operation does not disturb the contents of the register. When

brought out of shutdown, the previous setting is applied to the

RDAC. In addition, during shutdown, new settings can be

programmed. When the part is returned from shutdown, the

corresponding VR setting is applied to the RDAC.

After all data bits are read or written, the master establishes a

stop condition. A stop condition is defined as a low-to-high

transition on the SDA line while SCL is high. In write mode,

the master pulls the SDA line high during the 10^thclock pulse to

establish a stop condition (see Figure 48 and Figure 49). In read

mode, the master issues a no acknowledge for the ninth clock

pulse (that is, the SDA line remains high). The master brings

the SDA line low before the 10^thclock pulse and then brings the

SDA line high to establish a stop condition (see Figure 50 and

Figure 51).

The third MSB, T, is the OTP programming bit. A logic high

blows the polyfuses and programs the resistor setting permanently.

The OTP program time is 400 ms.

The fourth MSB must always be at Logic 0.

A repeated write function provides the user with the flexibility

of updating the RDAC output multiple times after addressing

and instructing the part only once. For example, after the RDAC

has acknowledged its slave address and instruction bytes in write

mode, the RDAC output is updated on each successive byte. If

different instructions are needed, however, the write/read mode

must restart with a new slave address, instruction, and data byte.

Similarly, a repeated read function of the RDAC is also allowed.

The fifth MSB, OW, is an overwrite bit. When raised to a logic high,

OW allows the RDAC setting to be changed even after the internal

fuses are blown. However, when OW is returned to Logic 0, the

position of the RDAC returns to the setting prior to the overwrite.

Because OW is not static, if the device is powered off and on,

the RDAC presets to midscale or to the setting at which the

fuses were blown, depending on whether the fuses had been

permanently set.

The remainder of the bits in the instruction byte are don’t cares

(see Figure 48 and Figure 49).

Rev. H | Page 21 of 24

AD5172/AD5173

Multiple Devices on One Bus (AD5173 Only)

LEVEL SHIFTING FOR DIFFERENT VOLTAGE

OPERATION

Figure 52 shows four AD5173 devices on the same serial bus.

Each has a different slave address because the states of the AD0

and AD1 pins are different. This allows each device on the bus to

be written to or read from independently. The master device

output bus line drivers are open-drain pull-downs in a fully

I²C-compatible interface.

If the SCL and SDA signals come from a low voltage logic

controller and are below the minimum V_IHlevel (0.7 V × V_DD),

level shift the signals for read/write communications between

the AD5172/AD5173 and the controller. Figure 53 shows one

of the implementations. For example, when SDA1 is at 2.5 V,

M1 turns off, and SDA2 becomes 5 V. When SDA1 is at 0 V,

M1 turns on, and SDA2 approaches 0 V. As a result, proper

level shifting is established. It is best practice for M1 and M2

to be low threshold N-channel power MOSFETs, such as the

FDV301N from Fairchild Semiconductor.

5V

R

P

SDA

SCL

MASTER

5V

V

= 2.5V

V

= 5V

DD1

DD2

R

P

R

P

R

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

P

AD0

G

AD5173

D

S

SDA1

SCL1

SDA2

SCL2

Figure 52. Multiple AD5173 Devices on One I²C Bus

D

S

M1

M2

2.7V TO 5.5V

AD5172/

AD5173

2.5V

CONTROLLER

Figure 53. Level Shifting for Different Voltage Operation

Rev. H | Page 22 of 24

AD5172/AD5173

OUTLINE DIMENSIONS

3.10

3.00

2.90

6

10

5.15

4.90

4.65

3.10

3.00

2.90

1

5

PIN 1

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.05

0.33

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 54. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

R_AB(kΩ)

Temperature Range

−4±°C to +125°C

Package Description

1±-Lead MSOP

Package Option

Branding

DCY

DCR

DCZ

DCT

DCX

DCU

DCW

DCV

DCM

DCH

DCQ

DCL

AD5172BRM2.5

2.5

1±

5±

1±±

2.5

1±

5±

RM-1±

AD5172BRM2.5-RL7

AD5172BRMZ2.5²

AD5172BRM1±

AD5172BRM1±-RL7

AD5172BRMZ1±²

AD5172BRMZ1±-RL7²

AD5172BRM5±

AD5172BRMZ5±²

AD5172BRMZ5±-RL7²

AD5172BRM1±±

AD5172BRMZ1±±²

AD5172BRMZ1±±-RL7²

AD5173BRM2.5

AD5173BRM2.5-RL7

AD5173BRMZ2.5²

AD5173BRMZ2.5-RL7²

AD5173BRM1±

AD5173BRM1±-RL7

AD5173BRMZ1±²

AD5173BRMZ1±-RL7²

AD5173BRM5±

AD5173BRM5±-RL7

AD5173BRMZ5±²

AD5173BRMZ5±-RL7²

AD5173BRM1±±

AD5173BRM1±±-RL7

AD5173BRMZ1±±²

DCL

DCN

DCJ

5±

1±±

DCJ

DCP

DCK

¹The part has a YWW or #YWW label and an assembly lot number label on the bottom side of the package. The Y shows the year that the part was made; for example,

Y = 5 means the part was made in 2±±5. WW shows the work week that the part was made.

²Z = RoHS Compliant Part.

Rev. H | Page 23 of 24

AD5172/AD5173

NOTES

Purchase of licensed I²C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D04103-0-4/09(H)

Rev. H | Page 24 of 24


型号：	AD5172BRMZ502
厂家：	ADI
描述：	256-Position, One-Time Programmable, Dual-Channel, I2C Digital Potentiometers 256位，一次性可编程，双通道， I2C数字电位器电位器
文件：	总24页 (文件大小：864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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