AD5172BRM2.5_技术文档

256-Position One-Time Programmable

Dual-Channel I²C Digital Potentiometers

AD5172/AD5173

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

A1

W1

B1

A2

W2

B2

2-channel, 256-position

OTP (one-time programmable) set-and-forget resistance

setting, low cost alternative to EEMEM

Unlimited adjustments prior to OTP activation

OTP overwrite allows dynamic adjustments with user

defined preset

End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Compact MSOP-10 (3 mm × 4.9 mm) package

Fast settling time: t_S= 5 µs typ in power-up

Full read/write of wiper register

FUSE

LINKS

V

DD

1

2

RDAC

REGISTER 2

GND

REGISTER 1

Power-on preset to midscale

8

Extra package address decode pins AD0 and AD1 (AD5173)

Single supply 2.7 V to 5.5 V

SDA

SCL

SERIAL INPUT

REGISTER

Low temperature coefficient: 35 ppm/°C

Low power, I_DD= 6 µA max

Figure 1. AD5172

Wide operating temperature: –40°C to +125°C

Evaluation board and software are available

Software replaces µC in factory programming applications

W1

B1

W2

B2

APPLICATIONS

Systems calibration

Electronics level setting

FUSE

LINKS

V

DD

1

2

Mechanical Trimmers® replacement in new designs

Permanent factory PCB setting

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

RF amplifier biasing

RDAC

REGISTER 1

RDAC

REGISTER 2

GND

AD0

AD1

ADDRESS

DECODE

8

Automotive electronics adjustment

Gain control and offset adjustment

SDA

SCL

SERIAL INPUT

REGISTER

GENERAL OVERVIEW

Figure 2. AD5173

The AD5172/AD5173 are dual channel, 256-position, one-time

programmable (OTP) digital potentiometers¹that employ fuse

link technology to achieve memory retention of resistance

setting. OTP is a cost-effective alternative to EEMEM for users

who do not need to program the digital potentiometer setting in

memory more than once. This device performs the same elec-

tronic adjustment function as mechanical potentiometers or

variable resistors with enhanced resolution, solid-state reliabil-

ity, and superior low temperature coefficient performance.

Unlike traditional OTP digital potentiometers, the AD5172/

AD5173 have a unique temporary OTP overwrite feature that

allows for new adjustments even after the fuse has been blown.

However, the OTP setting is restored during subsequent power-

up conditions. This feature allows users to treat these digital

potentiometers as volatile potentiometers with a programmable

preset.

For applications that program the AD5172/AD5173 at the

factory, Analog Devices offers device programming software

running on Windows® NT®, 2000, and XP® operating systems.

This software effectively replaces any external I²C controllers,

thus enhancing the time-to-market of the user’s systems.

The AD5172/AD5173 are programmed using a 2-wire, I²C

compatible digital interface. Unlimited adjustments are allowed

before permanently setting the resistance value. During OTP

activation, a permanent blow fuse command freezes the wiper

position (analogous to placing epoxy on a mechanical trimmer).

¹The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD5172/AD5173

TABLE OF CONTENTS

Electrical Characteristics—2.5 kΩ ................................................. 3

Terminal Voltage Operating Range.......................................... 14

Power-Up Sequence ................................................................... 14

Power Supply Considerations................................................... 14

Layout Considerations............................................................... 15

Evaluation Software/Hardware..................................................... 16

Software Programming ............................................................. 16

I²C Interface .................................................................................... 18

I²C Compatible 2-Wire Serial Bus ........................................... 20

Pin Configuration and Function Descriptions........................... 22

Outline Dimensions....................................................................... 23

Ordering Guide............................................................................... 24

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4

Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions

............................................................................................................. 5

Absolute Maximum Ratings............................................................ 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

Operation......................................................................................... 12

One-Time Programming (OTP) .............................................. 12

Programming the Variable Resistor and Voltage.................... 12

Programming the Potentiometer Divider............................... 13

ESD Protection ........................................................................... 14

REVISION HISTORY

Revision A

11/03—Data Sheet Changed from Rev. 0 to Rev. A

Change

Location

Changes to Electrical Characteristics—2.5 kΩ......................... 3

Rev. A | Page 2 of 24

AD5172/AD5173

ELECTRICAL CHARACTERISTICS—2.5 kΩ

Table 1. V_DD= 5 V 1ꢀ0 or 3 V 1ꢀ0; V_A= +V_DD; V_B= ꢀ V; –4ꢀ°C < T_A< +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

RWB (Wiper Resistance)

R-DNL

R-INL

∆R_AB

R_WB, V_A= No Connect

T_A= 27°C

–2

–6

–2±

±±.ꢀ

±±.ꢁ7 +6

+77

37

ꢀ6±

+2

LSB

%

ppm/°C

Ω

(∆R_AB/R_AB)/∆T V_AB= V_DD, Wiper = No Connect

R_WBCode = ±x±±, V_DD= 7 V

2±±

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature

Coefficient

DNL

INL

–ꢀ.7 ±±.ꢀ

+ꢀ.7

+2

LSB

ppm/°C

–2

±±.6

ꢀ7

(ꢂV_W/V_W)/ꢂT Code = ±x8±

Full-Scale Error

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁷

V_WFSE

V_WZSE

Code = ±xFF

Code = ±x±±

–ꢀ±

±

–2.7

2

±

ꢀ±

LSB

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance⁶A, B

f = ꢀ MHz, Measured to GND,

Code = ±x8±

f = ꢀ MHz, Measured to GND,

Code = ±x8±

47

6±

Capacitance W

C_W

pF

Shutdown Supply Current^ꢁ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

I_{A_SD}

I_CM

V_DD= 7.7 V

V_A= V_B= V_DD/2

±.±ꢀ

ꢀ

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 7 V

V_DD= 3 V

2.4

2.ꢀ

V

µA

pF

±.8

±.6

±ꢀ

V_IN= ± V or 7 V

C_IL

7

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage

Supply Current

OTP Supply Current

Power Dissipation⁸

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS⁹

Bandwidth –3 dB

Total Harmonic Distortion

V_WSettling Time

V_{DD RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.ꢁ

6

7.7

6.7

6

V

µA

mA

µW

T_A= 27°C

V_IH= 7 V or V_IL= ± V

V_{DD_OTP}= 6 V, T_A= 27°C

V_IH= 7 V or V_IL= ± V, V_DD= 7 V

V_DD= 7 V ± ꢀ±%, Code = Midscale

3.7

ꢀ±±

3±

PSS

±±.±2 ±±.±8 %/%

BW_2.7K

THD_W

t_S

Code = ±x8±

4.8

±.ꢀ

ꢀ

MHz

%

µs

V_A= ꢀ V rms, V_B= ± V, f = ꢀ kHz

V_A= 7 V, V_B= ± V, ±ꢀ LSB Error Band

R_WB= ꢀ.27 kΩ, R_S= ±

Resistor Noise Voltage Density

e_{N_WB}

3.2

nV/√Hz

^ꢀTypical specifications represent average readings at 27°C and V_DD= 7 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, Wiper (V_W) = no connect.

⁴INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= ± V. DNL

specification limits of ±ꢀ LSB maximum are guaranteed monotonic operating conditions.

⁷Resistor terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

^ꢁMeasured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁹All dynamic characteristics use V_DD= 7 V.

Rev. A | Page 3 of 24

AD5172/AD5173

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 2. V_DD= 5 V ꢀ10 or 3 V ꢀ10; V_A= V_DD; V_B= 1 V; –41°C < T_A< +ꢀ25°C; unless otherwise noted

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R_WB(Wiper Resistance)

R-DNL

R-INL

∆R_AB

R_WB, V_A= No Connect

T_A= 25°C

–1

–2.5

–2±

±±.1

±±.25 +2.5

+2±

35

16±

+1

LSB

%

ppm/°C

Ω

(∆R_AB/R_AB)/∆T V_AB= V_DD, Wiper = No Connect

R_WBCode = ±x±±, V_DD= 5 V

2±±

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(∆V_W/V_W)/∆T

V_WFSE

V_WZSE

–1

±±.1

±±.3

15

–1

1

+1

LSB

ppm/°C

LSB

Code = ±x8±

Code = ±xFF

Code = ±x±±

–2.5

±

2.5

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_A, V_B, V_W

C_A, C_B

C_W

I_{A_SD}

I_CM

GND

V_DD

V

Capacitance⁶A, B

f = 1 MHz, Measured to GND, Code = ±x8±

V_DD= 5.5 V

45

6±

±.±1

1

pF

µA

nA

Capacitance⁶W

Shutdown Supply Current⁷

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

1

V_A= V_B= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

±.8

±.6

±1

V_IN= ± V or 5 V

C_IL

5

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage⁸

Supply Current

OTP Supply Current⁹

Power Dissipation^1±

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS¹¹

Bandwidth –3 dB

V_{DD RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.7

6

5.5

6.5

6

V

µA

mA

µW

V_IH= 5 V or V_IL= ± V

3.5

1±±

V_IH= 5 V or V_IL= ± V, V_DD= 5 V

V_DD= +5 V ± 1±%, Code = Midscale

3±

PSS

±±.±2 ±±.±8 %/%

BW

R_AB= 1± kΩ, Code = ±x8±

R_AB= 5± kΩ, Code = ±x8±

R_AB= 1±± kΩ, Code = ±x8±

V_A=1 V rms, V_B= ± V, f = 1 kHz, R_AB= 1± kΩ

V_A= 5 V, V_B= ± V, ±1 LSB Error Band

R_WB= 5 kΩ, R_S= ±

6±±

1±±

4±

±.1

2

kHz

%

µs

nV/√Hz

Total Harmonic Distortion

V_WSettling Time (1± kΩ/5± kΩ/1±± kΩ)

Resistor Noise Voltage Density

THD_W

t_S

e_{N_WB}

9

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, Wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= ± V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

⁷Measured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸Different from operating power supply, power supply OTP is used one time only.

⁹Different from operating current, supply current for OTP lasts approximately 4±± ms for one time only.

1±

P

is calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

DISS

¹¹All dynamic characteristics use V_DD= 5 V.

Rev. A | Page 4 of 24

AD5172/AD5173

TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. V_DD= 5 V ꢀ10 or 3V ꢀ10; V_A= V_DD; V_B= 1 V; –41°C < T_A< +ꢀ25°C; unless otherwise noted

Parameter Symbol Conditions

I²C INTERFACE TIMING CHARACTERISTICS¹(Specifications Apply to All Parts)

Min Typ Max Unit

SCL Clock Frequency

t_BUFBus Free Time between STOP and START

t_HD;STAHold Time (Repeated START)

f_SCL

t₁

t₂

4±±

kHz

µs

1.3

±.6

After this period, the first clock pulse is

generated.

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time for Repeated START Condition

t_HD;DATData Hold Time²

t_SU;DATData Setup Time

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSetup Time for STOP Condition

t₃

t₄

t₅

t₆

t₇

t₈

t₉

t_1±

1.3

±.6

µs

ns

µs

±.9

1±±

±.6

3±±

¹See timing diagrams for locations of measured values.

²The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

Rev. A | Page 5 of 24

AD5172/AD5173

ABSOLUTE MAXIMUM RATINGS

Table 4. T_A= 25°C, unless otherwise noted

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Value

V_DDto GND

V_A, V_B, V_Wto GND

Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx¹

–±.3 V to +7 V

V_DD

Pulsed

±2± mA

Continuous

±5 mA

Digital Inputs and Output Voltage to GND

Operating Temperature Range

± V to 7 V

–4±°C to +125°C

15±°C

–65°C to +15±°C

3±±°C

Maximum Junction Temperature (T_JMAX

Storage Temperature

)

Lead Temperature (Soldering, 1± sec)

Thermal Resistance²θ_JA: MSOP-1±

23±°C/W

¹Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 6 of 24

AD5172/AD5173

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

0.5

0.4

T

= 25°C

R

= 10kΩ

A

AB

R

= 10kΩ

AB

1.5

1.0

0.3

V

= 2.7V

DD

0.2

0.5

0.1

V

= 2.7V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0

V

= 5.5V

DD

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 3. R-INL vs. Code vs. Supply Voltages

Figure 6. DNL vs. Code vs. Temperature

0.5

0.4

1.0

0.8

T

R

= 25°C

T

R

= 25°C

= 10kΩ

A

= 10kΩ

AB

0.3

0.6

0.2

0.4

V

= 2.7V

DD

V

= 5.5V

0.1

0.2

DD

0

V

= 2.7V

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

DD

V

= 5.5V

DD

32

64

96

128

160

192

224

256

64

96

128

160

192

224

CODE (DECIMAL)

Figure 4. R-DNL vs. Code vs. Supply Voltages

Figure 7. INL vs. Code vs. Supply Voltages

0.5

0.4

0.5

0.4

R

= 10kΩ

T

R

= 25°C

= 10kΩ

AB

A

AB

0.3

V

= 5.5V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0.2

0.1

V

= 2.7V

DD

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

V

= 2.7V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

32

64

96

128

160

192

224

256

64

96

128

160

192

224

CODE (DECIMAL)

Figure 5. INL vs. Code vs. Temperature

Figure 8. DNL vs. Code vs. Supply Voltages

Rev. A | Page 7 of 24

AD5172/AD5173

2.0

4.50

3.75

3.00

2.25

1.50

0.75

0

R

= 10kΩ

R

= 10kΩ

AB

1.5

1.0

V

= 2.7V

DD

= –40°C, +25°C, +85°C, +125°C

T

A

0.5

0

V

= 2.7V, V = 2.7V

A

DD

V

= 5.5V

DD

–0.5

–1.0

–1.5

–2.0

T

= –40°C, +25°C, +85°C, +125°C

A

V

= 5.5V, V = 5.0V

A

DD

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 9. R-INL vs. Code vs. Temperature

Figure 12. Zero-Scale Error vs. Temperature

0.5

0.4

10

R

= 10kΩ

AB

0.3

V

= 5V

DD

0.2

V

= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0.1

0

1

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 3V

DD

0.1

–40

0

32

64

96

128

160

192

224

256

–7

26

59

92

125

TEMPERATURE (°C)

CODE (DECIMAL)

Figure 10. R-DNL vs. Code vs. Temperature

Figure 13. Supply Current vs. Temperature

120

100

80

2.0

1.5

R

= 10kΩ

R

= 10kΩ

AB

1.0

0.5

60

V

= 2.7V

DD

T

= –40°C TO +85°C, –40°C TO +125°C

A

0

V

= 5.5V, V = 5.0V

A

DD

40

V

= 5.5V

DD

–0.5

–1.0

–1.5

–2.0

T

= –40°C TO +85°C, –40°C TO +125°C

A

20

V

= 2.7V, V = 2.7V

A

DD

0

–20

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 14. Rheostat Mode Tempco ∆R_WB/∆T vs. Code

Figure 11. Full-Scale Error vs. Temperature

Rev. A | Page 8 of 24

AD5172/AD5173

50

40

0

–6

R

= 10kΩ

AB

0x80

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

30

V

T

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

20

A

0x08

0x04

0x02

0x01

10

0

–10

–20

–30

V

= 5.5V

DD

T

= –40°C TO +85°C, –40°C TO +125°C

A

0

32

64

96

128

160

192

224

256

1k

10k

100k

1M

CODE (DECIMAL)

FREQUENCY (Hz)

Figure 15. AD5172 Potentiometer Mode Tempco ∆V_WB/∆T vs. Code

Figure 18. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

0

–6

0x80

0x40

0x20

0x80

0x40

0x20

–6

–12

–18

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

–24

0x08

0x04

–30

–36

0x02 0x01

–42

–48

–54

–60

10k

100k

FREQUENCY (Hz)

1M

10M

10k

100k

FREQUENCY (Hz)

1M

Figure 16. Gain vs. Frequency vs. Code, R_AB= 2.5 kΩ

Figure 19. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

0

–6

0x80

0x40

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

100kΩ

60kHz

50kΩ

0x20

0x10

0x08

0x04

120kHz

10kΩ

570kHz

2.5kΩ

2.2MHz

0x02

0x01

1k

10k

100k

FREQUENCY (Hz)

1M

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

Figure 20. –3 dB Bandwidth @ Code = 0x80

Rev. A | Page 9 of 24

AD5172/AD5173

10

T

= 25°C

A

1

V

= 5.5V

DD

V

W2

0.1

V

= 2.7V

DD

W1

0.01

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 24. Analog Crosstalk

Figure 25. Midscale Glitch, Code 0x80 to 0x7F

Figure 26. Large Signal Settling Time

Figure 21. I_DDvs. Input Voltage

V

W

V

W

SCL

Figure 22. Digital Feedthrough

V

W

V

W2

SCL

W1

Figure 23. Digital Crosstalk

Rev. A | Page 1± of 24

AD5172/AD5173

TEST CIRCUITS

Figure 27 to Figure 34 illustrate the test circuits that define the

test conditions used in the product specification tables.

DUT

A

DUT

A

V+ = V

DD

1LSB = V+/2

+15V

N

W

V

V+

IN

AD8610

V

OUT

OFFSET

GND

B

V

MS

B

2.5V

–15V

Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 31. Test Circuit for Gain vs. Frequency

NO CONNECT

DUT

0.1V

R

=

SW

I

SW

DUT

B

I

W

CODE = 0x00

A

W

0.1V

B

I

SW

V

MS

GND TO V

DD

Figure 28. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 32. Test Circuit for Incremental On Resistance

NC

DUT

I

= V /R

NOMINAL

DD

DUT

W

A

V

W

V

DD

V

I

CM

A

B

MS2

W

B

V

R

= [V

– V ]/I

W

MS2

MS1

W

MS1

GND

V

CM

NC

Figure 29. Test Circuit for Wiper Resistance

Figure 33. Test Circuit for Common-Mode Leakage Current

V

A

V+ = V

10%

PSRR (dB) = 20 LOG

DD

DUT

∆V

A1

A2

MS

DD

V

DD

(

)

RDAC1

V

RDAC2

W2

DD

A

%

∆V

MS

W

W1

V+

PSS (%/%) =

N/C

V

%

OUT

DD

V

B

IN

B2

V

MS

V

SS

B1

Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

CTA = 20 log[V /V ]

OUT IN

Figure 34. Test Circuit for Analog Crosstalk

Rev. A | Page 11 of 24

AD5172/AD5173

OPERATION

A

SCL

SDA

DECODER

MUX

DAC

REG.

2

I C INTERFACE

W

B

COMPARATOR

FUSES

EN

FUSE

REG.

ONE-TIME

PROGRAM/TEST

CONTROL BLOCK

Figure 35. Detailed Functional Block Diagram

The AD5172/AD5173 is a 256-position, digitally controlled

variable resistor (VR) that employs fuse link technology to

achieve memory retention of resistance setting.

A

B

A

B

W

B

An internal power-on preset places the wiper at midscale

during power-on. If the OTP function has been activated, the

device powers up at the user-defined permanent setting.

Figure 36. Rheostat Mode Configuration

Assuming a 10 kΩ part is used, the wiper’s first connection

starts at the B terminal for data 0x00. Because there is a 50 Ω

wiper contact resistance, such a connection yields a minimum

of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The

second connection is the first tap point, which corresponds to

139 Ω (R_WB= R_AB/256 + 2 × R_W= 39 Ω + 2 × 50 Ω) for data

0x01. The third connection is the next tap point, representing

178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB

data value increase moves the wiper up the resistor ladder until

the last tap point is reached at 10,100 Ω (R_AB+ 2 × R_W).

ONE-TIME PROGRAMMING (OTP)

Prior to OTP activation, the AD5172/AD5173 presets to mid-

scale during initial power-on. After the wiper is set at the

desired position, the resistance can be permanently set by

programming the T bit high along with the proper coding (see

Table 5 and Table 6). Note that fuse link technology requires 6 V

to blow the internal fuses to achieve a given setting. The user is

allowed only one attempt at blowing the fuses. Once program-

ming is completed, the power supply voltage must be reduced to

the normal operating range of 2.7 V to 5.5 V.

A

R

S

The device control circuit has two validation bits, E1 and E0,

that can be read back to check the programming status (see

Table 7). Users should always read back the validation bits to

ensure that the fuses are properly blown. After the fuses have

been blown, all fuse latches are enabled upon subsequent

power-on; therefore, the output corresponds to the stored

setting. Figure 35 shows a detailed functional block diagram.

R

D7

D6

D5

D4

D3

D2

D1

D0

S

W

PROGRAMMING THE VARIABLE RESISTOR AND

VOLTAGE

Rheostat Operation

R

RDAC

S

LATCH

AND

The nominal resistance of the RDAC between terminals A and

B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal

resistance (R_AB) of the VR has 256 contact points accessed by

the wiper terminal, plus the B terminal contact. The 8-bit data

in the RDAC latch is decoded to select one of the 256 possible

settings.

B

DECODER

Figure 37. AD5172/AD5173 Equivalent RDAC Circuit

Rev. A | Page 12 of 24

AD5172/AD5173

The general equation that determines the digitally programmed

output resistance between W and B is

Typical device-to-device matching is process lot dependent and

may vary by up to 30ꢀ. Because the resistance element is pro-

cessed using thin film technology, the change in R_ABwith

temperature has a very low 35 ppm/°C temperature coefficient.

D

128

RWB(D) =

×RAB +2×R

W

(1)

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

where D is the decimal equivalent of the binary code loaded in

the 8-bit RDAC register, R_ABis the end-to-end resistance, and

R_Wis the wiper resistance contributed by the on resistance of

the internal switch.

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

A-to-B. Unlike the polarity of V_DDto GND, which must be posi-

tive, voltage across A-B, W-A, and W-B can be at either polarity.

In summary, if R_AB= 10 kΩ and the A terminal is open-

circuited, the output resistance R_WBis set for the RDAC latch

codes, as shown in Table 5.

V

I

A

B

Table 5. Codes and Corresponding RWB Resistance

W

V

O

D (Dec.)

R_WB(Ω)

9,961

5,±6±

139

Output State

255

128

1

Full-Scale (R_AB– 1 LSB + R_W)

Midscale

1 LSB

Figure 38. Potentiometer Mode Configuration

±

1±±

Zero-Scale (Wiper Contact Resistance)

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across terminal AB divided by the 256 positions

of the potentiometer divider. The general equation defining the

output voltage at V_Wwith respect to ground for any valid input

voltage applied to terminals A and B is

Note that in the zero-scale condition, a finite wiper resistance of

100 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of

no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper W and terminal A also produces a

digitally controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

D

256

256 − D

256

V_W(D) =

V_A

+

V_B

(3)

For a more accurate calculation, which includes the effect of

wiper resistance, V_Wcan be found as

256– D

128

R

_WB(D)

R_AB

R

_WA(D)

R_AB

R^WA(D) =

×RAB +2×R

W

(2)

V_W(D) =

V_A+

V_B

(4)

For R_AB= 10 kΩ and the B terminal open-circuited, the

following output resistance R_WAis set for the RDAC latch codes,

as shown in Table 6.

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors R_WAand R_WBand not the abso-

lute values. Thus, the temperature drift reduces to 15 ppm/°C.

Table 6. Codes and Corresponding R_WAResistance

D (Dec.)

R_WA(Ω)

Output State

Full-Scale

Midscale

1 LSB

255

128

1

139

5,±6±

9,961

1±,±6±

±

Zero-Scale

Rev. A | Page 13 of 24

AD5172/AD5173

ESD PROTECTION

POWER SUPPLY CONSIDERATIONS

All digital inputs—SDA, SCL, AD0, and AD1— are protected

with a series input resistor and parallel Zener ESD structures, as

shown in Figure 39 and Figure 40.

To minimize the package pin count, both the one-time pro-

gramming and normal operating voltage supplies are applied to

the same V_DDterminal of the AD5172/AD5173. The AD5172/

AD5173 employ fuse link technology that requires 6 V to blow

the internal fuses to achieve a given setting. The user is allowed

only one attempt at blowing the fuses. Once programming is

completed, power supply voltage must be reduced to the normal

2.7 V to 5.5 V operating range. Such dual voltage requirements

require isolation between the supplies. The fuse programming

supply (either an on-board regulator or rack-mount power sup-

ply) must be rated at 6 V and must be able to provide a 100 mA

transient current for 400 ms for successful one-time program-

ming. Once programming is complete, the 6 V supply must be

removed to allow normal operation at 2.7 V to 5.5 V at regular

microamp current levels. Figure 42 shows the simplest imple-

mentation using a jumper. This approach saves one voltage

supply, but draws additional current and requires manual

configuration.

340Ω

LOGIC

GND

Figure 39. ESD Protection of Digital Pins

A,B,W

GND

Figure 40. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5172/AD5173 V_DDto GND power supply defines the

boundary conditions for proper 3-terminal digital potentiom-

eter operation. Supply signals present on terminals A, B, and W

that exceed V_DDor GND are clamped by the internal forward-

biased diodes (see Figure 41).

CONNECT J1 HERE

FOR OTP

6V

R1 50kΩ

V

DD

C1

1µF

C2

1nF

5V

R2 250kΩ

AD5172/

AD5173

CONNECT J1 HERE

AFTER OTP

V

DD

A

Figure 42. Power Supply Requirement

W

B

An alternate approach in 3.5 V to 5.5 V systems adds a signal

diode between the system supply and the OTP supply for

isolation, as shown in Figure 43.

GND

Figure 41. Maximum Terminal Voltages Set by V_DDand GND

APPLY FOR OTP ONLY

6V

POWER-UP SEQUENCE

D1

V

3.5V–5.5V

DD

Because the ESD protection diodes limit the voltage compliance

at terminals A, B, and W (see Figure 41), it is important to

power V_DD/GND before applying any voltage to terminals A, B,

and W. Otherwise, the diode will be forward biased such that

V_DDis powered unintentionally and may affect the rest of the

user’s circuit. The ideal power-up sequence is GND, V_DD, the

digital inputs, and then V_A/V_B/V_W. The relative order of

powering V_A, V_B, V_W, and the digital inputs is not important as

long as they are powered after V_DD/GND.

C1

1µF

C2

1nF

AD5172/

AD5173

Figure 43. Isolate 6 V OTP Supply from 3.5 V to 5.5 V Normal Operating

Supply. The 6 V supply must be removed once OTP is completed.

Rev. A | Page 14 of 24

AD5172/AD5173

APPLY FOR OTP ONLY

6V

Poor PCB layout introduces parasitics that may affect the fuse

programming. Therefore, it is recommended to add a 1 µF

tantalum capacitor in parallel with a 1 nF ceramic capacitor as

close as possible to the V_DDpin. These capacitors help ensure

OTP programming success by providing proper current densi-

ties. This combination of capacitor values provides both a fast

response for high frequency transients and a larger supply of

current for extended spikes. Typically, C1 minimizes any

transient disturbances and low frequency ripple, while C2

reduces high frequency noise.

R1

10kΩ

V

2.7V

DD

C1

C2

1µF

1nF

P1

P2

AD5172/

AD5173

P1=P2=FDV302P, NDS0610

Figure 44. Isolate 6 V OTP Supply from 2.7 V Normal Operating Supply.

The 6 V supply must be removed once OTP is completed.

LAYOUT CONSIDERATIONS

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

For users who operate their systems at 2.7 V, use of the

bidirectional low threshold P-Ch MOSFETs is recommended

for the supply’s isolation. As shown in Figure 44, this assumes

that the 2.7 V system voltage is applied first, and that the P1 and

P2 gates are pulled to ground, thus turning on P1 and

subsequently P2. As a result, V_DDof the AD5172/AD5173

approaches 2.7 V. When the AD5172/AD5173 setting is found,

the factory tester applies the 6 V to V_DD; the 6 V is also applied

to the gates of P1 and P2 to turn them off. The OTP command

is executed at this time to program the AD5172/AD5173; the

2.7 V source is therefore protected. Once the OTP is completed,

the tester withdraws the 6 V and the AD5172/AD5173’s setting

is fixed permanently.

Note that the digital ground should also be joined remotely to

the analog ground at one point to minimize the ground bounce.

V

DD

+

C1

C2

1µF

1nF

AD5172

GND

AD5172/AD5173 achieves the OTP function through blowing

internal fuses. Users should always apply the 6 V one-time

program voltage requirement at the first program command.

Failure to comply with this requirement may lead to the change

of fuse structures, rendering programming inoperable.

Figure 45. Power Supply Bypassing

Rev. A | Page 15 of 24

AD5172/AD5173

EVALUATION SOFTWARE/HARDWARE

Figure 46. AD5172/AD5173 Computer Software Interface

There are two ways of controlling the AD5172/AD5173. Users

can either program the devices with computer software or with

external I²C controllers.

The AD5172/AD5173 starts at midscale after power-up prior to

OTP programming. To increment or decrement the resistance,

the user may simply move the scrollbars on the left. To write

any specific value, the user should use the bit pattern in the

upper screen and press the Run button. The format of writing

data to the device is shown in Table 7. Once the desired setting

is found, the user may press the Program Permament button to

blow the internal fuse links.

SOFTWARE PROGRAMMING

Due to the advantages of the one-time programmable feature,

users may consider programming the device in the factory

before shipping the final product to end-users. ADI offers a

device programming software that can be implemented in the

factory on PCs running Windows 95 or later. As a result,

external controllers are not required, which significantly

reduces development time. The program is an executable file

that does not require any programming languages or user

programming skills. It is easy to set up and to use. Figure 46

shows the software interface. The software can be downloaded

from www.analog.com.

To read the validation bits and data out from the device, the

user simply presses the Read button. The format of the read bits

is shown in Table 8.

To apply the device programming software in the factory, users

must modify a parallel port cable and configure Pins 2, 3, 15,

and 25 for SDA_write, SCL, SDA_read, and DGND, respectively,

for the control signals (Figure 47). Users should also lay out the

PCB of the AD5172/AD5173 with SCL and SDA pads, as shown

in Figure 48, such that pogo pins can be inserted for factory

programming.

Rev. A | Page 16 of 24

AD5172/AD5173

AD5172

AD5173

13

25

12

24

11

23

B1

A1

W1

B2

B1

AD0

W2

W1

B2

W2

A2

AD1

SDA

SCL

GND

VDD

SDA

SCL

GND

VDD

10

22

9

21

8

Figure 48. Recommended AD5172/AD5173 PCB Layout. The SCL and SDA

pads allow pogo pins to be inserted so that signals can be communicated

through the parallel port for programming (Figure 47).

20

7

19

6

18

5

R3

100Ω

R2

17

4

SCL

SDA

16

3

READ

100Ω

15

2

R1

WRITE

14

100Ω

1

Figure 47. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,

Pin 15 = SDA_read, and Pin 25 = DGND.

Rev. A | Page 17 of 24

AD5172/AD5173

I²C INTERFACE

Table 7. Write Mode

AD5ꢀ72

W

S

±

1

±

1

A

A± SD

T

±

OW

X

A

D7 D6 D5 D4 D3 D2 D1 D±

Data Byte

A

P

Slave Address Byte

Instruction Byte

AD5ꢀ73

S

±

1

AD1 AD±

A

T

±

OW

X

D7 D6 D5 D4 D3 D2 D1 D±

Data Byte

Slave Address Byte

Instruction Byte

Table 8. Read Mode

AD5ꢀ72

S

±

1

±

1

R

A

D7 D6 D5 D4 D3 D2 D1 D±

Instruction Byte

A

E1 E±

X

A

P

Slave Address Byte

Data Byte

AD5ꢀ73

S

±

1

±

1

AD1 AD±

A

D7 D6 D5 D4 D3 D2 D1 D±

Instruction Byte

X

Slave Address Byte

Data Byte

S = Start Condition

P = Stop Condition

A = Acknowledge

OW = Overwrite the fuse setting and program the digital

potentiometer to a different setting. Note that upon power-up,

the digital potentiometer is preset to either midscale or fuse

setting, depending on whether not the fuse link has been blown.

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.

E1, E0 = OTP Validation Bits.

AD0, AD1 = Package Pin Programmable Address Bits

X = Don’t Care

0, 0 = Ready to Program.

W

= Write

1, 0 = Fatal Error. Some fuses not blown. Do not retry. Discard

this unit.

R = Read

A0 = RDAC Subaddress Select Bit

1, 1 = Programmed Successfully. No further adjustments

possible.

SD = Shutdown connects wiper to B terminal and open circuits

the A terminal. It does not change contents of wiper register.

T = OTP Programming Bit. Logic 1 programs the wiper

permanently.

Rev. A | Page 18 of 24

AD5172/AD5173

t₂

t₈

t₆

t₉

SCL

SDA

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

t₁

P

S

P

Figure 49. I²C Interface Detailed Timing Diagram

1

9

1

9

1

9

SCL

SDA

0

1

0

1

R/W

A0 SD

T

0

OW

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5172

ACK BY

AD5172

ACK BY

AD5172

START BY

MASTER

STOP BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

Figure 50. Writing to the RDAC Register—AD5172

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

A0 SD

T

0

OW

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5173

ACK BY

AD5173

ACK BY

AD5173

START BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

Figure 51. Writing to the RDAC Register—AD5173

1

0

9

1

9

1

9

SCL

SDA

1

0

1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0

X

NO ACK

BY MASTER

ACK BY

AD5172

ACK BY

MASTER

START BY

MASTER

STOP BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

Figure 52. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0

X

NO ACK

BY MASTER

ACK BY

AD5173

ACK BY

MASTER

START BY

MASTER

STOP BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

Figure 53. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173

Rev. A | Page 19 of 24

AD5172/AD5173

I²C COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I²C serial bus protocol operates as follows:

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see

Figure 49).

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 50 and

Figure 51). The following byte is the slave address byte,

which consists of the slave address followed by an R/ bit

W

(this bit determines whether data is read from or written to

the slave device). The AD5172 has a fixed slave address

byte, whereas the AD5173 has two configurable address

bits, AD0 and AD1 (see Figure 50 and Figure 51).

3. In the read mode, the data byte follows immediately after

the acknowledgment of the slave address byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (a slight difference from the write mode, where there

are eight data bits followed by an acknowledge bit). Simi-

larly, the transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL (see Figure 52 and Figure 53).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

Note that the channel of interest is the one that is

previously selected in the write mode. In the case where

users need to read the RDAC values of both channels, they

must program the first channel in the write mode and then

change to the read mode to read the first channel value.

After that, the user must change back to the write mode

with the second channel selected and read the second

channel value in the read mode. It is not necessary for users

to issue the Frame 3 data byte in the write mode for subse-

quent readback operation. Refer to Figure 52 and Figure 53

for the programming format.

its serial register. If the R/ bit is high, the master reads

from the slave device. If the R/ bit is low, the master

W

writes to the slave device.

W

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB) of the instruction byte is the RDAC

subaddress select bit. A logic low selects channel 1; a logic

high selects channel 2.

The second MSB, SD, is a shutdown bit. A logic high causes

an open circuit at terminal A while shorting the wiper to

terminal B. This operation yields almost 0 Ω in rheostat

mode or 0 V in potentiometer mode. It is important to note

that the shutdown operation does not disturb the contents

of the register. When brought out of shutdown, the previ-

ous setting is applied to the RDAC. Also, during shutdown,

new settings can be programmed. When the part is

returned from shutdown, the corresponding VR setting is

applied to the RDAC.

Following the data byte, the validation byte contains two

validation bits, E0 and E1. These bits signify the status of

the one-time programming (see Figure 52 and Figure 53).

4. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10^thclock pulse to establish a STOP

condition (see Figure 50 and Figure 51). In read mode, the

master issues a No Acknowledge for the ninth clock pulse

(i.e., the SDA line remains high). The master then brings

the SDA line low before the 10^thclock pulse, which goes

high to establish a STOP condition (see Figure 52 and

Figure 53).

The third MSB, T, is the OTP programming bit. A logic

high blows the poly fuses and programs the resistor setting

permanently.

The fourth MSB must always be at Logic 0.

The fifth MSB, OW, is an overwrite bit. When raised to a

logic high, OW allows the RDAC setting to be changed

even after the internal fuses have been blown. However,

once OW is returned to a logic zero, the position of the

RDAC returns to the setting prior to overwrite. Because

OW is not static, if the device is powered off and on, the

RDAC presets to midscale or to the setting at which the

fuses were blown, depending on whether or not the fuses

have been permanently set already.

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing and instruc-

ting the part only once. For example, after the RDAC has

acknowledged its slave address and instruction bytes in the

write mode, the RDAC output is updated on each successive

byte. If different instructions are needed, the write/read mode

has to start again with a new slave address, instruction, and data

byte. Similarly, a repeated read function of the RDAC is also

allowed.

The remainder of the bits in the instruction byte are don’t

cares (see Figure 50 and Figure 51).

Rev. A | Page 2± of 24

AD5172/AD5173

5V

Table 9. Validation Status

R

P

E1

E0

Status

SDA

±

Ready for Programming.

MASTER

1

±

Fatal Error. Some fuses not blown.

Do not retry. Discard this unit.

SCL

5V

1

Successful. No further

programming is possible.

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

AD0

Multiple Devices on One Bus(AD5173 Only)

AD5173

Figure 54 shows four AD5173s on the same serial bus. Each has

a different slave address because the states of their AD0 and

AD1 pins are different. This allows each device on the bus to be

written to or read from independently. The master device

output bus line drivers are open-drain pull-downs in a fully I²C

compatible interface.

Figure 54. Multiple AD5173s on One I²C Bus

Rev. A | Page 21 of 24

AD5172/AD5173

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

1

2

3

4

5

10

9

W1

B1

AD0

W2

9

B2

A1

8

W2

AD5172

TOP VIEW

A2

AD5173

TOP VIEW

AD1

SDA

SCL

7

GND

SDA

SCL

GND

6

V

DD

Figure 55. AD5172 Pin Configuration

Figure 56. AD5173 Pin Configuration

Table ꢀ1. AD5ꢀ72 Pin Function Descriptions

Table ꢀꢀ.AD5ꢀ73 Pin Function Descriptions

Pin Menmonic Description

Pin Mnemonic Description

1

2

3

4

5

6

7

8

9

1±

B1

A1

B1 Terminal.

A1 Terminal.

W2 Terminal.

Digital Ground.

Positive Power Supply.

Serial Clock Input. Positive edge triggered.

Serial Data Input/Output.

A2 Terminal.

B2 Terminal.

W1 Terminal.

1

2

B1

AD±

B1 Terminal.

Programmable Address Bit ± for Multiple

Package Decoding.

W2 Terminal.

Digital Ground.

Positive Power Supply.

Serial Clock Input. Positive edge triggered.

Serial Data Input/Output.

Programmable Address Bit 1 for Multiple

Package Decoding.

W2

GND

V_DD

SCL

SDA

A2

3

4

5

6

7

8

W2

GND

V_DD

SCL

SDA

AD1

B2

W1

9

1±

B2

W1

B2 Terminal.

W1 Terminal.

Rev. A | Page 22 of 24

AD5172/AD5173

OUTLINE DIMENSIONS

3.00 BSC

10

6

4.90 BSC

3.00 BSC

PIN 1

1

5

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.00

0.27

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 57. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Rev. A | Page 23 of 24

AD5172/AD5173

ORDERING GUIDE

Model

R_AB(kΩ)

2.5

1±

5±

1±±

Temperature Range

–4±°C to +125°C

Package Description

MSOP-1±

Evaluation Board

MSOP-1±

Package Option

RM-1±

Branding

D±U

D±V

D1±

D11

AD5172BRM2.5

AD5172BRM2.5-RL7

AD5172BRM1±

AD5172BRM1±-RL7

AD5172BRM5±

AD5172BRM5±-RL7

AD5172BRM1±±

AD5172BRM1±±-RL7

AD5172EVAL¹

AD5173BRM2.5

AD5173BRM2.5-RL7

AD5173BRM1±

AD5173BRM1±-RL7

AD5173BRM5±

AD5173BRM5±-RL7

AD5173BRM1±±

AD5173BRM1±±-RL7

AD5173EVAL¹

2.5

1±

5±

1±±

–4±°C to +125°C

RM-1±

D1K

D1L

D1M

D1N

Evaluation Board

¹The evaluation board is shipped with the 1± kΩ R_ABresistor option; however, the board is compatible with all available resistor value options.

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

C04103–0–11/03(A)

Rev. A | Page 24 of 24


型号：	AD5172BRM2.5
厂家：	ADI
描述：	256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers 256位一次性可编程双通道I2C数字电位器电位器
文件：	总24页 (文件大小：1150K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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