AD5171BRJ5-RL7 [ADI]
64-Position OTP Digital Potentiometer; 64位OTP数字电位计
| 型号： | AD5171BRJ5-RL7 |
| 厂家： | 
ADI |
| 描述： | 64-Position OTP Digital Potentiometer |
| 文件： | 总20页 (文件大小：1652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64-Position OTP Digital Potentiometer
AD5171
Preliminary Technical Data
a mechanical trimmer). When this permanent setting is
achieved, the value will not change regardless of supply
variations or environmental stresses under normal operating
conditions. To verify the success of permanent programming,
Analog Devices patterned the OTP validation such that the fuse
status can be discerned from two validation bits in read mode.
FEATURES
64 positions
OTP (one-time programmable)1 set-and-forget resistance
setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end resistance
Low tempco 5 ppm/oC in potentiometer mode
Low tempco 35 ppm/°C in rheostat mode
Compact standard SOT-23-8 package
Low power, IDD = 8 µA max
Fast settling time, ts = 5 µs typ in power-up
I2C compatible digital interface
Computer software replaces µc in factory programming
applications
For applications that program AD5171 in the factories, Analog
Devices offers a device programming software, which operates
across Windows® 95 to XP® platforms including Windows NT®.
This software application effectively replaces the need for
external I2C controllers or host processors and therefore
significantly reduces users’ development time.
An AD5171 evaluation kit is available, which includes the
software, connector, and cable that can be converted for the
factory programming applications.
Full read/write of wiper register
Extra I2C device address pin
Power-on preset to midscale
The AD5171 is available in a compact SOT-23-8 package. All
parts are guaranteed to operate over the automotive
temperature range of −40°C to +125°C. Besides its unique OTP
feature, the AD5171 lends itself well to other general-purpose
digital potentiometer applications due to its temperature
performance, small form factor, and low cost.
6 V one-time programming voltage
Low operating voltage, 2.7 V to 5.5 V
OTP validation check function
Automotive temperature range −40°C to +125°C
APPLICATIONS
SCL
Systems calibrations
Electronics level settings
A
2
I C INTERFACE
SDA
AND
Mechanical potentiometers and trimmers® replacements
Automotive electronics adjustments
Gain control and offset adjustments
Transducer circuits adjustments
Programmable filters up to 1.5 MHz BW
CONTROL LOGIC
W
AD0
B
WIPER
V
DD
REGISTER
GENERAL DESCRIPTION
GND
FUSE
LINK
The AD5171 is a 64-position, one-time programmable (OTP)
digital potentiometer2, which employs fuse link technology to
achieve the memory retention of resistance setting function.
OTP is a cost-effective alternative over the EEMEM approach
for users who do not need to reprogram new memory setting in
the digital potentiometer. This device performs the same
electronic adjustment function like most mechanical trimmers
and variable resistors do. The AD5171 is programmed using a
2-wire I2C compatible digital control. It allows unlimited
adjustments before permanently setting the resistance value.
During the OTP activation, a permanent fuse blown command
is sent after the final value is determined; therefore freezing the
wiper position at a given setting (analogous to placing epoxy on
AD5171
Figure 1. Functional Block Diagram
1
2
3
4
8
7
6
5
A
W
AD5171
B
V
DD
TOP VIEW
AD0
SDA
GND
SCL
(Not to Scale)
Figure 2. Pin Configuration
1One-time programmable (OTP) - Unlimited adjustments before permanent
setting.
2The terms digital potentiometer and RDAC are used interchangeably.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5171
Preliminary Technical Data
TABLE OF CONTENTS
AD5171—Electrical Characteristics .............................................. 3
I2C Controller Programming................................................ 15
Controlling Two Devices on One Bus..................................... 16
Applications..................................................................................... 17
Programmable Voltage Reference (DAC) ............................... 17
Gain Control Compensation .................................................... 17
Programmable Voltage Source with Boosted Output............ 17
Level Shifting for Different Voltage Operation ...................... 17
Resistance Scaling ...................................................................... 17
Resolution Enhancement .......................................................... 18
RDAC Circuit Simulation Model............................................. 18
AD5171 Evaluation Board ........................................................ 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Functional Descriptions.......................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
One-Time Programming (OTP) .............................................. 11
Determining the Variable Resistance and Voltage ................. 11
Rheostat Mode Operation..................................................... 11
Potentiometer Mode Operation........................................... 12
ESD Protection ........................................................................... 12
Terminal Voltage Operating Range.......................................... 13
Power-Up/Power-Down Sequences......................................... 13
Power Supply Considerations................................................... 13
Controlling the AD5171............................................................ 14
Software Programming ......................................................... 14
REVISION HISTORY
Revision 0: Initial Version
Rev. PrC | Page 2 of 20
AD5171
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Table 1. 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ versions, VDD = 3 V to 5 V 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C,
unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = No Connect,
–0.5
0.2
+0.5
LSB
R
AB = 10 kΩ, 50 kΩ, and 100
kΩ
RWB, VA = No Connect, RAB = 5
kΩ
RWB, VA = No Connect,
RAB = 10 kΩ, 50 kΩ, and 100 kΩ
RWB, VA = No Connect, RAB = 5
kΩ
–1
0.25
0.25
0.5
+1
LSB
LSB
LSB
Resistor Integral Nonlinearity2
R-INL
–1
+1
–1.5
–30
+1.5
+30
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
∆RAB/RAB
(∆RAB/RAB)/∆T
RW
%
35
60
ppm/°C
Ω
VDD = 5 V
115
DC CHARACTERISTICS POTENTIOMETER DIVIDER
MODE (Specifications apply to all RDACs)
Resolution
N
6
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
–0.5
–1
0.1
0.2
5
-0.5
0.5
+0.5
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x20
Code = 0x3F
Code = 0x00, RAB=10 kΩ,
50 kΩ, and 100 kΩ
–1.5
0
+0
1.5
Zero-Scale Error
Code = 0x00, RAB = 5 kΩ
0
2
LSB
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
With respect to GND
f = 1 MHz, measured to GND,
Code = 0x20
f = 1 MHz, measured to GND,
Code = 0x20
VA = VB = VDD/2
VDD
V
pF
Capacitance6 A, B
25
55
1
Capacitance6 W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS
nA
Input Logic High (SDA and SCL)
Input Logic Low (SDA and SCL)
Input Logic High (AD0)
Input Logic Low (AD0)
Input Current
VIH
VIL
VIH
VIL
IIL
0.7 VDD
–0.5
3.0
VDD+0.5
0.3VDD
VDD
1.0
1
V
V
V
V
µA
pF
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
0
Input Capacitance6
CIL
3
3
DIGITAL OUTPUTS
Output Logic Low (SDA)
Three-State Leakage Current (SDA)
Output Capacitance6
POWER SUPPLIES
VOL
IOZ
COZ
IOL = 6 mA
VIN = 0 V or 5 V
0.4
1
V
µA
pF
Power Supply Range
OTP Power Supply7
Supply Current
OTP Supply Current8
Power Dissipation9
Power Supply Sensitivity
VDD
2.7
6
5.5
6.5
8
V
V
µA
mA
mW
%/%
VDD_OTP
IDD
IDD_OTP
PDISS
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 6 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
4
100
0.02
0.04
PSSR
−0.025 +0.001 +0.025
Rev. PrC | Page 3 of 20
AD5171
Preliminary Technical Data
Parameter
DYNAMIC CHARACTERISTICS 6, 10, 11
Symbol
Conditions
Min
Typ1
Max
Unit
Bandwidth –3 dB
BW_5k
BW_10k
BW_50k
BW_100k
THD
RAB = 5 kΩ, Code = 0x20
RAB = 10 kΩ, Code = 0x20
RAB = 50 kΩ, Code = 0x20
RAB = 100 kΩ, Code = 0x20
VA =1 V rms, RAB = 10 kΩ,
VB = 0 V DC, f = 1 kHz
VA= 5 V 1 LSB error band,
VB = 0, measured at VW
VA = 5 V 1 LSB error band,
VB = 0, measured at VW
VA = 5 V 1 LSB error band,
VB = 0, measured at VW
RAB = 5 kΩ, f = 1 kHz,
Code = 0x20
RAB = 10 kΩ, f = 1 kHz,
Code = 0x20
1500
600
110
60
kHz
kHz
kHz
kHz
%
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time12
0.05
tS1
5
µs
tS_OTP
tS2
400
5
ms
Power-up Settling Time—Post Fuses Blown
Resistor Noise Voltage
µs
eN_WB
8
nV/√Hz
nV/√Hz
12
INTERFACE TIMING CHARACTERISTICS
(Applies to all parts6,12
)
SCL Clock Frequency
tBUF Bus Free Time between Start and Stop
tHD;STA Hold Time (Repeated Start)
fSCL
t1
t2
400
kHz
µs
µs
1.3
0.6
After this period, the first
clock pulse is generated
tLOW Low Period of SCL Clock
t3
t4
t5
t6
t7
t8
t9
t10
1.3
0.6
0.6
µs
µs
µs
µs
µs
µs
µs
µs
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
50
0.9
tSU;DAT Data Setup Time
0.1
0.6
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL signals
tSU;STO Setup Time for Stop Condition
0.3
0.3
1Typicals represent average readings at 25°C and VDD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
1 LSB maximum are guaranteed monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Different from operating power supply, power supply for OTP is used one-time only.
8Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value result in the minimum overall power consumption.
11All dynamic characteristics use VDD = 5 V.
12Different from settling time after fuse is blown. The OTP settling time occurs once only.
t6
t9
t8
SCL
SDA
t4
t5
t2
t10
t7
t3
t9
t8
t1
P
S
P
Figure 3. Interface Timing Diagram
Rev. PrC | Page 4 of 20
AD5171
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
VA, VB, VW to GND
Maximum Current
–0.3, +7 V
GND, VDD
I
WB, IWA Pulsed
20 mA
5 mA
5 mA
I
WB Continuous (RWB ≤ 1 kΩ, A open)1
IWA Continuous (RWA ≤ 1 kΩ, B open)1
Digital Inputs and Output Voltage to GND 0 V, VDD
Operating Temperature Range
–40°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature
–65°C to +150°C
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
300°C
215°C
Infrared (15 sec)
220°C
230°C/W
Thermal Resistance2 θJA
1Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2Package Power Dissipation = (TJ max – TA) / θJA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC | Page 5 of 20
AD5171
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
1
2
3
4
8
7
6
5
A
W
AD5171
B
V
DD
TOP VIEW
AD0
SDA
GND
SCL
(Not to Scale)
Figure 4. SOT-23-8
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
W
VDD
Wiper Terminal W. GND ≤ VW ≤ VDD.
Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be a
minimum of 6 V and 100 mA driving capability.
3
4
5
6
7
8
GND
SCL
SDA
AD0
B
Common Ground.
Serial Clock Input. Requires pull-up resistor.
Serial Data Input/Output. Requires pull-up resistor.
I2C Device Address Bit. Allows maximum of two AD5171s to be addressed.
Resistor Terminal B. GND ≤ VB ≤ VDD.
A
Resistor Terminal A. GND ≤ VA ≤ VDD.
Rev. PrC | Page 6 of 20
AD5171
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.10
0.08
0.06
0.04
0.02
0
V
= 5V
V
= 5V
DD
DD
0.08
0.06
–40°C
0.04
+125°C
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
+25°C
+125°C
–40°C
+25°C
0
0
0
8
16
24
32
40
48
56
64
64
64
0
0
8
16
24
32
40
48
56
64
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. R-INL vs. Code vs. Temperature
Figure 8. DNL vs. Code vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
V
= 5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
+25°C
+125°C
V
V
= 5V
= 3V
DD
DD
–0.02
–0.04
–0.06
–0.08
–0.10
–40°C
8
16
24
32
40
48
56
–40
–20
0
20
40
60
80
100
120
140
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 6. R-DNL vs. Code vs. Temperature
Figure 9. Full-Scale Error
0.10
0.08
0.06
0.04
0.02
0
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
DD
+25°C
+125°C
V
V
= 3V
= 5V
DD
DD
–0.02
–0.04
–0.06
–0.08
–0.10
–40°C
8
16
24
32
40
48
56
–40
–20
0
20
40
60
80
100
120
140
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 7. INL vs. Code vs. Temperature
Figure 10. Zero-Scale Error
Rev. PrC | Page 7 of 20
AD5171
Preliminary Technical Data
6
0
10
V
V
= 5V
= 3V
DD
DD
0x20
0x10
–6
–12
–18
–24
–30
–36
–42
–48
–54
0x08
0x04
1
0x02
0x01
0x00
0.1
–40
–20
0
20
40
60
80
100
120
140
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 14. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Figure 11. Supply Current vs. Temperature
180
160
140
120
100
80
6
0
0x3F
0x20
0x10
–6
–12
–18
–24
0x08
0x04
60
0x02
0x01
–30
–36
40
20
–42
0
0x00
–48
–54
–20
–40
0
8
16
24
32
40
48
56
64
100
1k
10k
100k
1M
CODE (DECIMAL)
FREQUENCY (Hz)
Figure 12. Rheostat Mode Tempco (∆RAB/RAB)/ ∆T vs. Code
Figure 15. Gain vs. Frequency vs. Code, RAB = 10 kΩ
6
0
25
20
15
10
5
0x3F
0x20
–6
0x10
0x08
0x04
0x02
0x01
–12
–18
–24
–30
–36
–42
0
–48
–54
0x00
1k
–5
100
10k
100k
1M
0
8
16
24
32
40
48
56
64
CODE (DECIMAL)
FREQUENCY (Hz)
Figure 13. Potentiometer Mode Tempco (∆VW /VW)/ ∆T vs. Code
Figure 16. Gain vs. Frequency vs. Code, RAB = 50
Ω
Rev. PrC | Page 8 of 20
Preliminary Technical Data
AD5171
6
0x3F
0x20
V
V
V
= 5.5V
DD
A
fCBLK = 400kHz
DATA 0x00
0x3F
0
= 5.5V
= GND
–6
0x10
–12
V
= 5V/DIV
0x08
W
–18
0x04
–24
0x02
–30
SCL = 5V/DIV
0x01
–36
–42
–48
0x00
–54
5V
5V
5µs
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 20. Settling Time
Figure 17. Gain vs. Frequency vs. Code, RAB = 100 kΩ
80
60
40
20
0
T
= 25°C
A
V
V
V
= 5.5V
DD
A
CODE = 0x20
= 5.5V
= GND
V
= 2.5V, V = 0V
B
A
fCBLK = 100kHz
V
= 5V DC ± 1.0V p-p AC
DD
0x1F
DATA 0x20
V
= 50mV/DIV
W
V
= 3V DC ± 0.6V p-p AC
DD
SCL = 5V/DIV
50mV
5V
200ns
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 21. Midscale Glitch Energy
Figure 18. PSRR vs. Frequency
V
V
V
= 5.5V
= 5.5V
= GND
fCLK = 100kHz
DD
A
B
OTP PROGRAMMED AT MS
V
V
= 5.5V
DD
= 5.5V
A
R
= 10kΩ
AB
V
= 10mV/DIV
W
V
= 1V/DIV
W
V
= 5V/DIV
SCL = 5V/DIV
500ns
DD
10mV
5V
5µs
1V
5V
Figure 19. Digital Feedthrough vs. Time
Figure 22. Power-Up Settling Time, after Fuses Blown
Rev. PrC | Page 9 of 20
AD5171
Preliminary Technical Data
10.00
V
= V = OPEN
B
A
A
T
= 25°C
R
= 5kΩ
AB
1.00
0.10
0.01
R
= 10kΩ
AB
R
= 50kΩ
AB
R
= 100kΩ
AB
0
8
16
24
32
40
48
56
64
CODE (DECIMAL)
Figure 23. IWB_max vs. Code
Rev. PrC | Page 10 of 20
AD5171
Preliminary Technical Data
THEORY OF OPERATION
The AD5171 allows unlimited 6-bit adjustments, except for one-
time programmable, set-and-forget resistance setting. OTP
technology is a proven cost-effective alternative over EEMEM
in one-time memory programming applications. AD5171
employs fuse link technology to achieve the memory retention
of the resistance setting function. It comprises six data fuses,
which control the address decoder for programming the RDAC,
one user mode test fuse for checking setup error, and one
programming lock fuse for disabling any further programming
once the data fuses are blown.
A
SCL
SDA
DECODER
MUX
DAC
2
I
C INTERFACE
REG.
W
B
COMPARATOR
ONE-TIME
FUSES
EN
FUSE
REG.
PROGRAM/TEST
CONTROL BLOCK
ONE-TIME PROGRAMMING (OTP)
Figure 24. Detailed Functional Block Diagram
Prior to OTP activation, the AD5171 presets to midscale during
power on. After the wiper is set at the desired position, the
resistance can be permanently set by programming the T bit to
high along with the proper coding (Table 7).
DETERMINING THE VARIABLE RESISTANCE
AND VOLTAGE
Rheostat Mode Operation
The device control circuit has two validation bits, E1 and E0,
that can be read back in the read mode for checking the
programming status as shown in Table 4.
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode (Figure 25).
Table 4. Validation Status
A
A
A
E1
E0
Status
W
W
W
0
0
Ready for Programming
0
1
Test Fuse Not Blown Successfully. (For factory
setup checking purpose only. Users should not
see these combinations.)
Error. Some fuses are not blown. Try again.
Successful. No further programming is possible.
B
B
B
Figure 25. Rheostat Mode Configuration
1
1
0
1
The nominal resistance (RAB) of the RDAC has 64 contact
points accessed by the wiper terminal, plus the B terminal
contact if RWB is considered. The 6-bit data in the RDAC latch is
decoded to select one of the 64 settings. Assuming that a 10 kΩ
part is used, the wiper’s first connection starts at the B terminal
for data 0x00. Such connection yields a minimum of 60 Ω
resistance between terminals W and B because of the 60 Ω
wiper contact resistance. The second connection is the first tap
point, which corresponds to 219 Ω (RWB = (1) × RAB/63 + RW)
for data 0x01, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is
reached at 10060 Ω ((63) × RAB/63 + RW). Figure 26 shows a
simplified diagram of the equivalent RDAC circuit. The general
equation determining RWB is
When the OTP T bit is set, the internal clock is enabled. The
program will attempt to blow a test fuse. The operation stops if
this fuse is not blown properly. The validation Bits E1 and E0
show 01, and the users should check the setup. If the test fuse is
blown successfully, the data fuses will be programmed next. The
six data fuses will be programmed in six clock cycles. The
output of the fuses is compared with the code stored in the
DAC register. If they do not match, E1 and E0 = 10 is issued as a
error and the operation stops. Users may retry with the same
codes. If the output and stored code match, the programming
lock fuse will be blown so that no further programming is
possible. In the meantime, E1 and E0 will issue 11 indicating the
lock fuse is blown successfully. All the fuse latches are enabled at
power-on and therefore the output corresponds to the stored
setting from this point on. Figure 24 shows a detailed functional
block diagram.
D
63
R
WB(D) = × RAB + RW
(1)
where:
D is the decimal equivalent of the 6-bit binary code.
R
R
AB is the end-to-end resistance.
W is the wiper resistance contributed by the on-resistance of
the internal switch.
Rev. PrC | Page 11 of 20
AD5171
Preliminary Technical Data
Table 5. RWB vs. Codes; RAB = 10 kΩ and
Potentiometer Mode Operation
the A Terminal Is Opened
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is the
voltage divider operation (Figure 27).
D (Dec)
RWB (Ω)
10060
5139
219
Output State
63
32
1
Full-Scale (RAB + RW)
Midscale
1 LSB
V
I
0
60
Zero-Scale (Wiper Contact Resistance)
A
W
Since a finite wiper resistance of 60 Ω is present in the zero-
scale condition, care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
V
O
B
Figure 27. Potentiometer Mode Configuration
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
complementary resistance RWA. When these terminals are used,
the B terminal can be opened or shorted to W. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
Ignoring the effect of the wiper resistance, the transfer function
is simply
D
VW (D) = VA
(3)
(4)
63
A more accurate calculation, which includes the wiper
resistance effect, yields
63 − D
63
(2)
R
(D) =
×R
+ R
W
D
63
R
WA
AB
RAB + RW
VW (D) =
VA
Table 6. RWA vs. Codes; RAB =10 kΩ and
AB + 2RW
B Terminal Is Opened
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
D (Dec)
RWA (Ω)
Output State
Full-Scale
Midscale
1 LSB
63
32
1
60
metric function of D/63 with a relatively small error contributed
by the RW terms, and therefore the tolerance effect is almost
cancelled. Although the thin film step resistor RS and CMOS
switches resistance RW have very different temperature coefficients,
the ratio-metric adjustment also reduces the overall temperature
coefficient effect to 5 ppm/oC, except at low value codes where RW
dominates.
4980
9901
10060
0
Zero-Scale
The typical distribution of the resistance tolerance from device
to device is process lot dependent, and it is possible to have
30ꢀ tolerance.
Potentiometer mode operations include others such as op amp
input, feedback resistor networks, and other voltage scaling
applications. A, W, and B terminals can in fact be input or output
terminals provided that |VAB|, |VWA|, and |VWB| do not exceed
VDD to GND.
A
D5
D4
D3
D2
D1
D0
R
S
R
S
ESD PROTECTION
W
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (Figure 28).
340Ω
LOGIC
R
RDAC
S
LATCH
AND
B
DECODER
Figure 28. ESD Protection of Digital Pins
Figure 26. AD5171 Equivalent RDAC Circuit
Rev. PrC | Page 12 of 20
AD5171
Preliminary Technical Data
TERMINAL VOLTAGE OPERATING RANGE
CONNECT J1
There are also ESD protection diodes between VDD and the
RDAC terminals. The VDD of AD5171 therefore defines their
voltage boundary conditions, see Figure 29. Supply signals
present on terminals A, B, and W that exceed VDD will be
clamped by the internal forward-biased diodes and should be
avoided.
HERE FOR OTP
6V
J1
R1
V
DD
50kΩ
C1
C2
1µF
0.1µF
AD5171
R2
5V
250kΩ
CONNECT J1
HERE AFTER OTP
V
DD
Figure 30. Power Supply Requirement
A
W
B
An alternate approach in 3.5 V to 5.5 V systems adds a signal
diode between the system supply and the OPT supply for
isolation, as shown in Figure 31.
GND
APPLY FOR OTP ONLY
6V
D1
Figure 29. Maximum Terminal Voltages Set by VDD
V
3.5V–5.5V
DD
C1
C2
10µF
0.1µF
AD5171
POWER-UP/POWER-DOWN SEQUENCES
Similarly, because of the ESD protection diodes, it is important
to power VDD first before applying any voltages to terminals A,
B, and W. Otherwise, the diode will be forward-biased such that
VDD will be powered unintentionally and may affect the rest of
the users’ circuits. The ideal power-up sequence is in the
following order: GND, VDD, digital inputs, and VA/VB/VW. The
order of powering VA, VB, VW, and digital inputs is not
important as long as they are powered after VDD. Similarly, VDD
should be powered down last.
Figure 31. Isolating the 6 V OPT Supply from the 3.5V to 5.5 V Normal
Operating Supply. The 6 V supply must be removed once OPT is complete.
APPLY FOR OTP ONLY
6V
R1
10kΩ
V
2.7V
DD
POWER SUPPLY CONSIDERATIONS
C1
C2
10µF
0.1µF
AD5171
P1
P2
To minimize the package pin count, both the one-time
programming and normal operating voltages are applied to the
same VDD terminal of the AD5171. The AD5171 employs fuse
link technology that requires 6 V to blow the internal fuses to
achieve a given setting. On the other hand, it operates at 2.7 V to
5.5 V once the programming is complete. Such dual voltage
requires isolation between supplies. The fuse programming
supply (either an on-board regulator or rack-mount power
supply) must be rated at 6 V and be able to handle 400 ms and
100 mA of transient current for one-time programming. Once
programming is complete, the 6 V supply must be removed to
allow normal operation of 2.7 V to 5.5 V. Figure 30 shows the
simplest implementation using a jumper. This approach saves
one voltage supply, but draws additional current and requires
manual configuration.
P1 = P2 = FDV302P, NDS0610
Figure 32. Isolating the 6 V OPT Supply from the 2.7 V Normal Operating
Supply. The 6 V supply must be removed once OPT is complete.
For users who operate their systems at 2.7 V, it is recommended
to use the bi-directional low-threshold P-Ch MOSFETs for the
supplies isolation. As shown in Figure 32 assumes the 2.7 V
system voltage is applied first but not the 6 V. The gates of P1
are P2 are pulled to ground, which turns on P1 and subse-
quently P2. As a result, VDD of AD5171 becomes 2.7 V minus a
few tenths of mV drop across P1 and P2. When the AD5171
setting is found, the factory tester applies the 6 V to VDD and
also to the gates of P1 and P2 to turn them off. While the OTP
command is executing at this time to program AD5171, the
2.7 V source is therefore protected. Once the OTP is complete,
the tester withdraws the 6 V, and AD5171 setting is permanently
fixed.
Rev. PrC | Page 13 of 20
AD5171
Preliminary Technical Data
Read
CONTROLLING THE AD5171
To read the validation bits and data out from the device, the
user may simply press the Read button. The user may also set
the bit pattern in the upper screen and press the Run button.
The format of reading data out from the device is shown in
Table 8.
To apply the device programming software in the factory, users
need to modify a parallel port cable and configure Pins 2, 3, 15,
and 25 for SDA_write, SCL, SDA_read, and DGND, respectively
for the control signals (Figure 34). Users should also layout the
PCB of the AD5171 with SCL and SDA pads, as shown in
Figure 35, such that pogo pins can be inserted for the factory
programming.
There are two ways of controlling the AD5171. Users can either
program the devices with computer software or external I2C
controllers.
Software Programming
Due to the advantage of the one-time programmable feature,
users may consider programming the device in the factory
before shipping to end users. ADI offers a device programming
software, which can be implemented in the factory on PCs that
run Windows 95 to XP platforms. As a result, external control-
lers are not required, which significantly reduces development
time. The program is an executable file that does not require
any programming languages or user programming skills. It is
easy to set up and use. Figure 33 shows the software interface.
The software can be downloaded from www.analog.com.
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
R3
100Ω
R2
SCL
SDA
READ
100Ω
R1
WRITE
100Ω
1
Figure 33. AD5171 Computer Software Interface
Figure 34. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND
Write
The AD5171 starts at midscale after power-up prior to the OPT
programming. To increment or decrement the resistance, the
user may simply move the scrollbar on the left. To write any
specific values, the user should use the bit pattern control in the
upper screen and press the Run button. The format of writing
data to the device is shown in Table 7. Once the desirable setting
is found, the user may press the Program Permanent button to
blow the internal fuse links for permanent setting. The user may
also set the programming bit pattern in the upper screen and
press the Run button to achieve the same result.
W
A
V
B
DD
DGND
SCL
AD0
SDA
Figure 35. Recommended AD5171 PCB Layout. The SCL and SDA pads allow
pogo pins to be inserted so that signals can be communicated through the
parallel port for programming (Figure 34).
Table 7. SDA Write Mode Bit Format
S
0
1
0
1
1
0
AD0
0
A
T
X
X
X
X
X
X
X
A
X
X
D5 D4 D3 D2 D1 D0
Data Byte
A
P
Slave Address Byte
Instruction Byte
Table 8. SDA Read Mode Bit Format
S
0
1
0
1
1
0
AD0
1
A
E1
E0
D5
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Data Byte
Rev. PrC | Page 14 of 20
AD5171
Preliminary Technical Data
Table 9. SDA Bits Definitions and Descriptions
Bit
Description
Bit
Description
S
P
Start Condition.
Stop Condition.
Acknowledge.
D5, D4, D3,
D2, D1, D0
E1, E0
0, 0
0, 1
1, 0
Data Bits.
A
OTP Validation Bits.
Ready to Program.
Test Fuse Not Blown Successfully. (For Factory Setup Checking
Purpose Only. Users should not see these combinations).
Fatal Error. Try again.
Programmed Successfully. No further adjustments possible.
AD0 I2C Device Address Bit. Allows maximum of
two AD5171s to be addressed.
X
T
Don’t Care.
OTP Programming Bit. Logic 1 programs wiper
position permanently.
1, 1
I2C Controller Programming
Write Bit Pattern Illustrations
1
9
1
0
9
1
9
SCL
0
R/W
0
1
0
1
1
AD0
X
X
X
X
X
X
X
X
X
D5 D4 D3 D2 D1 D0
SDA
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
START BY
MASTER
STOP BY
MASTER
DATA BYTE
Figure 36. Writing to the RDAC Register
1
9
1
9
1
9
SCL
SDA
X
X
X
X
X
X
X
X
D5 D4 D3 D2 D1 D0
ACK. BY
0
1
0
1
1
0
AD0
R/W
1
X
ACK. BY
ACK. BY
AD5171
AD5171
AD5171
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
STOP BY
MASTER
START BY
MASTER
DATA BYTE
Figure 37. Activating One-Time Programming
Read Bit Pattern Illustration
1
0
9
1
9
SCL
SDA
E1 E0 D5 D4 D3 D2 D1 D0
1
0
1
1
0
AD0 R/W
ACK. BY
AD5171
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
START BY
MASTER
RDAC REGISTER
Figure 38. Reading Data from RDAC Register
For users who prefer to use external controllers, the AD5171
can be controlled via an I2C compatible serial bus and is
connected to this bus as slave device. Referring to Figure 36,
Figure 37, and Figure 38, the 2-wire I2C serial bus protocol
operates as follows:
address defined as 010110. The next bit is AD0, which is an
I2C device address bit. Depending on the states of their
AD0 bits, two AD5171 can be addressed on the same bus
W
(Figure 39). The last LSB is the R/ bit, which determines
whether data will be read from or written to the slave
device.
1. The master initiates data transfer by establishing a start
condition, which is when SDA from high-to-low while SCL
is high (Figure 36 and Figure 37). The following byte is the
slave address byte, which consists of the 6 MSBs as a slave
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line goes low during
the 9th clock pulse (this is termed the Acknowledge bit). At
Rev. PrC | Page 15 of 20
AD5171
Preliminary Technical Data
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte will update the RDAC
output. For example, after the RDAC has acknowledged its slave
address and instruction bytes, the RDAC output will update
after these two bytes. If another byte is written to the RDAC
while it is still addressed to a specific slave device with the same
instruction, this byte will update the output of the selected slave
device. If different instructions are needed, the write mode has
to be started with a new slave address, instruction, and data
bytes. Similarly, a repeated read function of the RDAC is also
allowed.
2. The write operation contains one more instruction byte
than the read operation. The instruction byte in the write
mode follows the slave address byte. The MSB of the
instruction byte labeled T is the one-time programming
bit. After acknowledging the instruction byte, the last byte
in the write mode is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an Acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (Figure 36).
CONTROLLING TWO DEVICES ON ONE BUS
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (slight difference with the write mode; there are
eight data bits followed by a No Acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (Figure 38).
Figure 39 shows two AD5171 devices on the same serial bus.
Each has a different slave address since the state of each AD0
pin is different. This allows each device to be operated
independently. The master device output bus line drivers are
open-drain pull-downs in a fully I2C compatible interface.
5V
Rp
Rp
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In the write mode, the master will pull the
SDA line high during the 10th clock pulse to establish a stop
condition (Figure 36 and Figure 37). In the read mode, the
master will issue a No Acknowledge for the 9th clock pulse,
i.e., the SDA line remains high. The master will then bring
the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (Figure 38).
SDA
SCL
MASTER
SCL
SDA
AD0
SCL
SDA
AD0
5V
AD5171
AD5171
Figure 39. Two AD5171 Devices on One Bus
Rev. PrC | Page 16 of 20
AD5171
Preliminary Technical Data
APPLICATIONS
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-Ch
FET N1. N1 power handling must be adequate to dissipate
(VI − VO) × IL power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
reference such as ADR421, ADR03, or ADR370 can be applied
at the A terminal of the digital potentiometer.
PROGRAMMABLE VOLTAGE REFERENCE (DAC)
It is common to buffer the output of the digital potentiometer
as a DAC unless the load is much larger than RWB. The buffer
serves the purpose of impedance conversion as well as
delivering higher current, which may be needed.
5V
AD5171
1
U1
V
5V
V
IN
A
OUT
3
ADR03
W
U2
AD8601
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
V
0
AD1582
B
GND
2
A1
When users need to interface a 2.5 V controller with AD5171, a
proper voltage level shift must be employed so that the digital
potentiometer can be read from or written to the controller;
Figure 43 shows one of the implementations. M1 and M2
should be low threshold N-Ch power MOSFETs, such as
FDV301N.
Figure 40. Programmable Voltage Reference (DAC)
GAIN CONTROL COMPENSATION
The digital potentiometers are commonly used in gain controls
(Figure 41) or sensor transimpedance amplifier signal
conditioning applications. To avoid gain peaking or in worst-
case oscillation due to step response, a compensation capacitor
is needed. In general, C2 in the range of a few picofarads to no
more than a few tenths of a picofarad is adequate for the
compensation.
V
= 2.5V
V
= 5V
DD2
DD1
Rp
Rp
Rp
Rp
G
G
D
S
SDA1
SCL1
SDA2
SCL2
D
S
M1
C2
M2
4.7pF
2.7V–5.5V
AD5171
2.5V
CONTROLLER
R2 100kΩ
B
A
W
Figure 43. Level Shifting for Different Voltage Operation
R1
47kΩ
V
U1
O
RESISTANCE SCALING
V
I
The AD5171 offers 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ nominal
resistances. For users who need to optimize the resolution with
an arbitrary full-range resistance, the following techniques can
be used. By paralleling a discrete resistor (Figure 44) a
proportion tely lower voltage appears at terminal A to B, which
is applicable to only the voltage divider mode.
Figure 41. Typical Noninverting Gain Amplifier
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (Figure 42).
This translates into a finer degree of precision because the step
size at terminal W will be smaller. The voltage can be found as
U3 2N7002
(RAB ||R2)
R3 + RAB ||R2 64
D
V
V
VW (D) =
×
×VDD
(5)
OUT
IN
C
R
BIAS
A
B
C
U1
AD5171
+V
U2
W
V
DD
R3
I
L
AD8601
LD
–V
A
W
SIGNAL
R2
R1
B
Figure 42. Programmable Booster Voltage Source
Figure 44. Lowering the Nominal Resistance
Rev. PrC | Page 17 of 20
AD5171
Preliminary Technical Data
For log taper adjustment, such as volume control, Figure 45
shows another way of resistance scaling to achieve the log taper
function. In this circuit, the smaller the R2 with respect to RAB,
the more like the pseudo log taper characteristic it behaves. The
wiper voltage is simply
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentio-
meters. Configured as a potentiometer divider, the –3 dB
bandwidth of the AD5171 (5 kΩ resistor) measures 1.5 MHz at
half scale. Figure 14 to Figure 17 provide the large signal BODE
plot characteristics of the four available resistor versions 5 kΩ
10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is
shown in Figure 47. Listing 1 provides a macro model net list
for the 10 kΩ device.
(RWB ||R2)
WA + RWB ||R2
VW (D) =
×VI
(6)
R
V
I
A
RDAC
V
O
A
B
10kΩ
R1
W
C
C
C
W
A
B
25pF
25pF
B
R2
55pF
W
Figure 45. Resistor Scaling with Log Adjustment Characteristics
Figure 47. Circuit Simulation Model for RDAC = 10 kΩ
RESOLUTION ENHANCEMENT
Listing 1. Macro Model Net List for RDAC
The resolution can be doubled in the potentiometer mode of
operation by using three digital potentiometers. Borrowed from
ADI’s patented RDAC segmentation technique, users can con-
figure three AD5171 (Figure 46) to double the resolution. First,
U3 must be parallel with a discrete resistor RP, which is chosen
to be equal to a step resistance (RP = RAB/64). One can see that
adjusting U1 and U2 together forms the coarse 6-bit adjustment
.PARAM D=64, RDAC=10E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
A
W
W
B
0
W
0
B
0
25E-12
RWA
CW
{(1-D/64)*RDAC+60}
55E-12
and that adjusting U3 alone forms the finer 6-bit adjustment. As a
result, the effective resolution becomes 12-bit.
RWB
CB
{D/64*RDAC+60}
25E-12
*
A1
W1
U1
.ENDS DPOT
A3
W3
B1
R
P
U3
A2
B3
W2
U2
B2
COARSE
FINE
ADJUSTMENT ADJUSTMENT
Figure 46. Doubling the Resolution
Rev. PrC | Page 18 of 20
AD5171
Preliminary Technical Data
AD5171 EVALUATION BOARD
JP5
JP3
V
CC
V
DD
V+
U4
TEMP
C6
C7
10µF
5
4
1
2
3
0.1µF
TRIM
GND
CP3
CP1
V
CP4
V
DD
V
V
REF
IN
OUT
–IN1
C5
C4
ADR03
0.1µF
0.1µF
CP2
U3A
JP1
JP2
JP8
IN
8
4
2
3
OUT1
A
1
JP7
W
B
V
CP6
CP7 OUT1
V
DD
V–
V
DD
CP5
+IN1
C1
10µF
U2
U1
1
8
7
6
5
1
2
3
4
8
7
6
5
R2
W
A
B
W
A
B
R1
2
3
4
JP4
10kΩ
J1
V
V
DD
DD
AGND
10kΩ
C2
GND AD0
GND AD0
SCL SDA
C3
0.1µF
8
7
6
5
4
3
2
1
0.1µF
SCL SDA
C8
SCL
C9
AD5171/AD5273
AD5170
0.1µF
JP6
10µF
SDA
V
EE
6
–IN2
+IN2
7
OUT2
5
U3B
Figure 48. AD5171 Evaluation Board Schematic
The AD5171 evaluation board comes with a dual op amp
AD822 and a 2.5 V reference ADR03. Users can configure many
other building block circuits with minimum components
needed. Figure 49 shows one of the examples. There is space
available on the board that users can build additional circuits
for further evaluations, see Figure 50.
CP2
V
REF
V
DD
JP3
2
JP1
V
REF
U3A
A
4
A
V+
1
V
O
W
JP7
OUT1
AD822
U2
V–
W
3
11
B
B
JP4
JP2
Figure 50. AD5171 Evaluation Board
Figure 49. Programmable Voltage Reference
Rev. PrC | Page 19 of 20
AD5171
Preliminary Technical Data
OUTLINE DIMENSIONS
2.90 BSC
8
1
7
2
6
3
5
4
2.80 BSC
1.60 BSC
PIN 1
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 51. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB (kΩ)
Package Code
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
Package Description
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
SOT-23-8
Full Container Quantity
Branding
D12
D13
D14
D15
D12
D13
D14
D15
AD5171BRJ5-RL7
AD5171BRJ10-RL7
AD5171BRJ50-RL7
AD5171BRJ100-REEL7
AD5171BRJ5-R2
AD5171BRJ10-R2
AD5171BRJ50-R2
AD5171BRJ100-R2
AD5171EVAL*
5
3000
3000
3000
3000
3000
3000
3000
3000
1
10
50
100
5
10
50
100
10
* The evaluation board is shipped with three pieces of 10 kΩ parts. Users should order extra samples or different resistance options if needed.
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03437-0-9/03(PrC)
Rev. PrC | Page 20 of 20
相关型号：
AD5171BRJZ10-RL7
10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8, MO-178-BA, SOT-23, 8 PIN
ADI
AD5171BRJZ50-R2
50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8, LEAD FREE, MO-178-BA, SOT-23, 8 PIN
ROCHESTER
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