AD5170BRM10_技术文档

256-Position Two-Time Programmable

I²C Digital Potentiometer

AD5170

FUNCTIONAL BLOCK DIAGRAM

FEATURES

256-position

A

W

B

TTP (two-time programmable) set-and-forget resistance

setting allows second-chance permanent programming

Unlimited adjustments prior to OTP (one-time

programming) activation

FUSE

LINKS

OTP overwrite allows dynamic adjustments with user

defined preset

V

DD

1

2

End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Compact MSOP-10 (3 mm × 4.9 mm) package

Fast settling time: t_S= 5 µs typ in power-up

Full read/write of wiper register

RDAC

REGISTER

GND

AD0

AD1

ADDRESS

DECODE

8

Power-on preset to midscale

Extra package address decode pins AD0 and AD1

Single-supply 2.7 V to 5.5 V

SDA

SCL

SERIAL INPUT

REGISTER

Low temperature coefficient: 35 ppm/°C

Low power, I_DD= 6 µA maximum

Figure 1.

Wide operating temperature: –40°C to +125°C

Evaluation board and software are available

Software replaces µC in factory programming applications

APPLICATIONS

Systems calibration

The AD5170 is programmed using a 2-wire, I²C® compatible

digital interface. Unlimited adjustments are allowed before

permanently (there are actually two opportunities) setting the

resistance value. During OTP activation, a permanent blow fuse

command freezes the wiper position (analogous to placing

epoxy on a mechanical trimmer).

Electronics level setting

Mechanical Trimmers® replacement in new designs

Permanent factory PCB setting

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

RF amplifier biasing

Automotive electronics adjustment

Gain control and offset adjustment

Unlike traditional OTP digital potentiometers, the AD5170 has

a unique temporary OTP overwrite feature that allows for new

adjustments even after the fuse has been blown. However, the

OTP setting is restored during subsequent power-up

conditions. This feature allows users to treat these digital

potentiometers as volatile potentiometers with a programmable

preset.

GENERAL OVERVIEW

The AD5170 is a 256-position, two-time programmable (TTP)

digital potentiometer¹that employs fuse link technology to

enable two opportunities at permanently programming the

resistance setting. OTP is a cost-effective alternative to EEMEM

for users who do not need to program the digital potentiometer

setting in memory more than once. This device performs the

same electronic adjustment function as mechanical

potentiometers or variable resistors with enhanced resolution,

solid-state reliability, and superior low temperature coefficient

performance.

For applications that program the AD5170 at the factory,

Analog Devices offers device programming software running

on Windows NT®, 2000, and XP® operating systems. This

software effectively replaces any external I²C controllers, thus

enhancing the time-to-market of the user’s systems.

¹The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD5170

TABLE OF CONTENTS

Electrical Characteristics — 2.5 kΩ ............................................... 3

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence ................................................................... 14

Power Supply Considerations................................................... 14

Layout Considerations............................................................... 15

Evaluation Software/Hardware..................................................... 16

Software Programming ............................................................. 16

I²C Interface .................................................................................... 18

I²C Compatible 2-Wire Serial Bus ........................................... 20

Pin Configuration and Function Descriptions........................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Electrical Characteristics — 10 kΩ, 50 kΩ, 100 kΩ Versions..... 4

Timing Characteristics — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Versions.............................................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

One-Time Programming (OTP) .............................................. 12

Programming the Variable Resistor and Voltage ................... 12

Programming the Potentiometer Divider............................... 13

ESD Protection ........................................................................... 14

REVISION HISTORY

11/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Electrical Characteristics Table 1............................... 3

Changes to Electrical Characteristics Table 2............................... 4

Changes to One-Time Programming ......................................... 12

Changes to Figure 37, Figure 38, and Figure 39 ........................ 14

Changes to Power Supply Considerations................................... 14

Changes to Figure 40...................................................................... 15

Changes to Layout Considerations .............................................. 15

11/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD5170

ELECTRICAL CHARACTERISTICS — 2.5 kΩ

V_DD= 5 V 10% or 3 V 10%, V_A= +V_DD, V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R_WB(Wiper Resistance)

R-DNL

R-INL

∆R_AB

R_WB, V_A= no connect

T_A= 27°C

–2

–6

–2±

±±.1

±±.ꢀ7 +6

+77

37

16±

+2

LSB

%

ppm/°C

Ω

(∆R_AB/R_AB)/∆T V_AB= V_DD, Wiper = no connect

R_WBCode = ±x±±, V_DD= 7 V

2±±

DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient (∆V_W/V_W)/∆T

Full-Scale Error

Zero-Scale Error

DNL

INL

–1.7 ±±.1

+1.7

+2

LSB

ppm/°C

LSB

–2

±±.6

17

Code = ±x8±

Code = ±xFF

Code = ±x±±

V_WFSE

V_WZSE

–1±

±

–2.7

2

±

1±

RESISTOR TERMINALS

Voltage Range⁷

V_A,V_B,V_W

C_A, C_B

C_W

I_{A_SD}

I_CM

GND

V_DD

V

Capacitance⁶A, B

f = 1 MHz, measured to GND, code = ±x8±

V_DD= 7.7 V

47

6±

±.±1

1

pF

µA

nA

Capacitance W

Shutdown Supply Current^ꢀ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

1

V_A= V_B= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 7 V

V_DD= 3 V

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁷

±.8

±.6

±1

V_IN= ± V or 7 V

C_IL

7

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage

Supply Current

OTP Supply Current

Power Dissipation⁸

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS⁹

Bandwidth –3 dB

V_{DD RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.ꢀ

7.27

7.7

6

V

µA

mA

µW

T_A= 27°C

V_IH= 7 V or V_IL= ± V

V_{DD_OTP}= 7.7 V, T_A= 27°C

V_IH= 7 V or V_IL= ± V, V_DD= 7 V

V_DD= 7 V ± 1±%, Code = midscale

3.7

1±±

3±

PSS

±±.±2 ±±.±8 %/%

BW_2.7K

THD_W

t_S

Code = ±x8±

4.8

±.1

1

MHz

%

µs

Total Harmonic Distortion

V_WSettling Time

Resistor Noise Voltage Density

V_A= 1 V rms, V_B= ± V, f = 1 kHz

V_A= 7 V, V_B= ± V, ±1 LSB error band

R_WB= 1.27 kΩ, R_S= ±

e_{N_WB}

3.2

nV/√Hz

¹Typical specifications represent average readings at 27°C and V_DD= 7 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, Wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= ± V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁷Resistor terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

^ꢀMeasured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁹All dynamic characteristics use V_DD= 7 V.

Rev. A | Page 3 of 24

AD5170

ELECTRICAL CHARACTERISTICS — 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

V_DD= 5 V 10% or 3 V 10%, V_A= V_DD; V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R_WB(Wiper Resistance)

R-DNL

R-INL

∆R_AB

(∆R_AB/R_AB)/∆T

R_WB

R_WB, V_A= no connect

–1

–2.7

–2±

±±.1

±±.27 +2.7

+2±

37

16±

+1

LSB

%

ppm/°C

Ω

R_WB, V_A= no connect

T_A= 27°C

V_AB= V_DD, wiper = no connect

Code = ±x±±, V_DD= 7 V

2±±

DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature

Coefficient

DNL

INL

–1

±±.1

±±.3

17

+1

LSB

ppm/°C

Code = ±x8±

(∆V_W/V_W)/∆T

Full-Scale Error

Zero-Scale Error

V_WFSE

V_WZSE

Code = ±xFF

Code = ±x±±

–2.7

±

–1

1

±

2.7

LSB

RESISTOR TERMINALS

Voltage Range⁷

GND

V_DD

V

V_A,V_B,V_W

C_A,C_B

C_W

I_{A_SD}

I_CM

Capacitance⁶A, B

f = 1 MHz, measured to GND, code = ±x8±

V_DD= 7.7 V

47

6±

±.±1

1

pF

µA

nA

Capacitance⁶W

Shutdown Supply Current^ꢀ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

1

V_A= V_B= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 7 V

V_DD= 3 V

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

±.8

±.6

±1

V_IN= ± V or 7 V

C_IL

7

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage⁸

Supply Current

OTP Supply Current⁹

Power Dissipation^1±

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS¹¹

Bandwidth –3 dB

V_{DD RANGE}

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

2.ꢀ

7.27

7.7

6

V

µA

mA

µW

V_IH= 7 V or V_IL= ± V

3.7

1±±

V_{DD_OTP}= 7.7 V, T_A= 27°C

V_IH= 7 V or V_IL= ± V, V_DD= 7 V

V_DD= 7 V ± 1±%, code = midscale

3±

PSS

±±.±2 ±±.±8 %/%

BW

R_AB= 1± kΩ, code = ±x8±

R_AB= 7± kΩ, code = ±x8±

R_AB= 1±± kΩ, code = ±x8±

V_A=1 V rms, V_B= ± V, f = 1 kHz, R_AB= 1± kΩ

V_A= 7 V, V_B= ± V, ±1 LSB error band

6±±

1±±

4±

±.1

2

kHz

%

Total Harmonic Distortion

V_WSettling Time

THD_W

t_S

µs

(1± kΩ/7± kΩ/1±± kΩ)

Resistor Noise Voltage Density

e_{N_WB}

R_WB= 7 kΩ, R_S= ±

9

nV/√Hz

¹Typical specifications represent average readings at 27°C and V_DD= 7 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, Wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= ± V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁷Resistor terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

^ꢀMeasured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸Different from operating power supply, power supply OTP is used one time only.

⁹Different from operating current, supply current for OTP lasts approximately 4±± ms for one time only.

1±

P

is calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

DISS

¹¹All dynamic characteristics use V_DD= 7 V.

Rev. A | Page 4 of 24

AD5170

TIMING CHARACTERISTICS — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

V_DD= 5 V 10% or 3 V 10%, V_A= V_DD; V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Conditions

Min Typ Max

Unit

I²C INTERFACE TIMING CHARACTERISTICS¹(Specifications apply to all parts)

SCL Clock Frequency

t_BUFBus Free Time between STOP and START

t_HD;STAHold Time (Repeated START)

f_SCL

t₁

t₂

4±±

kHz

µs

1.3

±.6

After this period, the first clock

pulse is generated.

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time for Repeated START Condition

t_HD;DATData Hold Time²

t_SU;DATData Setup Time

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSetup Time for STOP Condition

t₃

t₄

t₇

t₆

t_ꢀ

t₈

t₉

t_1±

1.3

±.6

±.9

1±±

3±±

±.6

µs

ns

µs

¹See timing diagrams for locations of measured values.

²The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

Rev. A | Page 7 of 24

AD5170

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Value

V_DDto GND

V_A, V_B, V_Wto GND

Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx¹

–±.3 V to +ꢀ V

V_DD

Pulsed

±2± mA

Continuous

±7 mA

Digital Inputs and Output Voltage to GND

Operating Temperature Range

± V to ꢀ V

–4±°C to +127°C

17±°C

–67°C to +17±°C

3±±°C

Maximum Junction Temperature (T_JMAX

Storage Temperature

)

Lead Temperature (Soldering, 1± sec)

Thermal Resistance²θ_JA: MSOP-1±

23±°C/W

¹Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 6 of 24

AD5170

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

0.5

0.4

T

= 25°C

R

= 10kΩ

A

AB

R

= 10kΩ

AB

1.5

1.0

0.3

V

= 2.7V

DD

0.2

0.5

0.1

V

= 2.7V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0

V

= 5.5V

DD

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 2. R-INL vs. Code vs. Supply Voltages

Figure 5. DNL vs. Code vs. Temperature

0.5

0.4

1.0

0.8

T

R

= 25°C

T

R

= 25°C

= 10kΩ

A

= 10kΩ

AB

0.3

0.6

0.2

0.4

V

= 2.7V

DD

V

= 5.5V

0.1

0.2

DD

0

V

= 2.7V

DD

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 5.5V

DD

32

64

96

128

160

192

224

256

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 3. R-DNL vs. Code vs. Supply Voltages

Figure 6. INL vs. Code vs. Supply Voltages

0.5

0.4

0.5

0.4

R

= 10kΩ

T

R

= 25°C

= 10kΩ

AB

A

AB

0.3

V

= 5.5V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0.2

0.1

V

= 2.7V

DD

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

V

= 2.7V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

32

64

96

128

160

192

224

256

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 4. INL vs. Code vs. Temperature

Figure 7. DNL vs. Code vs. Supply Voltages

Rev. A | Page ꢀ of 24

AD5170

2.0

4.50

3.75

3.00

2.25

1.50

0.75

0

R

= 10kΩ

R

= 10kΩ

AB

1.5

1.0

V

= 2.7V

DD

= –40°C, +25°C, +85°C, +125°C

T

A

0.5

0

V

= 2.7V, V = 2.7V

A

DD

V

= 5.5V

DD

= –40°C, +25°C, +85°C, +125°C

–0.5

–1.0

–1.5

–2.0

T

A

V

= 5.5V, V = 5.0V

A

DD

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 8. R-INL vs. Code vs. Temperature

Figure 11. Zero-Scale Error vs. Temperature

0.5

0.4

10

R

= 10kΩ

AB

0.3

V

= 5V

DD

0.2

V

= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0.1

0

1

–0.1

–0.2

–0.3

–0.4

–0.5

= 3V

DD

0.1

–40

0

32

64

96

128

160

192

224

256

–7

26

59

92

125

TEMPERATURE (°C)

CODE (DECIMAL)

Figure 9. R-DNL vs. Code vs. Temperature

Figure 12. Supply Current vs. Temperature

120

100

80

2.0

1.5

R

= 10kΩ

R

= 10kΩ

AB

1.0

0.5

60

V

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

T

A

0

V

= 5.5V, V = 5.0V

A

DD

40

V

= 5.5V

DD

= –40°C TO +85°C, –40°C TO +125°C

–0.5

–1.0

–1.5

–2.0

T

A

20

V

= 2.7V, V = 2.7V

A

DD

0

–20

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 13. Rheostat Mode Tempco ∆R_WB/∆T vs. Code

Figure 10. Full-Scale Error vs. Temperature

Rev. A | Page 8 of 24

AD5170

50

40

0

–6

R

= 10kΩ

AB

0x80

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

30

V

T

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

20

A

0x08

0x04

0x02

0x01

10

0

–10

–20

–30

V

= 5.5V

DD

= –40°C TO +85°C, –40°C TO +125°C

T

A

0

32

64

96

128

160

192

224

256

1k

10k

100k

1M

CODE (DECIMAL)

FREQUENCY (Hz)

Figure 14. Potentiometer Mode Tempco ∆V_WB/∆T vs. Code

Figure 17. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

0

–6

0

–6

0x80

0x40

0x20

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

0x08

0x04

0x02 0x01

10k

100k

FREQUENCY (Hz)

1M

10M

10k

100k

FREQUENCY (Hz)

1M

Figure 15. Gain vs. Frequency vs. Code, R_AB= 2.5 kΩ

Figure 18. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

0

–6

0

–6

0x80

0x40

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

100kΩ

60kHz

50kΩ

0x20

0x10

0x08

0x04

120kHz

10kΩ

570kHz

2.5kΩ

2.2MHz

0x02

0x01

1k

10k

100k

FREQUENCY (Hz)

1M

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 16. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

Figure 19. –3 dB Bandwidth at Code = 0x80

Rev. A | Page 9 of 24

AD5170

10

T

= 25°C

A

1

V

= 5.5V

DD

V

W

0.1

V

= 2.7V

DD

0.01

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 22. Midscale Glitch, Code 0x80 to 0x7F

Figure 20. I_DDvs. Input Voltage

V

W

SCL

Figure 21. Digital Feedthrough

Figure 23. Large Signal Settling Time

Rev. A | Page 1± of 24

AD5170

TEST CIRCUITS

Figure 24 to Figure 29 illustrate the test circuits that define the

test conditions used in the product specification tables.

V

V+ = V

1LSB = V+/2

A

DUT

W

DD

V+ = V ± 10%

DD

N

∆V

MS

A

B

DUT

W

PSRR (dB) = 20 LOG

(

)

∆V

DD

∆V

%

V+

A

B

MS

DD

∆V

PSS (%/%) =

DD

V+

V

MS

V

MS

Figure 24. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 27. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

NO CONNECT

DUT

+15V

A

W

I

V

IN

W

A

W

AD8610

–15V

V

B

OUT

OFFSET

GND

B

V

2.5V

MS

Figure 25. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 28. Test Circuit for Gain vs. Frequency

NC

DUT

I

= V /R

DD NOMINAL

W

A

B

DUT

V

W

A

B

I

CM

V

MS2

V

DD

W

R

= [V

– V

]/I

MS2 W

W

MS1

GND

V

MS1

V

CM

NC NC = NO CONNECT

Figure 26. Test Circuit for Wiper Resistance

Figure 29. Test Circuit for Common-Mode Leakage Current

Rev. A | Page 11 of 24

AD5170

THEORY OF OPERATION

A

SCL

SDA

DECODER

MUX

DAC

REG.

2

I C INTERFACE

W

B

COMPARATOR

FUSES

EN

FUSE

REG.

ONE-TIME

PROGRAM/TEST

CONTROL BLOCK

Figure 30. Detailed Functional Block Diagram

The AD5170 is a 256-position, digitally controlled variable

resistor (VR) that employs fuse link technology to achieve

memory retention of resistance setting.

PROGRAMMING THE VARIABLE RESISTOR AND

VOLTAGE

Rheostat Operation

The nominal resistance of the RDAC between Terminal A and

Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.

The nominal resistance (R_AB) of the VR has 256 contact points

accessed by the wiper terminal, plus the B terminal contact. The

8-bit data in the RDAC latch is decoded to select one of 256

possible settings.

An internal power-on preset places the wiper at midscale

during power-on. If the OTP function has been activated, the

device powers up at the user-defined permanent setting.

ONE-TIME PROGRAMMING (OTP)

Prior to OTP activation, the AD5170 presets to midscale during

initial power-on. After the wiper is set at the desired position,

the resistance can be permanently set by programming the T bit

high along with the proper coding (see Table 7 and Table 8) and

one time V_{DD_OTP}. Note that fuse link technology of the

A

W

AD517x family of digital pots requires V_{DD_OTP}between 5.25 V

and 5.5 V to blow the fuses to achieve a given nonvolatile

setting. On the other hand, V_DDcan be 2.7 V to 5.5 V during

operation. As a result, system supply that is lower than 5.25 V

requires external supply for one-time programming. Note that

the user is allowed only one attempt in blowing the fuses. If the

user fails to blow the fuses at the first attempt, the fuses’

structures may have changed such that they may never be

blown regardless of the energy applied at subsequent events. For

details, see the Power Supply Considerations section.

B

Figure 31. Rheostat Mode Configuration

Assuming a 10 kΩ part is used, the wiper’s first connection

starts at the B terminal for data 0x00. Because there is a 50 Ω

wiper contact resistance, such a connection yields a minimum

of 100 Ω (2 × 50 Ω) resistance between Terminal W and

Terminal B. The second connection is the first tap point, which

corresponds to 139 Ω (R_WB= R_AB/256 + 2 × R_W= 39 Ω + 2 × 50 Ω)

for data 0x01. The third connection is the next tap point, repre-

senting 178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on.

Each LSB data value increase moves the wiper up the resistor

ladder until the last tap point is reached at 10,100 Ω (R_AB+ 2 × R_W).

The device control circuit has two validation bits, E1 and E0,

that can be read back to check the programming status (see

Table 7). Users should always read back the validation bits to

ensure that the fuses are properly blown. After the fuses have

been blown, all fuse latches are enabled upon subsequent

power-on; therefore, the output corresponds to the stored

setting. Figure 30 shows a detailed functional block diagram.

Rev. A | Page 12 of 24

AD5170

For R_AB= 10 kΩ and the B terminal open-circuited, the

following output resistance, R_WA,is set for the RDAC latch

codes, as shown in Table 6.

A

SD BIT

R

S

Table 6. Codes and Corresponding R_WAResistance

R

D7

D6

D5

D4

D3

D2

D1

D0

S

D (Dec.)

R_WA(Ω)

Output State

Full Scale

Midscale

1 LSB

277

128

1

139

S

7,±6±

9,961

1±,±6±

W

±

Zero Scale

Typical device-to-device matching is process lot dependent and

may vary by up to 30%. Since the resistance element is pro-

cessed using thin film technology, the change in R_ABwith

temperature has a very low 35 ppm/°C temperature coefficient.

RDAC

R

S

LATCH

AND

DECODER

B

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

Figure 32. AD5170 Equivalent RDAC Circuit

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

A-to-B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A–B, W–A, and W–B can be at either

polarity.

The general equation that determines the digitally programmed

output resistance between Terminal W and Terminal B is

D

R

WB(D) =

×RAB +2×R

W

(1)

128

where D is the decimal equivalent of the binary code loaded in

the 8-bit RDAC register, R_ABis the end-to-end resistance, and

V

I

A

B

R

_Wis the wiper resistance contributed by the on resistance of

W

V

O

the internal switch.

In summary, if R_AB= 10 kΩ and the A terminal is open-

circuited, the output resistance R_WBis set for the RDAC latch

codes, as shown in Table 5.

Figure 33. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal AB divided by the 256 positions

of the potentiometer divider. The general equation defining the

output voltage at V_Wwith respect to ground for any valid input

voltage applied to Terminal A and Terminal B is

Table 5. Codes and Corresponding R_WBResistance

D (Dec.)

R_WB(Ω)

9,961

7,±6±

139

Output State

277

128

1

Full Scale (R_AB– 1 LSB + R_W)

Midscale

1 LSB

±

1±±

Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of

100 Ω is present. Care should be taken to limit the current flow

between Terminal W and Terminal B in this state to a maximum

pulse current of no more than 20 mA. Otherwise, degradation

or possible destruction of the internal switch contact can occur.

D

256 − D

256

V_W(D) =

V_A+

V_B

(3)

256

For a more accurate calculation, which includes the effect of

wiper resistance, V_Wcan be found as

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper, Terminal W, and Terminal A also

produces a digitally controlled complementary resistance, R_WA

When these terminals are used, the B terminal can be opened.

Setting the resistance value for R_WAstarts at a maximum value

of resistance and decreases as the data loaded in the latch

increases in value. The general equation for this operation is

R

_WB(D)

R_AB

R

_WA(D)

R_AB

.

V_W(D) =

V_A+

V_B

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors, R_WAand R_WB, and not the ab-

solute values. Thus, the temperature drift reduces to 15 ppm/°C.

256 – D

128

R

^WA(D) =

×RAB + 2×R

W

(2)

Rev. A | Page 13 of 24

AD5170

fuse programming supply (either an on-board regulator or

rack-mount power supply) must be rated at 5.25 V to 5.5 V and

able to provide a 100 mA current for 400 ms for successful one-

time programming. Once fuse programming is completed, the

V_{DD_OTP}supply must be removed to allow normal operation at

2.7 V to 5.5 V and the device will consume current in µA range.

Figure 37 shows the simplest implementation of a dual supply

requirement by using a jumper. This approach saves one voltage

supply, but draws additional current and requires manual

configuration.

ESD PROTECTION

All digital inputs—SDA, SCL, AD0, and AD1—are protected

with a series input resistor and parallel Zener ESD structures, as

shown in Figure 34 and Figure 35.

340Ω

LOGIC

GND

Figure 34. ESD Protection of Digital Pins

CONNECT J1 HERE

FOR OTP

5.5V

A, B, W

R1 50kΩ

V

DD

C1

10µF

C2

1nF

GND

AD5170

R2 250kΩ

CONNECT J1 HERE

AFTER OTP

Figure 35. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5170 V_DDto GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer opera-

tion. Supply signals present on Terminal A, Terminal B, and

Terminal W that exceed V_DDor GND will be clamped by the

internal forward-biased diodes (see Figure 36).

Figure 37. Power Supply Requirement

An alternate approach in 3.5 V to 5.25 V systems adds a signal

diode between the system supply and the OTP supply for

isolation, as shown in Figure 38.

V

DD

APPLY FOR OTP ONLY

5.5V

A

D1

V

3.5V–5.25V

DD

W

B

C1

1µF

C2

1nF

AD5170

GND

Figure 36. Maximum Terminal Voltages Set by V_DDand GND

POWER-UP SEQUENCE

Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating

Supply. The V_{DD_OTP}must be removed once OTP is completed.

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 36), it is

important to power V_DD/GND before applying any voltage to

Terminal A, Terminal B, and Terminal W. Otherwise, the diode

will be forward biased such that V_DDis powered unintentionally

and may affect the rest of the user’s circuit. The ideal power-up

sequence is GND, V_DD, the digital inputs, and then V_A/V_B/V_W.

The relative order of powering V_A, V_B, V_W, and the digital

inputs is not important as long as they are powered after

V_DD/GND.

APPLY FOR OTP ONLY

5.5V

R1

10kΩ

V

2.7V

DD

C1

10µF

C2

1nF

P1

P2

AD5170

P1=P2=FDV302P, NDS0610

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time pro-

gramming and normal operating voltage supplies share the

same V_DDterminal of the AD5170. The AD5170 employs fuse

link technology that requires 5.25 V to 5.5 V for blowing the

internal fuses to achieve a given setting, but normal V_DDcan be

anywhere between 2.7 V and 5.5 V after the fuse programming

process. As a result, dual voltage supplies and isolation are

needed if system V_DDis lower than the required V_{DD_OTP}. The

Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.

The V_{DD_OTP}supply must be removed once OTP is completed.

For users who operate their systems at 2.7 V, use of the

bidirectional low threshold P-Ch MOSFETs is recommended

for the supply’s isolation. As shown in Figure 39, this assumes

Rev. A | Page 14 of 24

AD5170

the 2.7 V system voltage is applied first, and the P1 and P2 gates

are pulled to ground, thus turning on P1 and subsequently P2.

As a result, V_DDof the AD5170 approaches 2.7 V. When the

AD5170 setting is found, the factory tester applies the V_{DD_OTP}

to both the V_DDand the MOSFETs gates turning off P1 and P2.

The OTP command is executed at this time to program the

AD5170 while the 2.7 V source is protected. Once the fuse

programming is completed, the tester withdraws the V_{DD_OTP}

and the setting for AD5170 is permanently fixed.

LAYOUT CONSIDERATIONS

It is good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Note that the digital ground should also be joined remotely to

the analog ground at one point to minimize the ground bounce.

AD5170 achieves the OTP function through blowing internal

fuses. Users should always apply the 5.25 V to 5.5 V one-time

program voltage requirement at the first fuse programming

attempt. Failure to comply with this requirement may lead to a

change in the fuse structures, rendering programming

inoperable.

V

DD

+

C1

10µF

C2

1nF

AD5170

Poor PCB layout introduces parasitics that may affect the fuse

programming. Therefore, it is recommended to add a 10 µF

tantalum capacitor in parallel with a 1 nF ceramic capacitor as

close as possible to the V_DDpin. The type and value chosen for

both capacitors are important. This combination of capacitor

values provides both a fast response and larger supply current

handling with minimum supply droop during transients. As a

result, these capacitors increase the OTP programming success

by not inhibiting the proper energy needed to blow the internal

fuses. Additionally, C1minimizes transient disturbance and low

frequency ripple while C2 reduces high frequency noise during

normal operation.

GND

Figure 40. Power Supply Bypassing

Rev. A | Page 17 of 24

AD5170

EVALUATION SOFTWARE/HARDWARE

Figure 41. AD5170 Computer Software Interface

There are two ways of controlling the AD5170. Users can either

program the devices with computer software or external I²C

controllers.

The AD5170 starts at midscale after power-up prior to OTP

programming. To increment or decrement the resistance, the

user may simply move the scrollbars on the left. To write any

specific value, the user should use the bit pattern in the upper

screen and press the Run button. The format of writing data to

the device is shown in Table 7. Once the desired setting is

found, the user presses the Program Permanent button to blow

the internal fuse links.

SOFTWARE PROGRAMMING

Due to the advantages of the one-time programmable feature,

users may consider programming the device in the factory

before shipping the final product to end-users. ADI offers

device programming software that can be implemented in the

factory on PCs running Windows® 95 or later. As a result,

external controllers are not required, which significantly

reduces development time. The program is an executable file

that does not require knowledge of any programming languages

or programming skills. It is easy to set up and to use. Figure 41

shows the software interface. The software can be downloaded

from www.analog.com.

To read the validation bits and data from the device, the user

simply presses the Read button. The format of the read bits is

shown in Table 8.

To apply the device programming software in the factory, users

must modify a parallel port cable and configure Pin 2, Pin 3,

Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND,

respectively, for the control signals (Figure 42). Users should

also lay out the PCB of the AD5170 with SCL and SDA pads, as

shown in Figure 43, such that pogo pins can be inserted for

factory programming.

Rev. A | Page 16 of 24

AD5170

13

25

12

24

11

23

AD5170

B

A

W

NC

AD0

GND

VDD

AD1

SDA

SCL

10

22

9

21

8

20

7

Figure 43. Recommended AD5170 PCB Layout. The SCL and SDA pads allow

pogo pins to be inserted so that signals can be communicated through the

parallel port for programming (Figure 42).

19

6

18

5

R3

100Ω

R2

17

4

SCL

SDA

16

3

READ

100Ω

15

2

R1

WRITE

14

100Ω

1

Figure 42. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,

Pin 15 = SDA_read, and Pin 25 = DGND.

Rev. A | Page 1ꢀ of 24

AD5170

I²C INTERFACE

Table 7. Write Mode

W

R

S

±

1

±

1

AD1 AD±

A

2T SD

T

±

OW

X

A

Dꢀ D6 D7 D4 D3 D2 D1 D±

Data Byte

A

P

Slave Address Byte

Instruction Byte

Table 8. Read Mode

S

±

1

±

1

AD1 AD±

Dꢀ D6 D7 D4 D3 D2 D1 D±

Instruction Byte

E1 E±

X

Slave Address Byte

Data Byte

S = Start Condition.

P = Stop Condition.

A = Acknowledge.

T = OTP Programming Bit. Logic 1 permanently programs the

wiper.

OW = Overwrite the fuse setting and program the digital

potentiometer to a different setting. Note that upon power-up,

the digital potentiometer presets to either midscale or fuse

setting depending on whether the fuse link has been blown.

AD0, AD1 = Package Pin Programmable Address Bits.

X = Don’t Care.

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.

E1, E0 = OTP Validation Bits.

W

= Write.

R = Read.

0, 0 = Ready to Program.

2T = Second fuse link array for two-time programming. Logic 0

corresponds to first trim. Logic 1 corresponds to second trim.

Note that blowing trim #2 before trim #1 effectively disables

trim #1 and in turn only allows one-time programming.

1, 0 = Fatal Error. Some fuses not blown. Do not retry.

Discard this unit.

1, 1 = Programmed Successfully. No further adjustments are

possible.

SD = Shutdown connects wiper to B terminal and open circuits

the A terminal. It does not change the contents of the wiper

register.

Rev. A | Page 18 of 24

AD5170

t₂

t₈

t₆

t₉

SCL

SDA

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

t₁

P

S

P

Figure 44. I²C Interface Detailed Timing Diagram

1

9

1

9

1

9

SCL

SDA

0

1

0

1

AD1 AD0 R/W

A0 SD

T

0

OW

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5170

ACK BY

AD5170

ACK BY

AD5170

START BY

MASTER

STOP BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

Figure 45. Writing to the RDAC Register

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0

X

NO ACK

BY MASTER

ACK BY

AD5170

ACK BY

MASTER

START BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

Figure 46. Reading Data from the RDAC Register

Rev. A | Page 19 of 24

AD5170

I²C COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I²C serial bus protocol operates as follows:

The fifth MSB, OW, is an overwrite bit. When raised to a

logic high, OW allows the RDAC setting to be changed

even after the internal fuses have been blown. However,

once OW is returned to a logic zero, the position of the

RDAC returns to the setting prior to overwrite. Because

OW is not static, if the device is powered off and on, the

RDAC presets to midscale or to the setting at which the

fuses were blown, depending on whether the fuses have

been permanently set.

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 45). The

following byte is the slave address byte, which consists of

the slave address followed by an R/ bit (this bit deter-

W

mines whether data is read from, or written to, the slave

device). AD0 and AD1 are configurable address bits which

allow up to four devices on one bus (see Table 7).

The remainder of the bits in the instruction byte are Don’t

Care bits (see Figure 45).

The slave address corresponding to the transmitted address

bits responds by pulling the SDA line low during the ninth

clock pulse (this is termed the Acknowledge bit). At this

stage, all other devices on the bus remain idle while the

selected device waits for data to be written to, or read from,

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an Acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see

Figure 44).

its serial register. If the R/ bit is high, the master will read

W

from the slave device. If the R/ bit is low, the master will

W

write to the slave device.

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB), 2T, of the instruction byte is the

second trim enable bit. A logic low selects the first array of

fuses, and a logic high selects the second array. This means

that after blowing the fuses with trim#1, the user still has

another chance to blow them again with trim#2. Note that

using trim#2 before trim#1 effectively disables trim#1 and,

in turn, only allows one-time programming.

3. In the read mode, the data byte follows immediately after

the acknowledgment of the slave address byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (a slight difference from the write mode, with eight

data bits followed by an Acknowledge bit). Similarly, the

transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of

SCL (see Figure 46).

The second MSB, SD, is a shutdown bit. A logic high causes

an open circuit at Terminal A while shorting the wiper to

Terminal B. This operation yields almost 0 Ω in rheostat

mode or 0 V in potentiometer mode. It is important to

note that the shutdown operation does not disturb the

contents of the register. When brought out of shutdown,

the previous setting is applied to the RDAC. Also, during

shutdown, new settings can be programmed. When the

part is returned from shutdown, the corresponding VR

setting is applied to the RDAC.

Following the data byte, the validation byte contains two

validation bits, E0 and E1. These bits signify the status of

the one-time programming (see Figure 46).

4. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10^thclock pulse to establish a STOP

condition (see Figure 45). In read mode, the master issues a

No Acknowledge for the 9^thclock pulse (i.e., the SDA line

remains high). The master then brings the SDA line low

before the 10^thclock pulse, which goes high to establish a

STOP condition (see Figure 46).

The third MSB, T, is the OTP (one-time programmable)

programming bit. A logic high blows the poly fuses and

programs the resistor setting permanently. For example, if

the user wanted to blow the first array of fuses, the

instruction byte would be 00100XXX. To blow the second

array of fuses, the instruction byte would be 10100XXX. A

logic low of the T bit simply allows the device to act as a

typical volatile digital potentiometer.

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing and instructing

the part only once. For example, after the RDAC has acknowledged

its slave address and instruction bytes in the write mode, the

RDAC output updates on each successive byte. If different

instructions are needed, the write/read mode has to start again

with a new slave address, instruction, and data byte. Similarly, a

repeated read function of the RDAC is also allowed.

The fourth MSB must always be at Logic 0.

Rev. A | Page 2± of 24

AD5170

5V

Table 9. Validation Status

E1 E0 Status

R

P

SDA

SCL

±

1

±

Ready for Programming.

Fatal Error. Some fuses not blown. Do not retry.

Discard this unit.

MASTER

5V

1

Successful. No further programming is possible.

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

Multiple Devices on One Bus

AD0

Figure 47 shows four AD5170s on the same serial bus. Each has

a different slave address because the states of their AD0 and

AD1 pins are different. This allows each device on the bus to be

written to, or read from, independently. The master device

output bus line drivers are open-drain pull-downs in a fully I²C

compatible interface.

AD5170

Figure 47. Multiple AD5170s on One I²C Bus

Rev. A | Page 21 of 24

AD5170

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

10

W

B

9

NC

A

8

AD0

GND

AD5170

TOP VIEW

AD1

SDA

SCL

7

6

V

DD

Figure 48. Pin Configuration

Table 10. Pin Function Descriptions

Mnemonic

Description

B Terminal.

A Terminal.

1

2

B

A

3

4

7

6

ꢀ

8

9

1±

AD±

GND

V_DD

SCL

SDA

AD1

NC

W

Programmable Address Bit ± for Multiple Package Decoding.

Digital Ground.

Positive Power Supply.

Serial Clock Input. Positive Edge Triggered.

Serial Data Input/Output.

Programmable Address Bit 1 for Multiple Package Decoding.

No Connect.

W Terminal.

Rev. A | Page 22 of 24

AD5170

OUTLINE DIMENSIONS

3.00 BSC

10

6

4.90 BSC

3.00 BSC

PIN 1

1

5

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.00

0.27

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 49. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

R_AB(kΩ)

Temperature

Package Description

MSOP-1±

Package Option

RM-1±

Branding

AD71ꢀ±BRM2.7

AD71ꢀ±BRM2.7-RLꢀ

AD71ꢀ±BRM1±

AD71ꢀ±BRM1±-RLꢀ

AD71ꢀ±BRM7±

AD71ꢀ±BRM7±-RLꢀ

AD71ꢀ±BRM1±±

AD71ꢀ±BRM1±±-RLꢀ

AD71ꢀ±EVAL¹

2.7

1±

7±

1±±

–4±°C to +127°C

D±Y

D±Z

D±W

D±X

Evaluation Board

¹The evaluation board is shipped with the 1± kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

Rev. A | Page 23 of 24

AD5170

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

D04104–0–11/04(A)

Rev. A | Page 24 of 24


型号：	AD5170BRM10
厂家：	ADI
描述：	256-Position Two-Time Programmable I2C Digital Potentiometer 256位两次可编程I2C数字电位计转换器数字电位计电阻器光电二极管
文件：	总24页 (文件大小：1077K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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