AD260AND-4 [ADI]
High Speed, Logic Isolator with Power Transformer; 高速，电力变压器逻辑隔离
| 型号： | AD260AND-4 |
| 厂家： | 
ADI |
| 描述： | High Speed, Logic Isolator with Power Transformer |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Logic Isolator
with Power Transformer
a
AD260
FEATURES
FUNCTIONAL BLOCK DIAGRAM
IsoLogic™ Circuit Architecture
Isolation Test Voltage: To 3.5 kV rms
AD260
LATCH
TRISTATE
TRISTATE
TRISTATE
D
1
S0
S1
S2
F0 18
LINE 0
LINE 1
LINE 2
LINE 3
LINE 4
Five Isolated Logic Lines: Available in Six I/O Configurations
Logic Signal Bandwidth: 20 MHz (Min), 40 mbps (NRZ)
Isolated Power Transformer: 37 V p-p, 1.5 W Max
CMV Transient Immunity: 10 kV/s Min
Waveform Edge Transmission Symmetry: ؎1 ns
Field and System Output Enable/Three-State Functions
Performance Rated Over –25؇C to +85؇C
UL1950, IEC950, EN60950 Certification, Pending
E
LATCH
D
2
3
19
20
21
F1
F2
F3
E
LATCH
D
E
LATCH
D
4
S3
S4
TRISTATE
TRISTATE
E
APPLICATIONS
LATCH
D
22
17
F4
5
6
PLC/DCS Analog Input and Output Cards
Communications Bus Isolation
General Data Acquisition Applications
IGBT Motor Drive Controls
E
ENABLE
ENABLE
+5Vdc
FLD
SYS
+5Vdc
+5Vdc
High Speed Digital I/O Ports
+5Vdc
16
15
7
8
FLD
SYS
5Vdc RTN
5Vdc RTN
5V RTN
5V RTN
FLD
SYS
GENERAL DESCRIPTION
17V p-p OUT
CT OUT
DRIVE
+5V
The AD260 is designed using Analog Devices new IsoLogic
circuit architecture to isolate five digital control signals to/
from a microcontroller and its related field I/O components. Six
models allow all I/O combinations from five input lines to five
output lines, including combinations in between. Every AD260
effectively replaces up to five opto-isolators while also providing
the 1.5 W transformer for a 3.5 kV isolated dc-dc power supply
circuit.
PWRA
PWRCT
PWRB
14
13
12
9
DRVA
DRVCT
DRVB
FLD
10
11
FLD
DRIVE
17V p-p OUT
FLD
FIELD
SYSTEM
the input. This guarantees the output is always valid 10 µs after
a fault condition or after the power-up reset interval.
The AD260 also has an integral center tap transformer for gen-
erating isolated power. Typically driven by a 5 V push-pull drive
at the primary, it will generate a 37 V p-p output capable of
supplying up to 1.5 W. This can then be regulated to the de-
sired voltage, including ±5 V dc for circuit components and
24 V for a 20 mA loop supply when needed.
Each line of the AD260 has a bandwidth of 20 MHz (min) with
a propagation delay of only 14 ns, which allows for extremely
fast data transmission. Output waveform symmetry is maintained
to within ±1 ns of the input so the AD260 can be used to accu-
rately isolate time-based PWM signals.
All field or system output pins of the AD260 can be set to a high
resistance three-state level by use of the two enable pins. A field
output three-stated offers a convenient method of presetting
logic levels at power-up by use of pull-up/down resistors. Sys-
tem side outputs being three-stated allows for easy multiplexing
of multiple AD260s.
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The
AD260 is available in six pin-compatible versions of I/O con-
figurations to meet a wide variety of requirements.
Wide Bandwidth with Minimal Edge Error: The AD260 with
IsoLogic affords extremely fast isolation of logic signals due to its
20 MHz bandwidth and 14 ns propagation delay. It maintains a
waveform input-to-output edge transition error of typically less
than ±1 ns (total) for positive vs. negative transition.
The isolation barrier of the AD260 B Grade is 100% tested at
3.5 kV rms (system to field). The barrier design also provides
excellent common-mode transient immunity from 10 kV/µs
common-mode voltage excursions of field side terminals relative
to the system side, with no false output triggering on either side.
3.5 kV rms Test Voltage Isolation Rating: The AD260
B Grade is rated to operate at 1.25 kV rms and is 100% pro-
duction tested at 3.5 kV rms, using a standard ADI test method.
Each output is updated within nanoseconds by input logic tran-
sitions, the AD260 also has a continuous output update feature
that automatically updates each output based on the dc level of
High Transient Immunity: The AD260 rejects common-
mode transients slewing at up to 10 kV/µs without false trigger-
ing or damage to the device.
IsoLogic is a trademark of Analog Devices, Inc.
(Continued on page 6)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(Typical at T = +25؇C, +5 V dc , +5 V dc , t = 50 ns max unless otherwise noted)
AD260–SPECIFICATIONS
A
SYS
FLD RR
Parameter
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Threshold Voltage
Positive Transition (VT+
)
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
2.0
3.0
0.9
1.2
0.4
0.5
2.7
3.2
1.8
2.2
0.9
1.0
5
3.15
4.2
2.2
3.0
1.4
1.5
V
V
V
V
V
V
pF
µA
Negative Transition (VT–
)
Hysteresis Voltage (VH)
Input Capacitance (CIN
Input Bias Current (IIN
)
)
Per Input
0.5
OUTPUT CHARACTERISTICS
Output Voltage1
High Level (VOH
)
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
4.4
3.7
V
V
V
V
Low Level (VOL
)
0.1
0.4
Output Three-State Leakage Current
ENABLESYS/FLD @ Logic Low/High Level Respectively
0.5
µA
DYNAMIC RESPONSE 1 (Refer to Figure 2)
Max Logic Signal Frequency (fMIN
Waveform Edge Symmetry Error (tERROR
Logic Edge Propagation Delay (tPHL, tPLH
Minimum Pulsewidth (tPWMIN
)
50% Duty Cycle, +5 V dcSYS = 5 V
tPHL vs. tPLH
20
25
MHz
ns
ns
)
±1
14
)
25
)
ns
Max Output Update Delay on Fault or After
Power-Up Reset Interval (≈ 30 µs)2
12
µs
ISOLATION BARRIER RATING3
Operating Isolation Voltage (VCMV
)
AD260A
AD260B
AD260A
AD260B
375
1250
V rms
V rms
V rms
V rms
V/µs
4
Isolation Rating Test Voltage (VCMV TEST
)
1750
3500
10,000
Transient Immunity (VTRANSIENT
Isolation Mode Capacitance (CISO
Capacitive Leakage Current (ILEAD
)
)
)
Total Capacitance, All Lines and Transformer
240 V rms @ 60 Hz
14
18
2
pF
µA rms
POWER TRANSFORMER
Primary Winding
Bifilar Wound, Center-Tapped
Each Half
Each Half
Inductance (L )
1
mH
P
Number of Turns (N )
P
26
0.6
Turns
Ω
Resistance
Each Half
Max Volt-Seconds (E × t)
Recommended Operating Frequency
Absolute Min Operating Frequency
Secondary Winding
Each Half
27
300
V × µs
kHz
kHz
–25°C to +85°C, Push-Pull Drive
–25°C to +85°C, Push-Pull Drive
Bifilar Wound, Center-Tapped
Each Half
150
75
200
Number of Turns (N )
48
2.3
Turns
Ω
S
Resistance
Each Half
Insulation Withstand (VCMV TEST
Capacitance
Recommended Max Power
)
Primary to Secondary
Primary to Secondary
Rated Performance
3,500
1.0
V rms
pF
W
5
1.5
POWER SUPPLY
Supply Voltage (+5 V dcSYS and +5 V dcFLD
)
Rated Performance
Operating
Effective, per Input, Either Side
Effective per Output, Either Side—No Load
Each, +5 V dcSYS & FLD
4.5
4.0
5.5
5.75
V dc
V dc
pF
pF
mA
mA
Power Dissipation Capacitance
8
28
4
Quiescent Supply Current
Supply Current
All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD
)
18
TEMPERATURE RANGE
Rated Performance (TA)5
–25
–40
+85
+85
°C
°C
Storage (TSTG
)
NOTES
1For best performance, bypass +5 V dc supplies to com. at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF.
2As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point where
+5 V dcSYS & FLD passes above 3.3 V.
3“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice
the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but
nondestructive).
4Partial Discharge at 80 pC THLD.
5Supply Current will increase slightly, but otherwise the unit will function within specification to –40°C.
Specifications are subject to change without notice.
REV. 0
–2–
AD260
ABSOLUTE MAXIMUM RATINGS*
Parameter
Conditions
Min Typ Max
Units
Supply Voltage (+5 V dcSYS & FLD
DC Input Voltage (VIN MAX
DC Output Voltage (VOUT MAX
Clamp Diode Input Current (IIK
Clamp Diode Output Current (IOK
Output DC Current, per Pin (IOUT
DC Current, VCC or GND (ICC or IGND
Storage Temperature (TSTG
Lead Temperature (Soldering, 10 sec)
Electrostatic Protection (VESD
)
–0.5
–0.5
–0.5
–25
–25
–25
–50
–40
+6.0
+0.5
+0.5
+25
+25
+25
+50
+85
V
V
V
mA
mA
mA
mA
°C
)
Referred to +5 V dcSYS & FLD and 5 V RTNSYS & FLD Respectively
Referred to +5 V RTNSYS & FLD and 5 V dcSYS & FLD Respectively
For VI < –0.5 V or VI > 5 V RTNSYS & FLD +0.5 V
)
)
)
)
For VO < –0.5 V or VO > 5 V RTNSYS & FLD +0.5 V
)
)
+300 °C
)
Per MIL-STD-883, Method 3015
4.5
5
kV
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may effect device reliability.
I/O CONFIGURATIONS AVAILABLE
PIN CONFIGURATION
The AD260 is available in several configurations. The choice of
model is determined by the desired number of input vs. output
lines. All models have identical footprints with the power and
enable pins always being in the same locations.
1
S0
S1
S2
S3
2
3
4
5
S4
PIN FUNCTION DESCRIPTIONS
6
SYSTEM
ENABLE
SYS
7
+5Vdc
SYS
8
5V RTN
DRVA
SYS
Pin
Mnemonic
Function
9
10
11
DRVCT
DRVB
1–5*
6
7
S0 Through S4 Digital Xmt or Rcv from F0 Through F4
ENABLESYS
+5 V dcSYS
5 V RTNSYS
System Output Enable/Three-State
System Power Supply (+5 V dc Input)
System Power Supply Common
Not Present On Unit
BOTTOM VIEW
8
PWRB
PWRCT
PWRA
5V RTN
+5Vdc
12
13
14
15
16
FLD
FLD
FLD
FLD
FLD
9–14
15
16
17
5 V RTNFLD
+5 V dcFLD
ENABLEFLD
Field Power Supply Common
Field Power Supply (+5 V Input)
Field Output Enable/Three-State
ENABLE
17
18
19
20
21
22
FIELD
FLD
F0
18–22* F0 Through F4 Digital Xmt or Rcv from S0 Through S4
F1
F2
F3
F4
*Function of pin determined by model. Refer to Table I.
Caution: Use care in handling unit as contaminants on the bot-
tom side of the unit or the circuit card to which it is mounted will
lead to reduced breakdown voltage across the isolation barrier.
ORDERING GUIDE
Model Number
Description
Isolation Test Voltage
Package Description
Package Option
AD260AND-0
AD260AND-1
AD260AND-2
AD260AND-3
AD260AND-4
AD260AND-5
0 Inputs, 5 Outputs
1 Input, 4 Outputs
2 Inputs, 3 Outputs
3 Inputs, 2 Outputs
4 Inputs, 1 Output
5 Inputs, 0 Outputs
1.75 kV rms
1.75 kV rms
1.75 kV rms
1.75 kV rms
1.75 kV rms
1.75 kV rms
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
ND-22
ND-22
ND-22
ND-22
ND-22
ND-22
AD260BND-0
AD260BND-1
AD260BND-2
AD260BND-3
AD260BND-4
AD260BND-5
0 Inputs, 5 Outputs
1 Input, 4 Outputs
2 Inputs, 3 Outputs
3 Inputs, 2 Outputs
4 Inputs, 1 Output
5 Inputs, 0 Outputs
3.5 kV rms
3.5 kV rms
3.5 kV rms
3.5 kV rms
3.5 kV rms
3.5 kV rms
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
ND-22
ND-22
ND-22
ND-22
ND-22
ND-22
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD260 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD260
PIN CONFIGURATIONS
AD260BND-2
AD260BND-0
AD260-2
AD260-0
LATCH
LATCH
TRISTA
T
D
TT
D
1
S0
S1
S2
1
S0
S1
S2
F0 18
R
LINE 0 – OUT
LINE 1 – OUT
LINE 2 – OUT
LINE 3 – IN
F0 18
LINE 0 – OUT
LINE 1 – OUT
LINE 2 – OUT
LINE 3 – OUT
LINE 4 – OUT
IS
T
A
TE
T
E
E
E
LATCH
LATCH
TR
IS
TA
TE
D
T
D
2
3
19
20
21
2
3
F1
19
20
21
R
IS
T
F1
F2
F3
A
T
E
E
E
LATCH
LATCH
D
TR
ISTATE
D
T
T
T
F2
F3
F4
R
IS
T
A
T
E
E
E
LATCH
LATCH
D
4
D
S3
S4
R
4
S3
S4
IS
T
A
ISTATE
TR
T
E
E
E
LATCH
LATCH
D
22
17
D
22
17
5
6
7
F4
R
LINE 4 – IN
TE
TRISTA
5
6
7
IS
T
A
T
E
E
E
ENABLE
+5Vdc
ENABLE
+5Vdc
ENABLE
ENABLE
+5Vdc
FLD
FLD
SYS
FLD
SYS
+5Vdc
+5Vdc
+5Vdc
+5Vdc
16
15
+5Vdc
16
15
SYS
FLD
SYS
5Vdc RTN
5Vdc RTN
5Vdc RTN
5Vdc RTN
5V RTN
PWRA
8
9
5V RTN
DRVA
5V RTN
8
9
5V RTN
DRVA
FLD
SYS
FLD
SYS
17V p-p OUT
CT OUT
DRIVE
+5V
DRIVE
+5V
17V p-p OUT
CT OUT
14
13
12
PWRA
PWRCT
PWRB
FLD
14
13
12
FLD
FLD
FLD
PWRCT
10 DRVCT
FLD
FLD
10 DRVCT
17V p-p OUT
DRIVE
17V p-p OUT
DRIVE
11
DRVB
PWRB
11
DRVB
FIELD
SYSTEM
FIELD
SYSTEM
AD260BND-3
AD260BND-1
AD260-3
AD260-1
LATCH
LATCH
TRISTATE
D
1
2
S0
S1
F0 18
D
1
2
3
LINE 0 – OUT
LINE 1 – OUT
LINE 2 – IN
S0
S1
S2
F0 18
LINE 0 – OUT
LINE 1 – OUT
LINE 2 – OUT
LINE 3 – OUT
LINE 4 – IN
E
E
LATCH
LATCH
TRISTATE
D
19
20
21
F1
F2
F3
D
19
F1
E
E
LATCH
LATCH
D
D
3
4
5
S2
S3
S4
20
21
F2
F3
TRISTATE
E
E
LATCH
LATCH
D
LINE 3 – IN
LINE 4 – IN
D
4
S3
S4
TRISTATE
TRISTATE
E
E
LATCH
D
LATCH
F4 22
F4 22
D
5
6
E
E
ENABLE
+5Vdc
6
7
17
ENABLE
+5Vdc
FLD
ENABLE
+5Vdc
SYS
ENABLE
+5Vdc
17
FLD
SYS
+5Vdc
+5Vdc
+5Vdc
+5Vdc
5Vdc RTN
DRIVE
16
15
FLD
SYS
16
15
7
8
FLD
SYS
5Vdc RTN
5Vdc RTN
5Vdc RTN
5V RTN
8
9
5V RTN
DRVA
FLD
SYS
5V RTN
PWRA
5V RTN
FLD
SYS
DRIVE
+5V
17V p-p OUT
CT OUT
17V p-p OUT
CT OUT
PWRA
PWRCT
PWRB
14
13
12
FLD
14
13
12
9
DRVA
FLD
+5V
10 DRVCT
FLD
PWRCT
10
DRVCT
FLD
FLD
17V p-p OUT
DRIVE
17V p-p OUT
DRIVE
11
DRVB
11 DRVB
FLD
PWRB
FIELD
SYSTEM
FIELD
SYSTEM
REV. 0
–4–
AD260
PIN CONFIGURATIONS
AD260BND-4
AD260BND-5
AD260-5
AD260-4
LATCH
LATCH
T
D
1
D
S0
F0 18
R
1
LINE 0 – IN
LINE 1 – IN
LINE 2 – IN
LINE 3 – IN
LINE 4 – IN
S0
LINE 0 – OUT
LINE 1 – IN
LINE 2 – IN
LINE 3 – IN
LINE 4 – IN
18
19
20
F0
F1
F2
F3
IS
T
A
T
E
TRISTATE
TRISTATE
TRISTATE
TRISTATE
TRISTATE
E
E
LATCH
LATCH
19
D
S1
S2
S3
S4
F1
D
E
2
3
4
2
3
4
S1
S2
S3
S4
T
A
T
IS
R
T
E
E
LATCH
LATCH
D
20
E
E
E
D
F2
T
A
T
IS
R
T
E
E
LATCH
LATCH
21
D
F3
21
D
T
A
T
IS
R
T
E
E
LATCH
LATCH
22
17
D
F4
5
6
22
17
D
F4
5
6
T
A
T
IS
R
T
E
E
ENABLE
ENABLE
+5Vdc
ENABLE
+5Vdc
ENABLE
+5Vdc
FLD
SYS
FLD
SYS
+5Vdc
+5Vdc
+5Vdc
+5Vdc
+5Vdc
16
15
7
8
16
15
7
8
FLD
SYS
FLD
SYS
5Vdc RTN
5Vdc RTN
5Vdc RTN
5Vdc RTN
5V RTN
5V RTN
5V RTN
PWRA
5V RTN
FLD
SYS
FLD
SYS
DRIVE
+5V
17V p-p OUT
CT OUT
17V p-p OUT
CT OUT
DRIVE
+5V
PWRA
PWRCT
PWRB
14
13
12
9
DRVA
DRVCT
DRVB
14
13
12
9
DRVA
FLD
FLD
FLD
FLD
10
11
PWRCT
10
DRVCT
FLD
FLD
17V p-p OUT
DRIVE
17V p-p OUT
DRIVE
11 DRVB
PWRB
FIELD
SYSTEM
FIELD
SYSTEM
Table I.
Pin
AD260BND-0
AD260BND-1
AD260BND-2
AD260BND-3
AD260BND-4
AD260BND-5
1
2
3
4
5
6
7
8
S0 (Xmt)
S1 (Xmt)
S2 (Xmt)
S3 (Xmt)
S4 (Xmt)
ENABLESYS
+5 V dcSYS
5 V RTNSYS
DRVA
S0 (Xmt)
S1 (Xmt)
S2 (Xmt)
S3 (Xmt)
S4 (Rcv)
*
*
*
S0 (Xmt)
S1 (Xmt)
S2 (Xmt)
S3 (Rcv)
S4 (Rcv)
*
*
*
S0 (Xmt)
S1 (Xmt)
S2 (Rcv)
S3 (Rcv)
S4 (Rcv)
*
*
*
S0 (Xmt)
S1 (Rcv)
S2 (Rcv)
S3 (Rcv)
S4 (Rcv)
*
*
*
S0 (Rcv)
S1 (Rcv)
S2 (Rcv)
S3 (Rcv)
S4 (Rcv)
*
*
*
9
*
*
*
*
*
10
11
12
13
14
15
16
17
18
19
20
21
22
DRVCT
DRVB
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
PWRBFLD
PWRCTFLD
PWRAFLD
5 V RTNFLD
+5 V dcFLD
ENABLEFLD
F0 (Rcv)
F1 (Rcv)
F2 (Rcv)
F3 (Rcv)
F4 (Rcv)
F0 (Rcv)
F1 (Rcv)
F2 (Rcv)
F3 (Rcv)
F4 (Xmt)
F0 (Rcv)
F1 (Rcv)
F2 (Rcv)
F3 (Xmt)
F4 (Xmt)
F0 (Rcv)
F1 (Rcv)
F2 (Xmt)
F3 (Xmt)
F4 (Xmt)
F0 (Rcv)
F1 (Xmt)
F2 (Xmt)
F3 (Xmt)
F4 (Xmt)
F0 (Xmt)
F1 (Xmt)
F2 (Xmt)
F3 (Xmt)
F4 (Xmt)
*Pin function is the same on all models, as shown in the AD260BND-0 column.
REV. 0
–5–
AD260
(Continued from page 1)
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ±1 ns.
Integral Isolated Power: The AD260 includes an integral,
uncommitted and flexible 1 Watt power transformer for devel-
oping isolated field power sources.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 µA
per MHz and each receiver 40 µA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
Field and System Enable Functions: Both the isolated and
nonisolated sides of the AD260 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
The total capacitance spanning the isolation barrier is less than
10 pF.
CE Certifiable: Simply by adding the external bypass capacitors
at the supply pins, the AD260 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
The minimum width of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates all
inputs about every 5 µs and in the absence of logic transitions,
sends appropriate “set-hi” or “set-lo” data across the barrier.
GENERAL ATTRIBUTES
The AD260 provides five HCMOS/ACMOS compatible isolated
logic lines with ≥ 10 kV/µs common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
Recovery time from a fault condition or at power-up is thus
between 5 µs and 10 µs.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD260 part configurations (see Table I).
3.5kV
SCHMITT
TRIGGER
DATA
ISOLATION
DATA
OUTPUT
TRANSMITTER BARRIER RECEIVER BUFFER
OUT
DATA IN
ENABLE
D
G
Q
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
ENABLE
CONTINUOUS
UPDATE CIRCUIT
GATED
TRANSPARENT
LATCH
Figure 1. Simplified Block Diagram
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
PROPAGATION DELAY
POSITIVE GOING
INPUT THRESHOLD
HYSTERESIS
+3V
+2V
NEGATIVE GOING
INPUT
INPUT THRESHOLD
63%
OUTPUT
37%
tff
tPD
tPLH
tPD
tPHL
EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE
SCHMITT
TRIGGER
DELAY LINE
BUFFER
100⍀
12.5ns
tPD
5pF
5pF
OUTPUT
CAPACITANCE
INPUT
CAPACITANCE
trr = tff = 100⍀ x C
TOTAL OUTPUT CAPACITANCE
Х0.5ns – NO LOAD
= 5.5ns INTO 50pF
TOTAL DELAY = (tPLH OR tPHL) = tPD + (trr OR tff) Х13ns (NO LOAD), 18ns (50pF LOAD)
Figure 2. Typical Timing and Delay Models
REV. 0
–6–
AD260
Application Examples
The power transformer is designed to operate between 150 kHz
and 250 kHz and will easily deliver more than 1 W of isolated
power when driven push-pull (5 V) on the system side. Different
transformer tap, rectifier and regulator schemes will provide
combinations of ±5 V, 15 V, 24 V or even 30 V or higher.
The output voltage when driven with a low voltage-drop drive
(@ 5 V push-pull) will be 37 V p-p across the entire secondary.
This will drop to 33 V p-p at 4.5 V drive.
The following is an example of a typical transformer system-side
drive circuit and a field-side regulation circuit suitable for use in
most general applications.
V
FLD
DD
+5V
REG
+5V ISO
96T
CT.
ENABLE FLD
(PWR-UP ENABLE)
+5Vdc
4.7k⍀
9
15 16
V
I
V
COMP
IN
REF
12
11
10
1
LOGIC/SHUTDOWN (H )
I
–5V
REG
INV
–5V ISO
2
NI
LM2524
52T
CT
0.1F
Figure 4.
+
–
3.3F
TANT.
4
5
C +
L
C –
L
13
14
V
@
V(MIN) @
+5Vdc/+4.5Vdc
150mA
3.3k⍀
OUT
6
7
R
T
5V DRIVE
4.5V DRIVE
+
a
a
C
T
470pF
LOAD
GND
8
+8.55
7.62
80mA
COM
+5Vdc
6
1
+5Vdc/+4.5Vdc
150mA
4
+
–
b
b
D
D
S
SHUTDOWN (ON/OFF)
1
D
MAX
253
20mA
52T
CT
+
–
3.3F
TANT.
؎17.63
15.79
20mA
COM
8
3
F
2
S
G
G
2
1
2
7
+5Vdc/+4.5Vdc
150mA
+
–
a
a
Figure 3. System Side Transformer Driver Examples
40mA
40mA
؎8.64
7.72
COM
a
a
+
+
+5Vdc/+4.5Vdc
150mA
b
23.5
7.72
+26.3
+8.64
a
20mA
20mA
COM
b
"a" DIODES IN5818/MBR0530
"b" DIODES IN5819/MBR0540
Figure 5. Field Side Power Supply Rectifier Examples
REV. 0
–7–
AD260
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
22-Lead Plastic DIP
(ND-22)
0.550 (13.97)
MAX
1.500 (38.1) MAX
0.440
(11.18)
MAX
END VIEW
SIDE VIEW
1
12
11
22
0.100
(2.54)
0.050 (1.27)
0.020
؋
0.010 (0.508
؋
0.254) 22 PLACES
0.160 (4.06)
0.140 (3.56)
0.350
(8.89)
0.075 (1.91)
PIN 1
BOTTOM
VIEW
SYSTEM
0.250
(6.35)
0.5* (12.2)
FIELD
0.050
(1.27)
0.350 (8.89)
*CREEPAGE PATH (SUBTRACT APPROXIMATELY
0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD.
THIS SPACING SUPPORTS THE INTRINSICALLY
SAFE RATING OF 750V. WAVE SOLDERING IS
NOT RECOMMENDED.
–8–
REV. 0
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