AD2428 [ADI]
Automotive Audio Bus A2B Transceiver;型号: | AD2428 |
厂家: | ADI |
描述: | Automotive Audio Bus A2B Transceiver |
文件: | 总38页 (文件大小:2020K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Automotive Audio Bus A2B Transceiver
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
A2B BUS FEATURES
A2B TRANSCEIVER FEATURES
Line topology
Single master, multiple slave
Configurable A2B bus master or slave operation
I2C interface
Up to 15 m between nodes and up to 40 m overall cable
length (see Table 9)
Communication over distance
Synchronous data
Multichannel I2S/TDM to I2S/TDM
8-bit to 32-bit multichannel I2S/TDM interface
Programmable I2S/TDM data rate
Up to 32 upstream and 32 downstream channels
PDM interface
Programmable PDM clock rate
Synchronous clock, phase aligned in all nodes
Low latency slave to slave communication
Control and status information I2C to I2C
GPIO and interrupt
Bus power or local power slave nodes
Configurable with SigmaStudio graphical software tool
AEC-Q100 qualified for automotive applications
Up to 4 high dynamic range microphone inputs
Simultaneous reception of I2S data with up to 4 PDM
microphones
Unique ID register for each transceiver
Crossover or straight-through cabling
Programmable settings to optimize EMC performance
APPLICATIONS
Audio communication link
Microphone arrays
Beamforming
Hands free and in car communication
Active and road noise cancellation
Audio/video conferencing systems
IOVDD
DVDD
PLLVDD
VOUT1 VIN
VOUT2
BTRXVDD
2
SCL
SDA
IRQ/IO0
ADR1/IO1
ADR2/IO2
A B
BP
BCM
BN
PLL
VREG1
VREG2
TRX B
(Towards
Last Slave)
2
I C
SWP
SENSE
DIAGNOSTICS
DTX0/IO3
DTX1/IO4
DRX0/IO5
DRX1/IO6
2
AP
ACM
AN
A B
2
I S/TDM
PDM
TRX A
(Towards
Master)
PDMCLK/IO7
BCLK SYNC
VSSN
VSS
ATRXVDD
Figure 1. Functional Block Diagram
A2B and the A2B logo are registered trademarks of Analog Devices, Inc.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
TABLE OF CONTENTS
A2B Bus Features ..................................................... 1
A2B Transceiver Features ........................................... 1
Applications ........................................................... 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
A2B Bus Details .................................................... 4
I2C Interface ........................................................ 5
I2S/TDM Interface ................................................ 5
Pulse Density Modulation (PDM) Interface ................. 6
GPIO Over Distance .............................................. 6
Mailboxes ........................................................... 6
Data Slot Exchange Between Slaves ........................... 6
Clock Sustain State ................................................ 6
Test Circuits and Switching Characteristics ............... 21
Output Drive Currents ......................................... 21
Test Conditions .................................................. 22
Pin Configuration and Function Descriptions ............... 24
Power Analysis ...................................................... 28
Current Flow ...................................................... 28
VREG1 and VREG2 Output Currents ...................... 29
Current at VIN (IVIN) ......................................... 30
Power Dissipation ............................................... 30
Resistance Between Nodes ..................................... 30
Voltage Regulator Current in Master Node or Local
Powered Slave Node .......................................... 31
Power Dissipation of A2B Bus ................................. 31
Power Analysis of Bus Powered System .................... 31
Supply Voltage ................................................... 31
Reducing Power Consumption ............................... 32
Power Estimation Example .................................... 32
Thermal Power ................................................... 35
Designer Reference ................................................. 36
VSENSE and Considerations for Diodes ................... 36
Optional Add On Circuits ..................................... 36
Layout Guidelines ............................................... 37
Outline Dimensions ................................................ 39
Automotive Products .............................................. 40
Ordering Guide ..................................................... 41
Programmable Settings to Optimize EMC
Performance ..................................................... 6
Specifications .......................................................... 8
Operating Conditions ............................................ 8
Electrical Characteristics ......................................... 9
Power Supply Rejection Ratio (PSRR) ...................... 11
Timing Specifications .......................................... 12
Power-Up Sequencing Restrictions ......................... 16
A2B Bus System Specification ................................. 17
PDM Typical Performance Characteristics ................ 18
Absolute Maximum Ratings .................................. 20
Thermal Characteristics ....................................... 20
ESD Caution ...................................................... 21
REVISION HISTORY
1/2020—Rev. A to Rev. B
Updated All Products to Released Status . . . . . . . Throughout
Deleted Product Status Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Automotive Products ................................ 37
Changes to Ordering Guide ....................................... 38
Deleted Pending Products Table.................................. 39
Rev. B
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AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
GENERAL DESCRIPTION
The Automotive Audio Bus (A2B®) provides a multichannel,
I2S/TDM link over distances of up to 15 m between nodes. It
embeds bidirectional synchronous pulse-code modulation
(PCM) data (for example, digital audio), clock, and synchroni-
zation signals onto a single differential wire pair. A2B supports a
direct point to point connection and allows multiple, daisy-
chained nodes at different locations to contribute and/or con-
sume time division multiplexed (TDM) channel content.
The transceiver can connect directly to general-purpose digital
signal processors (DSPs), field-programmable gate arrays
(FPGAs), application specific integrated circuits (ASICs),
microphones, analog-to-digital converters (ADCs), digital-to-
analog converters (DACs), and codecs through a multichannel
I2S/TDM interface. It also provides a pulse density modulation
(PDM) interface for direct connection of up to four PDM digital
microphones.
A2B is a single-master, multiple-slave system where the trans-
ceiver at the host controller is the master. The master generates
clock, synchronization, and framing for all slave nodes. The
master A2B transceiver is programmable over a control port
(I2C) for configuration and read back. An extension of the con-
trol port protocol is embedded in the A2B data stream, which
grants direct access of registers and status information on slave
transceivers as well as I2C to I2C communication over distance.
Finally, the transceiver also supports an A2B bus powering fea-
ture, where the master node supplies voltage and current to the
slave nodes over the same daisy-chained, twisted pair wire cable
as used for the communication link.
Table 1. Product Comparison Guide
Feature
AD2420/
AD2426/
AD2427/
AD2428/
AD2429/
AD2420W
AD2426W
AD2427W
AD2428W
AD2429W
Master capable
No
No
No
Yes
Yes
Number of slaves discoverable1
Functional TRX blocks
I2S/TDM support
N/A
N/A
N/A
Up to 10
A + B
Yes
Up to 2
B only
Yes
A only
A only
No
A + B
No
No
PDM microphone inputs
Max node to node cable length
1 N/A means not applicable.
2 mics2
5 m
4 mics
15 m
4 mics
15 m
4 mics
15 m
4 mics
5 m
2 PDM microphones must be connected to the DRX0/IO5 pin.
Rev. B
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AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
A2B BUS DETAILS
control frame. Every slave can use or consume some of the
downstream data and add data for downstream nodes. The last
slave node transceiver responds after the response time with a
synchronization response frame (SRF). Upstream synchronous
data is added by each node directly after the response frame.
Each node can also use or consume upstream data.
Figure 2 shows a single-master, multiple-slave A2B communica-
tions system with the master transceiver controlled by the host.
The host generates a periodic synchronization signal on the
I2S/TDM interface at a fixed frequency (typically 48 kHz) to
which all A2B nodes synchronize.
The embedded control and response frames allow the host to
individually address each slave transceiver in the system. The
host also enables access to remote peripheral devices that are
connected to the slave transceivers via the I2C or SPI ports for
I2C to I2C communication over distance between multiple
nodes.
All nodes in an A2B system are sampled synchronously in the
same A2B superframe. Synchronous I2S/TDM downstream data
from the master arrives at all slaves in the same A2B superframe,
and the upstream audio data of every node arrives synchro-
nously in the same I2S/TDM frame at the master. The remaining
audio phase differences between slaves can be compensated for
by register-programmable fine adjustment of the SYNC pin sig-
nal delay.
Communications along the A2B bus occur in periodic super-
frames. The superframe frequency is the same as the
synchronization signal frequency, and data is transferred at a bit
rate that is 1024 times faster (typically 49.152 MHz). Each
superframe is divided into periods of downstream transmission,
upstream transmission, and no transmission (where the bus is
not driven). Data is exchanged over the A2B bus in up to 32
equal width slots for both upstream and downstream
transmissions.
The A2B bus also communicates the following control and
status information between nodes:
• I2C to I2C communication
• General-purpose input/output (GPIO)
• Interrupts
There is a sample delay incurred for data moving between the
A2B bus and the I2S/TDM interfaces because data is received
and transmitted over the I2S/TDM every sample period (typi-
cally 48 kHz). This timing relationship between samples over
the A2B bus is shown in Figure 4.
MASTER
2
I S/TDM
2
A B
Note in Figure 4, both downstream and upstream samples are
named for the frame where they enter the A2B system as follows:
HOST
DSP
TRANSCEIVER
2
2
A B
I C
• Data transmitted by the master node transceiver in Super-
frame M creates Downstream Data M.
2
2
I S/TDM
SLAVE A B
TRANSCEIVER
• Data transmitted by the slave node transceivers in Super-
frame N creates Upstream Data N.
• Data received over the I2S/TDM interface by the A2B trans-
ceiver is transmitted over the A2B bus in the next
superframe.
2
2
I C
A B
2
2
I S/TDM
SLAVE A B
TRANSCEIVER
• Data on the A2B bus is transmitted over the I2S/TDM inter-
2
face of an A2B transceiver in the next superframe.
I C
2
• Data transmitted across the A2B bus (master to slave or
slave to master) has two frames of latency plus any internal
delay that has accumulated in the transceivers as well as
delays due to wire length. Therefore, overall latency is
slightly over two samples (<50 μs at 48 kHz sample periods)
from the I2S/TDM interface in one A2B transceiver to the
I2S/TDM interface of another A2B transceiver.
A B
2
2
I S/TDM
SLAVE A B
TRANSCEIVER
2
I C
To support and extend the A2B bus functions and performance,
the transceivers have additional features, as described in the fol-
lowing sections.
Figure 2. Communication System Block Diagram
In Figure 3, a superframe is shown with an initial period of
downstream transmission and a later period of upstream
transmission.
All signals on the A2B bus are line coded, and the master node
forwards the synchronization signal downstream from the mas-
ter transceiver to the last slave node transceiver in the form of a
synchronization preamble. This preamble is followed by control
data to build a synchronization control frame (SCF). Down-
stream, TDM synchronous data is added directly after the
Rev. B
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AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
SUPERFRAME: 20.83ȝs FOR 48kHz SAMPLING RATE
SYNCH
CONTROL
FRAME
SYNCH
RESPONSE
FRAME
SYNCH
CONTROL
FRAME
DOWNSTREAM
UPSTREAM
2
2
A B DATA SLOTS
A B DATA SLOTS
Figure 3. A2B Superframe
MASTER NODE
2
I S TX
2
2
2
I S UPSTREAM DATA N
2
-
2
I S UPSTREAM DATA N
-
1
I S UPSTREAM DATA N
DATA
2
2
2
I S RX
DATA
I S DOWNSTREAM DATA M
I S DOWNSTREAM DATA M
+
1
I S DOWNSTREAM DATA M + 2
SUPERFRAME
DNSTREAM
UPSTREAM
DNSTREAM
UPSTREAM
DNSTREAM
UPSTREAM
2
2
2
2
2
2
2
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
A B DATA
M
-
1
N
-
1
M
N
M+1
N+1
SLAVE NODE
2
I S RX
2
2
2
I S UPSTREAM DATA N
I S UPSTREAM DATA N + 1
I S UPSTREAM DATA N + 2
DATA
2
2
2
2
I S TX
I S DOWNSTREAM DATA M
-
2
I S DOWNSTREAM DATA M
-
1
I S DOWNSTREAM DATA M
DATA
Figure 4. A2B Bus Synchronous Data Exchange
I2C INTERFACE
The I2C interface in the transceiver provides access to the inter-
nal registers. Operation is not guaranteed above the VI2C_VBUS
specification. The I2C interface has the following features:
• Slave functionality in the A2B master
• Master or slave functionality in the A2B slave
• Multimaster support in the A2B slave
• 100 kbps or 400 kbps rate operation
• 7-bit addressing
BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver
through a master configured AD2425W transceiver. See the
AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B
Transceiver Technical Reference for details.
I2S/TDM INTERFACE
The I2S/TDM serial port operates in full-duplex mode, where
both the transmitter and receiver operate simultaneously using
the same critical timing bit clock (BCLK) and synchronization
(SYNC) pins. A2B slave transceivers generate the timing signals
on the BCLK and SYNC output pins. A2B master transceivers
use the same BCLK and SYNC pins as inputs, which are driven
by the host device. The I2S/TDM port includes the following
features:
• Single-word and burst mode read and write operations
• Clock stretching
All transceivers can be accessed by a locally connected processor
using the 7-bit I2C device address (BASE_ADDR) established by
the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at
power-on reset, thus providing for up to four master devices
connecting to the same I2C bus. A slave configured transceiver
recognizes only this I2C device address. A master configured
transceiver, however, also recognizes a second I2C device
address for remote access to slave nodes over the A2B bus
(BUS_ADDR). The least significant bit (LSB) of the 7-bit device
address determines whether an I2C data exchange uses the
BASE_ADDR (Bit 1 = 0) to access the transceiver or
• Programmable clock and frame sync timing and polarity
• Numerous TDM operating modes
• 16- or 32-bit data width
• Simultaneous operation with PDM port
• Single- or dual-pin input/output (I/O)
Rev. B
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AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
I2S Reduced Rate
used to customize handshaking among numerous nodes in a
system to coordinate system events, such as synchronizing
audio.
Slave transceivers can run the I2S/TDM/PDM interface at a
reduced rate frequency, with respect to the superframe rate. The
reduced rate frequency is derived by dividing the superframe
rate from a programmable set of values. Different slave nodes
can be configured to run at different reduced I2S/TDM rates.
DATA SLOT EXCHANGE BETWEEN SLAVES
Using the DTX0 and DTX1 pins, slave transceivers can selec-
tively output upstream or downstream data that originates from
other nodes without the need for data slots to be routed through
the master node. Receive data channels can be skipped based on
a programmable offset, when the data is presented as upstream
or downstream slots to the A2B bus.
The transceiver provides an option for a processor to track the
full rate audio frame, which contains new reduced rate samples.
The IO7 pin can be used as a strobe, and the direction can be
configured as an input or output.
PULSE DENSITY MODULATION (PDM) INTERFACE
CLOCK SUSTAIN STATE
The PDM block on the transceiver converts a PDM input
stream into pulse code modulated (PCM) data to be sent over
the A2B bus and/or out to the local node through the I2S/TDM
port. It supports high dynamic range microphones with high
signal-to-noise ratio (SNR) and extended maximum sound
pressure level. The PDM interface supports 12 kHz and 24 kHz
frame rates in addition to a 48 kHz frame rate and can be used
on both master and slave transceivers.
In the clock sustain state, audio signals of locally powered slave
nodes are attenuated in the event of lost bus communication.
When the bus loses communication and a reliable clock cannot
be recovered by the slave node, the slave node transceiver enters
the sustain state and, if enabled, signals this event to a GPIO pin.
In the clock sustain state, the phase-locked loop (PLL) of the
slave node transceiver continues to run for 1024 SYNC periods,
while attenuating the I2S DTX0 to DTX1 data from the current
value to 0. After the 1024 SYNC periods, the slave node trans-
ceiver resets and reenters the power-up state.
Even lower PDM sampling rates (for example, down to 375 Hz)
are possible in combination with the reduced rate feature of the
transceiver. The cutoff frequency of the high-pass filter in the
transceiver PDM block is fixed to 1 Hz.
PROGRAMMABLE SETTINGS TO OPTIMIZE EMC
PERFORMANCE
BCLK can be used to clock PDM microphones on a slave, but if
PDMCLK/IO7 is used instead, the BCLK frequency can be set to
a different frequency using the I2S/TDM registers. In this case,
PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture
PDM input on DRX0/DRX1. The clock rate from PDMCLK is
64× the SYNC frequency.
The following programmable features can be used to improve
electromagnetic compatibility (EMC) performance.
Programmable LVDS Transmit Levels
The low voltage differential signal (LVDS) transmitter can be set
to transmit the signal at high, medium, or low levels. Higher
transmit levels yield greater immunity to EMI, whereas lower
transmit levels can reduce emissions from the twisted-pair
cables that link A2B bus nodes together. The improved LVDS
receiver (compared to other members of the AD242xW family)
maintains robust operation when transmit levels are lowered.
On a master node, BCLK is always an input, so the clock to
PDM microphones that are attached to a master typically comes
from PDMCLK/IO7. It is possible to use BCLK to drive the
PDM clock inputs on a master node, but this restricts the possi-
ble TDM settings because BCLK is required to fall within the
f
BCLK specification in Table 4.
BCLK and PDMCLK/IO7 can also be used concurrently to
clock PDM microphones at the same frequency and phase
alignment, but with opposite polarity. Additionally, a register
setting selects whether rising edge data or falling edge data is
sampled first.
Spread-Spectrum Clocking
Spread-spectrum clocking can be used to reduce narrow-band
emissions on a printed circuit board (PCB). Spread-spectrum
clocking is disabled on the transceiver by default, but spread-
spectrum clocking for all internal clocks can be enabled during
discovery by a register write.
GPIO OVER DISTANCE
The transceiver supports general-purpose input/output (GPIO)
between multiple nodes without host intervention after initial
programming. The host is required only for initial setup of the
GPIO bus ports. I/O pins of different nodes can be logically OR
or AND gate combined.
If spread-spectrum clocking support is enabled for the internal
clocks, spread-spectrum clocking can also be enabled for both
the I2S interface and the programmed CLKOUTs. Enabling
spread-spectrum clocking for internal clocks, CLKOUTs, and
the I2S interface may reduce narrow-band emissions by several
dB on a particular node. When spread-spectrum clocking is
enabled on a clock output, the time interval error (TIE) jitter on
that clock increases.
MAILBOXES
The transceiver supports interrupt driven, bidirectional mes-
sage exchange between I2C master devices (microcontrollers) at
different slave nodes and the host connected to the master node
transceiver in two dedicated mailboxes. The mailboxes can be
Unique ID
Each transceiver contains a unique ID, which can be read from
registers using software. If a read of the unique ID fails, an inter-
rupt can be generated.
Rev. B
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January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Support for Crossover or Straight Through Cabling
Straight through cables can be supported by swapping the dc
coupling at the B-side connector. See the Designer Reference
section for details about the reference schematics.
Data Only and Power Only Bus Operation
The A2B bus can be operated without closing the PMOS switch
to send a dc bias downstream. Conversely, a dc bias can also be
sent downstream without the presence of data. These features
are available for debug purposes only.
Rev. B
| Page 7 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
SPECIFICATIONS
For information about product specifications, contact your
Analog Devices, Inc. representative.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
Power Supplies
VDVDD
VIOVDD
Digital Core Logic Supply Voltage
Digital Input/Output (I/O) Supply 3.3 V I/O
1.70
3.0
1.90
3.3
1.98
3.63
V
V
Voltage
1.8 V I/O
1.7
1.7
1.9
1.9
1.98
1.98
V
V
VPLLVDD
Phased-Locked Loops (PLL) Supply
Voltage
VTRXVDD
Transceiver Supply Voltage
External I2C Bus Voltage
Applies to the ATRXVDD and BTRXVDD pins 3.0
3.3 V VIOVDD, 1.8 V VIOVDD 1.7
3.3
3.63
3.63
V
V
VI2C_VBUS
1.9/3.3
Voltage Regulator (VREG1, VREG2)
VVIN
Regulator Input Supply Voltage
Specification must be met at the VIN pin of 3.7
each A2B bus transceiver
9.0
V
V
V
VRST
VVIN Chip Reset Assertion Voltage VVIN dropping
Threshold
2.65
2.97
3.25
VRSTN
VVIN ChipResetDeassertionVoltage VVIN rising
Threshold
3.11
Digital I/O
1
VIH
High Level Input Voltage
Low Level Input Voltage
VIOVDD = 1.98 V
0.7 × VIOVDD
2.2
V
V
V
V
V
V
VIOVDD = 3.63 V
1
VIL
VIOVDD = 1.70 V
0.3 × VIOVDD
0.8
VIOVDD = 3.00 V
2
VIH_I2C
VIOVDD = 3.63 V, 1.98 V
VIOVDD = 3.00 V, 1.70 V
0.7 × VIOVDD
VIL_I2C
0.3 × VIOVDD
Temperature
TJ
TJ
Junction Temperature
Junction Temperature
TAMBIENT = 0°C to 70°C
0
105
°C
°C
TAMBIENT = –40°C to +85°C
–40
+105
AUTOMOTIVE USE ONLY
TJ Junction Temperature
(Automotive Grade)
TAMBIENT = –40°C to +105°C
–40
+1253
°C
1 Applies to PDMCLK/IO7, BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0 pins.
2 Applies to SDA and SCL pins.
3 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices, Inc. for more information.
Rev. B
| Page 8 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
ELECTRICAL CHARACTERISTICS
Parameter
Current
IDVDD
Conditions
Min
Typ
Max
Unit
Digital Core Logic Supply Current VDVDD = 1.98 V
9.0
0.5
10.5
1.1
12.0
12.0
1.5
13.0
mA
mA
mA
IPLLVDD
PLL Supply Current
Transceiver Supply Current
VPLLVDD = 1.98 V
TX enabled, RX disabled, 100% duty cycle 9.5
(ITXVDD), VTRXVDD = 3.63 V
1
ITRXVDD
TX disabled, RX enabled, 100% duty cycle 2.2
(IRXVDD), VTRXVDD = 3.63 V
TX disabled, RX disabled, 0% activity level, 1.0
2.8
1.7
3.5
2.5
mA
mA
V
TRXVDD = 3.63 V
Voltage Regulator (VREG1, VREG2)
VVOUT1
VVOUT2
VREG1 Output Voltage
VREG2 Output Voltage
VREG1 Output Current
VREG2 Output Current
VREG1 External Device Current
1.80
3.15
1.90
3.30
1.98
3.45
40.0
50.0
V
V
mA
mA
mA
2
IVOUT1
2
IVOUT2
3, 4
IVEXT1
IVOUT1 – IPLLVDD – IDVDD – IIOVDD current
available to external device
IVOUT2 – ITRXVDD current available to external
device
20
20
3, 4
IVEXT2
VREG2 External Device Current
mA
VOUT1/VIN
VOUT2/VIN
Line Regulation
Line Regulation
VVIN = 3.7 V to VIN
VVIN = 3.7 V to VIN
0
0.017
0.030
+0.005
0.009
0.008
600
0.055
0.060
+0.055
0.017
0.015
750
29
25
25
%/V
%/V
%/V
%/mA
%/mA
μA
mA
μF
μF
0.013
–0.025
V
VIN = 5.0 V to 8 V
VOUT1/IOUT1 Load Regulation
VOUT2/IOUT2 Load Regulation
IVINQ
VVIN = 5.0 V, IVOUT1 = 1 mA to 40 mA
VVIN = 5.0 V, IVOUT2 = 1 mA to 50 mA
VVIN =VIN, IVOUT1 = 0 mA, IVOUT2 = 0 mA
VVIN = VIN, IVOUT1 = 8 mA, IVOUT2 = 20 mA
Quiescent Current
530
IVIN
Operational Current
VREG1 Load Capacitance
VREG2 Load Capacitance
CLoad1
CLoad2
Digital I/O
IIH
1.0
2.2
Input Leakage, High
Input Leakage, Low
VIOVDD = 3.63 V, VIN = 3.63 V
VIOVDD = 3.63 V, VIN = 0 V
VIOVDD = 1.9 V, VIN = 3.63 V
VIOVDD = 1.70 V, IOH = 1 mA
VIOVDD = 3.00 V, IOH = 1 mA
VIOVDD = 3.00 V, IOL = 1 mA
VIOVDD = 1.70 V, IOL = 1 mA
VIOVDD = 3.00 V, IOL = 1.5 mA
VIOVDD = 1.70 V, IOL = 1.5 mA
10.0
10.0
10.0
μA
μA
μA
V
V
V
V
V
V
pF
IIL
IOZH_I2C
5
Three-State Leakage Current
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Low Level Output Voltage
I2C Low Level Output Voltage
I2C Low Level Output Voltage
Pin Capacitance
VOH1.9
VOH3.3
1.35
2.40
6
VOL
VOL
0.40
0.40
0.40
0.40
5
6
5, 7
VOL_I2C
VOL_I2C
5, 7
CPD
4.8
Negative Bias Switch
IVSSN
IVSSN
RVSSN
Internal VSSN Switch Current
Internal VSSN Switch Current
Internal VSSN On Resistance
AD2426(W)/AD2427(W)/AD2428(W)
AD2420(W)/AD2429W
300
100
1.2
mA
mA
Ω
1 Master and last slave only consume half the transceiver current because only one of the two TRX blocks is used.
2 In a bus powered system, IVOUT has a direct impact on IVSSN and VVIN in other nodes. For more information, see the Power Analysis section.
3 Consider the package thermal limits when dissipating current above typical limits. For more information, see the Thermal Characteristics section.
4 Must comply with IVOUT1 and IVOUT2 maximum.
5 Applies to SDA and SCL pins.
6 Applies to BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0, PDMCLK/IO7 pins.
7 The minimum IOL current is lower than the I2C specification because the SDA and SCL pins are designed for a limited number of I2C attached slave devices.
Rev. B
| Page 9 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 2. Differential Input/Output
Parameter
Conditions
Min
Typ
Max
Unit
LVDS
|VOD
|
Differential Output Voltage Magnitude See Figure 19
High Transmit Level
425
315
210
545
415
305
mV
mV
mV
Medium Transmit Level
Low Transmit Level
Receiver
VTH
Differential Input Threshold Voltage
–52
+52
mV
Rev. B
| Page 10 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
POWER SUPPLY REJECTION RATIO (PSRR)
Typical PSRR at TJ = 40°C with load capacitance
CLOAD = 4.7 ꢀF || 100 ꢀF.
0
0
–10
VIN = 3.7V
VIN = 3.7V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
–10
VIN = 4.0V
VIN = 5.0V
–20
–20
VIN = 6.0V
VIN = 7.0V
–30
–30
VIN = 8.0V
VIN = 9.0V
–40
–40
–50
–60
–50
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. VOUT1 PSRR, IVOUT1 = 10 mA
Figure 7. VOUT2 PSRR, IVOUT2 = 10 mA
0
–10
0
–10
VIN = 3.7V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
VIN = 3.7V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. VOUT1 PSRR, IVOUT1 = 40 mA
Figure 8. VOUT2 PSRR, IVOUT2 = 50 mA
Rev. B
|
Page 11 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
TIMING SPECIFICATIONS
Table 3. Clock and Reset Timing (A2B Master)
Parameter
Min
Typ
Max
Unit
Timing Requirements
fSYNCM
SYNC Pin Input Frequency Continuous Clock
43.6
44.1, 48.0
0.29
48.5
1.0
kHz
ns
tSYNCIJ
SYNC Pin Input Jitter RMS TIE
SYNC Pin Output Jitter RMS TIE
Bus Clock
Delay from First Missed SYNC to Reset (A2B Master)
Delay from First Missed SCF to Reset (A2B Slave)
PLL Lock Time
tSYNCOJ
fSYSBCLK
tDNSYNCR
2.6
ns
1024 × fSYNCM
kHz
ms
ms
ms
1
0.64
0.64
0.74
0.74
1
tDNSCFR
tPLK
7.5
1 Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset.
Table 4. Pulse Density Modulation Microphone Input Timing
Parameter
Min
Typ
Max
Unit
Timing Requirements
tRISS
tRIHS
tRISS
tRIHS
DRXn Input Setup Before BCLK
12.0
0
ns
ns
ns
ns
DRXn Input Hold After BCLK
DRXn Input Setup Before PDMCLK
DRXn Input Hold After PDMCLK
12.5
0
Switching Characteristics
fBCLK
tBCLKOJ
tSOL
BCLK/PDMCLK Output Frequency
3.05
3.18
175
MHz
ps
BCLK/PDMCLK Output Jitter RMS Cycle to Cycle
BCLK/PDMCLK Output Pulse Width Low
161.0
ns
Table 5. GPIO Timing
Parameter
Min
Typ
Max
Unit
ns
Timing Requirement
tFIPW
Input Pulse Width
tSYSBCLK + 1
tSYSBCLK – 1
Switching Characteristic
tFOPW
Output Pulse Width
ns
Rev. B
| Page 12 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 6. I2C Port Timing
Parameter
Min
Typ
Max
Unit
Timing Requirements
fSCL
SCL Clock Frequency
0
400
kHz
μs
μs
μs
μs
μs
ns
μs
ns
ns
ns
ns
μs
tSCLH
tSCLL
tSCS
tSCH
tSPS
tDS
SCL Pulse Width High
SCL Pulse Width Low
Start and Repeated Start Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data Setup Time
0.6
1.3
0.6
0.6
0.6
100
0.0
tDH
Data Hold Time
0.9
tSCLR
tSCLF
tSDR
tSDF
tBFT
SCL Rise Time
300
300
300
300
SCL Fall Time
SDA Rise Time
SDA Fall Time
Bus-Free Time Between Stop and Start
1.3
SDA
t
t
SCLF
t
BFT
t
SDF
t
t
t
SDR
t
SCH
SPS
SCLR
t
SCLL
DS
SCL
t
t
SCH
t
t
SCLH
t
SCS
DH
SCS
P
S
S
Sr
Figure 9. I2C Port Timing
Rev. B
| Page 13 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 7. I2S Timing
1.8 V
Max
3.3 V
Unit
Parameter
I2S Slave Timing Requirements (A2B Master)
Min
Min
Max
tBCLKW
BCLK Width
19.5
39.0
2.25
2.0
9.5
19.0
2.25
3.0
ns
ns
ns
ns
ns
ns
ns
ns
tBCLKS
BCLK Period
1
tSIS
SYNC Input Setup Before BCLK Sample Edge
SYNC Input Hold After BCLK Sample Edge
DRXn Input Setup Before BCLK Sample Edge
DRXn Input Hold After BCLK Sample Edge
DRX1 on DTX1 Input Setup Before BCLK Sample Edge
DRX1 on DTX1 Input Hold After BCLK Sample Edge
1
tSIH
1
tRISM
0.5
0.5
1
tRIHM
2.0
1.5
1
tRISM
4.0
4.5
1
tRIHM
0.5
0.5
I2S Slave Switching Characteristics (A2B Master)
2
tDODM
DTXn Output Delay After BCLK Drive Edge
DTXn Output Hold After BCLK Drive Edge
DTXn Data Enable Delay After BCLK Drive Edge
DTXn Data Disable Delay After BCLK Drive Edge
15.25
13.0
12.0
8.0
ns
ns
ns
ns
2
tDOHM
3.0
2.0
3.0
2.0
2
tDOENM
2
tDODIM
I2S Master Timing Requirements (A2B Slave)
1
tRISS
DRXn Input Setup Before BCLK Sample Edge
0.0
5.8
2.5
2.5
0.0
2.0
4.5
0.5
ns
ns
ns
ns
1
tRIHS
DRXn Input Hold After BCLK Sample Edge
1
tRISS
DRX1 on DTX1 Input Setup Before BCLK Sample Edge
DRX1 on DTX1 Input Hold After BCLK Sample Edge
1
tRIHS
I2S Master Switching Characteristics (A2B Slave)
fBCLK
BCLK Output Frequency3
25.0
100
0.55
2.2
50.0
100
0.55
2.2
MHz
ps
tBCLKMOJ
BCLK Output Jitter (RMS Cycle to Cycle, fBCLKS = 12.288 MHz)
Transmit or Receive BCLK Duty Cycle
t
SOL/tSOH
0.45
0.45
tBCLK
ns
tSOJ
SYNC Output Jitter (RMS Cycle to Cycle fSYNCM = 48 kHz)
SYNC Output Delay After BCLK Drive Edge
SYNC Output Hold After BCLK Drive Edge
DTXn Output Delay After BCLK Drive Edge
DTXn Output Hold After BCLK Drive Edge
2
tSOD
6.5
6.5
ns
2
2
2
tSOHD
tDODS
tDOHS
2.8
5.5
4.5
6.0
ns
10.8
9.25
ns
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
3 When VIOVDD = 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I2S devices. The timing violations are seen
when the A2B slave node is receiving and A2B master node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved.
Rev. B
| Page 14 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
DRIVE EDGE
SAMPLE EDGE
tBCLKW
BCLK/PDMCLK
SYNC
tSIS
tSIH
tRISM
tRIHM
RECEIVE DATA
MSB
MSB
MSB
-
-
1
1
(DRXn) CHANNEL
tDODM
tDOHM
TRANSMIT DATA
(DTXn) CHANNEL
MSB
Figure 10. I2S Slave (A2B Master) Timing
DRIVE EDGE
SAMPLE EDGE
t
SOL/tSOH
BCLK/PDMCLK
tSOD
tSOHD
SYNC
tRISS
tRIHS
RECEIVE DATA
MSB
MSB
-
-
1
1
(DRXn) CHANNEL
tDODS
tDOHS
TRANSMIT DATA
(DTXn) CHANNEL
MSB
MSB
Figure 11. I2S Master (A2B Slave) Timing
DRIVE EDGE
DRIVE EDGE
BCLK
tDOENM
tDODIM
TRANSMIT DATA
(DTXn) CHANNEL
Figure 12. I2S Slave (A2B Master) Enable and Three-State Timing
Rev. B
| Page 15 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
POWER-UP SEQUENCING RESTRICTIONS
When externally supplied, VDVDD and VIOVDD must reach at least
90% of specification before VVIN begins ramping. To avoid dam-
age to input pins and to ensure correct sampling of the
ADR1/ADR2 pins at start-up, VIOVDD must be within specifica-
tion before input signals are driven by external devices.
Table 8. Power-Up Timing
Parameter
Min
Max
Unit
Timing Requirements
tVIN
When Externally Supplied, VDVDD and VIOVDD Must Reach 90% of Specification
Before VVIN Begins Ramping
Minimum Time Required for VVIN to be Held Below VRST to Assert Power on Reset 25
>0
ms
ms
tPORST
V
V
IOVDD
t
DVDD
|
PORST
t
VIN
MAX V
RSTN
MIN V
RST
V
VIN
Figure 13. Power-Up Sequencing Timing with Externally Supplied VDVDD and VIOVDD
Rev. B
| Page 16 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
A2B BUS SYSTEM SPECIFICATION
Table 9. A2B System Specifications
Parameter
System Specification
Cable
Unshielded, single, twisted pair wire (UTP) with 100 Ω differential impedance. EMC performance
and full functionality under worst-case environmental conditions is confirmed with Leoni Dacar
545 cable (76D00305).
Maximum Cable Length
AD2428(W)Mastered System
AD2429(W) Mastered System
Maximum Number of Nodes
AD2428(W) Mastered System
AD2429(W) Mastered System
Maximum Number of Audio Slots
AD2426(W)/AD2427(W)/AD2428(W)1
AD2420(W)/AD2429(W)1
40 m total, 15 m between nodes.
10 m total, 5 m between nodes.
11 nodes (1 master node and 10 slave nodes).
Three nodes (1 master node and 2 slave nodes).
64 total, up to 32 upstream and 32 downstream slots, depending upon system design.
AD2429(W): 4 upstream and 2 downstream slots, depending upon system design.
AD2420(W): 2 upstream slots, depending upon system design.
Number of Audio Channels per Slave Node Individually programmable 0 to 32 upstream channels and 0 to 32 downstream channels.
Synchronous A2B Data Slot Size
8, 12, 16, 20, 24, 28, or 32 bits to match I2S/TDM data-word lengths. Same slot size for all nodes.
Upstream and downstream can choose different slot sizes. 12-, 16-, or 20-bit slot sizes can carry
compressed data over the A2B bus for 16-, 20-, or 24-bit I2S/TDM word lengths.
Audio Sampling Frequency
44.1 kHz to 48 kHz. All nodes sample synchronously. Slave node transceivers support sample rates
(fS) of 1× (48 kHz), 2× (96 kHz) or 4× (192 kHz), individually configured per slave.
To support 2× and 4× sampling rates in slaves, the master uses two and four times the number of
I2S/TDM data channels as the 1× sampling frequency (fSYNCM) interface to the host.
Transceivers also support reduced rate sampling for 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz,
2 kHz, 1.71 kHz, or 1.5 kHz at a low latency 48 kHz superframe rate.
Discovery Time
Less than 35 ms per node. Much less than 350 ms for total system startup in a system with 10 nodes.
Includes register initialization.
Bit Error Detection
Error Correction
Robust error detection for control data and status data with 16-bit cyclic redundancy check (CRC).
Parity and line code error detection on synchronous data slots with audio error correction (repeat
of last known good data).
For 24-bit and 32-bit data channels, single error correction and double error detection (SECDED) of
synchronous data slots is possible.
Location and cause of failure can be detected for A2B wires shorted to a high voltage (for example,
positive terminal of car battery), shorted to ground, wires shorted to each other, wires reversed or
open connection.
Failure Diagnostics1
System EMI/EMC
System ESD
Meets or exceeds industry specifications for robustness (ISO 11452-2, ISO 11452-4,
ISO 7637-3) and emissions (CISPR25).
See IEC ESD ratings in Table 12 for terminals.
1
See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information.
Rev. B
| Page 17 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
RMS Time Interval Error (TIE) Jitter
0.1
Clocks in an A2B system are passed from the master to Slave 0,
from Slave 0 to Slave 1, and so on. Each transceiver adds self jit-
0
ter to the incoming jitter, which results in jitter growth from the
master to the nth slave. Table 10 illustrates typical rms TIE jitter
–0.1
growth.
–0.2
Table 10. SYNC Output RMS TIE Jitter at Each Slave
Slave Node
Typ
1.57
1.79
1.91
2.04
2.15
2.27
2.44
2.47
2.58
2.70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–0.3
–0.4
–0.5
1
2
3
4
0.0001
0.001
0.01
0.1
1
5
NORMALIZED FREQUENCY (RELATIVE TO fSYNCM
) (Hz)
6
Figure 15. PDM Frequency Response
7
8
160
140
120
100
80
9
10
5.50
PDM TYPICAL PERFORMANCE CHARACTERISTICS
Figure 14 through Figure 18 and Table 11 describe typical PDM
performance characteristics.
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
40
20
0
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 16. PDM Group Delay vs. Frequency, fSYNCM = 48 kHz
–120
CH1
–130
–140
–150
–160
–170
–180
–190
CH2
0
–20
–40
–60
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 14. PDM FFT, fSYNCM = 48 kHz, –60 dB Frame Sync Input
–80
–100
–120
–140
0.0001
0.001
0.01
0.1
1
) (Hz)
NORMALIZED FREQUENCY (RELATIVE TO fSYNCM
Figure 17. PDM Total Harmonic Distortion + Noise (THD + N) vs. Normal-
ized Frequency (Relative to fSYNCM
)
Rev. B
| Page 18 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
0
–20
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
FREQUENCY (MHz)
Figure 18. PDM Out of Band Frequency Response (48 kHz Output)
Table 11. PDM Interface Performance Specifications
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic Range
With A-Weighted Filter (RMS)
SNR
20 Hz to 20 kHz, –60 dB input
120
dB
dB
A-weighted, fourth-order input
Default is 64×
120
Decimation Ratio
Frequency Response
Stop Band
64×
–0.1
128×
256×
+0.01
DC to 0.45 fSYNCM
dB
0.566
fSYNCM
Attenuation
74
dB
Group Delay
0.02 fSYNCM input signal
PDM to PCM
3.80
0
fSYNCM cycles
dB
Gain
Start-Up Time1
Bit Width
48
24
fSYNCM cycles
Bits
Internal and output
1 The PDM start-up time is the time for the filters to settle after the PDM block is enabled. It is the time to wait before data is guaranteed to meet the specified performance.
Rev. B
| Page 19 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Permanent damage can occur if the digital pin output current
ABSOLUTE MAXIMUM RATINGS
per pin group value is exceeded. For example, if three pins from
Group 2 in Table 13 are sourcing or sinking 2 mA each, the total
current for those pins is 6 mA. Up to 9 mA can be sourced or
sunk by the remaining pins in the group without damaging the
device.
Stresses at or above those listed in Table 12 can cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
Table 13. Total Current Pin Groups
Group
Pins in Group
Table 12. Absolute Maximum Ratings
1
2
IRQ/IO0, ADR1/IO1, ADR2/IO2
BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5,
DRX1/IO6, IO7
Parameter
Rating
VIN to VSS
–0.7 V to +30 V
–0.3 V to +3.63 V
–0.3 V to +1.98 V
–0.3 V to +1.98 V
–0.3 V to +3.63 V
–0.3 V to VIOVDD + 0.5 V
–0.33 V to +3.63 V
–0.33 V to +2.10 V
–0.33 V to +5.5 V
Power Supply IOVDD to VSS
Power Supply DVDD to VSS
Power Supply PLLVDD to VSS
Power Supply TRXVDD to VSS
Digital Pin Output Voltage Swing1
Input Voltage2, 3
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board (PCB), use the following equations:
TJ = TCASE + ΨJT × PD
where:
TJ = junction temperature (°C).
T
CASE = case temperature (°C) measured by customer at top cen-
Input Voltage2, 4
I2C Input Voltage2, 5
ter of package.
Ψ
JT = values in Table 14.
A2B Bus Terminal Voltage
AP, AN, BP, and BN Pins
SENSE, SWP, VSSN Voltage to VSS
Storage Temperature Range
Junction Temperature While Biased
ESD Rating HBM
PD = power dissipation.
–0.5 V to +4.1 V
+30 V maximum
–65°C to +150°C
–40°C to +125°C
Values of JA are provided for package comparison and PCB
design considerations. Use JA for a first-order approximation
of TJ by the following equation:
TJ = TA + JA × PD
where TA = ambient temperature (°C).
Values of JC are provided for package comparison and PCB
VIN and SWP Pins
2.5 kV
2.5 kV
2.5 kV
design considerations when an external heat sink is required.
AP, AN, BP, and BN Pins
All Other Pins
Values of JB are provided for package comparison and PCB
design considerations.
ESD Rating FICDM
Thermal characteristics of the LFCSP_SS package are shown in
Table 14. See JESD51-13 for detailed parameter definitions.
The junction to board measurement complies with JESD51-8.
The junction to case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
All Pins
1.25 kV
System ESD Rating CON1-A and CON1-B
Terminals6
IEC 61000-4-2, Air Discharge
15 kV
12 kV
IEC 61000-4-2, Contact Discharge
Digital Pin Output Current per Pin Group7 15 mA
Table 14. Thermal Characteristics
1 Applies to BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6,
IRQ/IO0, ADR1/IO1, ADR2/IO2, PDMCLK/IO7.
2 Only applies when the related power supply (VIOVDD) is within specification. When
the power supply is below specification, the range is the voltage being applied to
that power domain 0.2 V.
Parameter
JA
JMA
JMA
JC
JB
JT
JT
JT
Conditions
Typical (°C/W)
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 0 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
31.6
28.8
28.1
4.6
3 Applies when nominal VIOVDD is 3.3 V.
4 Applies when nominal VIOVDD is 1.8 V.
5 Applies to SCL and SDA.
14.7
0.20
0.27
0.30
6 CON1-A and CON1-B are connectors.
7 For more information, see the following description and Table 13.
Rev. B
|
Page 20 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
The 32-lead LFCSP_SS package requires thermal trace squares
30
and thermal vias to an embedded ground plane in the PCB. The
exposed paddle must connect to ground for proper operation to
data sheet specifications. Refer to JEDEC standard JESD51-5 for
more information.
IOVDD = 3.6V @ – 40°C
IOVDD = 3.3V @ 25°C
IOVDD = 3.0V @ 125°C
20
10
0
V
OH
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
– 10
– 20
– 30
V
OL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
TEST CIRCUITS AND SWITCHING
CHARACTERISTICS
Figure 21. GPIO, BCLK, and SYNC Drivers (DS0, 3.3 V IOVDD)
Figure 19 shows a line driver voltage measurement circuit of the
differential line driver and receiver AP/AN and BP/BN pins.
0
IOVDD = 1.9V @ – 40°C
– 0.5
IOVDD = 1.8V @ 25°C
IOVDD = 1.7V @ 125°C
– 1.0
– 1.5
– 2.0
– 2.5
– 3.0
– 3.5
– 4.0
– 4.5
– 5.0
AP/BP
ꢀꢁꢂꢁꢃȍ
VOD
AN/BN
V
OL
Figure 19. Differential Line Driver Voltage Measurement
OUTPUT DRIVE CURRENTS
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
SOURCE VOLTAGE (V)
Figure 20 through Figure 25 show typical current voltage char-
acteristics for the output drivers of the transceiver. The curves
represent the current drive capability of the output drivers as a
function of output voltage. Drive Strength 0 is DS0, and Drive
Strength 1 is DS1.
Figure 22. I2C Drivers (1.8 V IOVDD)
0
– 2
IOVDD = 3.6V @ – 40
IOVDD = 3.3V @ 25
IOVDD = 3.0V @ 125
°C
°
C
°
C
– 4
8
IOVDD = 1.9V @ – 40°C
– 6
6
4
IOVDD = 1.8V @ 25°C
IOVDD = 1.7V @ 125°C
– 8
V
– 10
– 12
– 14
– 16
– 18
OH
2
V
OL
0
– 2.0
– 4.0
– 6.0
– 8.0
V
OL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 23. I2C Drivers (3.3 V IOVDD)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
SOURCE VOLTAGE (V)
Figure 20. GPIO, BCLK, and SYNC Drivers (DS0, 1.8 V IOVDD)
Rev. B
| Page 21 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
The output enable time, tENA, is the interval from the point when
15
a reference signal reaches a high or low voltage level to the point
when the output starts driving, as shown on the right side of
Figure 27. If multiple pins are enabled, the measurement value
is that of the first pin to start driving.
IOVDD = 1.9V @ – 40°C
IOVDD = 1.8V @ 25°C
IOVDD = 1.7V @ 125°C
10
5
V
OH
0
REFERENCE
SIGNAL
– 5
V
OL
– 10
tDIS
tENA
– 15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
SOURCE VOLTAGE (V)
Figure 24. GPIO, BCLK, and SYNC Drivers (DS1, 1.8 V IOVDD)
60
40
IOVDD = 3.6V @ – 40°C
IOVDD = 3.3V @ 25°C
IOVDD = 3.0V @ 125°C
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
20
0
Figure 27. Output Enable/Disable
V
OH
OL
Output Disable Time Measurement
– 20
–40
– 60
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 27.
V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 25. GPIO, BCLK, and SYNC Drivers (DS1, 3.3 V IOVDD)
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 28). VLOAD is equal
to VIOVDD/2. Figure 29 through Figure 32 show how output rise
time varies with capacitance. The delay and hold specifications
given must be derated by a factor derived from these figures.
The graphs in Figure 29 through Figure 32 cannot be linear out-
side the ranges shown.
TEST CONDITIONS
All timing parameters in this data sheet were measured under
the conditions described in this section. Figure 26 shows the
measurement point for ac measurements (except output
enable/disable). The measurement point, VMEAS, is VIOVDD/2 for
VIOVDD (nominal) = 3.3 V.
INPUT
OR
OUTPUT
V
V
MEAS
MEAS
Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Enable Time Measurement
Output pins are considered enabled when they make a transi-
tion from a high impedance state to the point when they start
driving.
Rev. B
|
Page 22 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
9
8
7
6
5
4
3
2
1
0
TESTER PIN ELECTRONICS
50:
V
LOAD
T1
DUT
OUTPUT
45:
70:
tRISE
ZO = 50:ꢀ(impedance)
TD = 4.04 ꢀ 1.18 ns
50:
tFALL
0.5pF
4pF
2pF
400:
DRIVE STRENGTH = 1
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
5
10
15
20
25
30
35
40
45
0
LOAD CAPACITANCE (pF)
Figure 30. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VIOVDD = 1.8 V, TJ = 25°C)
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY,THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
10
9
Figure 28. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
8
18
16
14
7
6
tRISE
5
tFALL
4
3
2
12
tRISE
10
8
tFALL
1
DRIVE STRENGTH = 0
6
4
0
10
20
30
40
50
60
0
LOAD CAPACITANCE (pF)
2
DRIVE STRENGTH = 0
Figure 31. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VIOVDD = 3.3 V, TJ = 25°C)
0
5
10
15
20
25
30
35
40
45
0
LOAD CAPACITANCE (pF)
8
7
6
Figure 29. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VIOVDD = 1.8 V, TJ = 25°C)
5
tRISE
4
tFALL
3
2
1
DRIVE STRENGTH = 1
0
10
20
30
40
50
60
70
80
90
0
LOAD CAPACITANCE (pF)
Figure 32. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VIOVDD = 3.3 V, TJ = 25°C)
Rev. B
|
Page 23 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
The 32-lead LFCSP_SS package pin configuration is shown in
Figure 33. The pin function descriptions are shown in Table 15.
All digital inputs and digital outputs are three-stated with inputs
disabled during reset.
32 31 30 29 28 27 26 25
PLLVDD
DVDD
DVDD
SCL
SDA
IRQ/IO0
ADR1/IO1
ADR2/IO2
1
2
3
4
5
6
7
8
24 BCM
23 BN
22 BP
EPAD
(PIN 33)
21 BTRXVDD
20 ATRXVDD
19 AP
18 AN
17 ACM
TOP VIEW
9 10 11 12 13 14 15 16
PIN 33 IS THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. THIS PIN MUST BE CONNECTED TO GND.
Figure 33. 32-Lead LFCSP_SS and LFCSP Package Pin Configuration
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions
Pin
No. Pin Name
Alternate
Type
PWR
PWR
D_IO
Functions1 Description
1
PLLVDD
None
None
None
Power Supply for PLL. PLLVDD can be supplied by VVOUT1
.
2, 3 DVDD
42
Power Supply for Digital Core Logic. DVDD can be supplied by VVOUT1
.
SCL
Serial Clock for I2C Data Transfers. Digital input in A2B master mode. Digital input (I2C slave) or
output (I2C master) in A2B slave mode. This pin uses open-drain I/O cells and must be pulled up
to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper
resistor value). Connect the pin to ground when the I2C interface is not used.
52
62
SDA
D_IO
D_IO
None
None
I2C Mode Serial Data. This pin is a bidirectional open-drain input/output and must be pulled up
to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper
resistor value). Connect the pin to ground if the I2C interface is not used.
Interrupt Request Output. In master mode, A2B transceivers create event driven interrupt
requests towards the host controller.
IRQ/IO0
In slave mode, this pin indicates mailbox empty/full status to the slave node processor when
mailbox interrupts are enabled.
When not serving as an interrupt output pin, this pin serves as a general-purpose I/O pin with
interrupt request input capability. The IRQ/IO0 pin must be initialized to become either an input
or an output. This pin is high impedance by default.
72
ADR1/IO1
D_IO
CLKOUT1 The ADR1/IO1 and ADR2/IO2 pins set the I2C slave device address during power-on reset; up to
four A2B master transceiver chips connect to the same I2C bus. The ADR1/IO1 pin is high
impedance by default. The ADR1/IO1 pin can then be initialized to become a general-purpose
input/output (GPIO) pin with interrupt request capability.
This pin can be programmed to become a clockoutput (CLKOUT1). The clock output can be used
as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. B
| Page 24 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name
Alternate
Type
Functions1 Description
82
ADR2/IO2
D_IO
CLKOUT2 The ADR1/IO1 and ADR2/IO2 pins set the I2C slave device address during power-on reset; up to
four A2B master transceiver chips connect to the same I2C bus. The ADR2/IO2 pin is high
impedance by default. The ADR2/IO2 pin can then be initialized to become a general-purpose
input/output (GPIO) pin with interrupt request capability.
This pin can be programmed to become a clockoutput (CLKOUT2). The clock output can be used
as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators.
9
IOVDD
PWR
None
Power Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
whichalsosetsthehighestinputvoltagethat isallowedonthedigitalinputpins. TwoI/Ovoltage
ranges are supported (see VIOVDD specifications in the Operating Conditions section). The current
draw of these pins is variable and depends on the loads of the digital outputs. IOVDD can be
sourced by either the VOUT1 or VOUT2 pin. However, if the signals do not originate from logic
supplied by the VOUT1 pin or VOUT2 pin, source IOVDD with an external supply.
10
11
BCLK
SYNC
D_IO
D_IO
PDMCLK
None
Bit Clock. Digital input in master mode. Digital output in slave mode.
When using the PDM interface in slave mode, this pin can operate as the clock output (PDMCLK)
for PDM microphones (the PDMCLK/IO7 pin can also be used).
Synchronization Signal. Digital input in master mode. Digital output in slave mode.
For the AD2428W and AD2429W, the SYNC signal frames a multichannel I2S/TDM data stream.
An A2B master node must have a continuous signal because the A2B master transceiver derives
all clocking information for itself and for the A2B bus from this input.
When this pin stops toggling, the A2B bus resets after a delay. For more information, see Table 3.
122 DTX0/IO3
D_IO
D_IO
None
DRX1
For the AD2428W and ADW2429W, serial I2S/TDM data is driven to the DTX0/IO3 pin in multi-
channel I2S/TDM format.
This pin serves as theIO3 general-purposeI/OpinwhenDTX0 functionis disabled. TheDTX0/IO3
pin is high impedance by default until configured. The pin returns to high impedance when the
chip resets due to a missing synchronization signal or low supply voltage.
For the ADW2420W, AD2426W, and AD2427W, this pin is GPIO only (IO3).
132 DTX1/IO4
For the AD2428W and AD2429W, serial I2S/TDM data is driven to the DTX1/IO4 pin in multi-
channel I2S/TDM format.
When configured as the alternate DRX1 location, the DTX1/IO4 pin receives data presented in
multichannel I2S/TDM format. This alternate location can be used when the DRX0/IO5 and
DRX1/IO6 pins are used to receive PDM microphone data.
This pin serves as the IO4 general-purpose I/O pin when DTX1 and DRX1 functions are disabled.
The DTX1/IO4 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, this pin is GPIO only (IO4).
For the AD2428W and AD2429W, serial I2S/TDM data is received on the DRX0/IO5 pin in multi-
channel I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input
(PDM0). This pin serves as the IO5 GPIO pin when DRX0 and PDM0 functions are disabled. The
DRX0/IO5 pin is high impedance by default until configured. The pin returns to high impedance
when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, the DRX0 function is not supported.
142 DRX0/IO5
D_IO
PDM0
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. B
| Page 25 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name
Alternate
Type
Functions1 Description
152 DRX1/IO6
D_IO
PDM1
For the AD2428W and AD2429W, serial I2S/TDM data is received on the DRX1/IO6 pin in multi-
channel I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input
(PDM1). This pin serves as the IO6 GPIO pin when DRX1 and PDM1 functions are disabled. The
DRX1/IO6 pin is high impedance by default until configured. The pin returns to high impedance
when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, the DRX1 function is not supported.
162 PDMCLK/IO7 D_IO
RRSTRB
PDM Microphone Clock Output.
In master mode, the PDM clock output (PDMCLK) is used to clock PDM microphones. This pin
runs at 64× the SYNC frequency regardless of the BCLK rate used by the host.
When using the PDM interface in slave mode, this pin can still operate as the clock output for
PDM microphones (PDMCLK), but BCLK can also be used.
When PDM functions are disabled, this pin serves as the IO7 GPIO pin. The PDMCLK/IO7 pin can
also be used as a strobe to indicate when reduced rate data is updated (RRSTRB). The
PDMCLK/IO7 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
17
18
ACM
AN
A_IN
A_IO
None
None
Common-Mode Input for Bidirectional, Differential A2B Line Transceiver A.
Inverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 18 is directed
towards the master. Pin 18 is self biased.
19
20
AP
A_IO
PWR
None
None
Noninverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 19 is directed
towards the master. Pin 19 is self biased.
Power Supply for A2B Line Driver and Receiver Circuit. Decouple these pins to VSS with one
shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied
by VOUT2. Supply the ATRXVDD pin for a master, last slave, or daisy-chained slave.
ATRXVDD
21
BTRXVDD
PWR
None
Power Supply for A2B Line Driver and Receiver Circuit. Decouple these pins to VSS with one
shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied
by VOUT2. Supply the BTRXVDD pin for a master, last slave, or daisy-chained slave
22
23
24
25
26
BP
A_IO
A_IO
A_IN
PWR
PWR
None
None
None
None
None
For the AD2427W, AD2428W, and AD2429W, this is the noninverted pin of bidirectional, differ-
entialA2B line driver and Receiver B, which is directed towardsthelastslave. Thispinisselfbiased.
BN
For the AD2427W, AD2428W, and AD2429W, this is the inverted pin of bidirectional, differential
A2B line driver and Receiver B, which is directed towards the last slave. This pin is self biased.
BCM
VSS
VSSN
For the AD2427W, AD2428W, and AD2429W, this is the common-mode input for bidirectional,
differential A2B Line Transceiver B.
Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
For the AD2427W, AD2428W, and AD2429W, this is the power supply return current connection
for the next slave device. Connect to the inductor that provides the negative bias for the next
slave device. The AD2427W, AD2428W, and AD2429W connect VSSN to the local VSS potential
to sequence power to the next slave devices in the chain. VSSN automatically disconnects under
critical fault conditions.
27
28
SWP
D_OUT None
For the AD2427W, AD2428W, and AD2429W, this is the active low open-drain output to drive
the gate of a PMOS switch. The switch is open (SWP pin is high) by default. The switch can be
closed (SWP pin goes low) to sequence power to the next slave devices in the chain. The switch
automatically opens (SWP goes high) under critical fault conditions.
SENSE
A_IN
None
Analog input to sense the power supplied to the next slave device. For the AD2420W, AD2426W,
or a last in line AD2427W/AD2428W/AD2429W, connect this pin to local ground through a 33 kΩ
pull-down resistor.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. B
| Page 26 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name
Alternate
Type
Functions1 Description
29
VOUT2
PWR
None
Second Output of the On-Chip low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the TRXVDD supply pins. External devices also can be powered
by this supply if the current consumption is within the specification. Decouple VOUT2 to VSS
with a 4.7 ꢀF capacitor.
30
31
32
VIN
PWR
PWR
PWR
None
None
None
Power supply pin that accepts a wide input voltage range (see the VVIN specification in the
Operating Conditions section) for an on-chip low dropout voltage regulator.
VSS
Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
VOUT1
First Output of the On-Chip Low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the DVDD and PLLVDD power supply pins. External devices can
be powered by this supply if the current consumption is within the specification. Decouple
VOUT1 to VSS with a 4.7 ꢀF capacitor.
33
EPAD
PWR
None
Power Supply Pin for Return Currents. See other VSS pin description in this table. This pin is the
exposed pad on the bottom of the package and must be connected to GND.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
1 See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information about configuring pins for alternate functions.
2 If the listed functions for this pin are not required, do not connect this pin.
Rev. B
| Page 27 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
POWER ANALYSIS
This section provides information on power consumption of the
A2B system. The intent of power dissipation calculations is to
assist board designers in estimating power requirements for
power supply and thermal relief designs.
Constant Current
All currents that are not influenced directly by A2B bus activity
on other nodes fall under the category of constant current.
Power dissipation on an A2B node depends on various factors,
such as the required external peripheral supply current and bus
activity. An A2B system can be comprised of a mix of bus pow-
ered slaves and local powered slaves. A bus powered slave
derives power from the A2B bus wires. A local powered slave
derives power from separate power wires. Power estimation for
a bus powered system is more complex when compared to a
local powered system. For power analysis, A2B systems with
both local and bus powered slaves must be divided into seg-
ments of nodes that draw from the same power supply.
PLL Supply Current
The PLL supply current is specified as IPLLVDD, which is the static
current in an active transceiver.
VIN Quiescent Current
The VIN quiescent current is specified as the static current
IVINQ. It is independent of the load and does not include any
power drawn from the voltage regulator output pins.
IOVDD Current
The on-chip I2S/TDM/PDM I/O current IIOVDD is based on
dynamic switching currents on the BCLK, SYNC, DTX0, DTX1,
DRX0, and DRX1 pins.
CURRENT FLOW
Figure 34 describe key parameters and equations to calculate
power dissipation on the transceiver. The current flow on an
A2B node incorporates the described current paths.
The dynamic current, due to switching activity on an output
pin, is calculated using the following equation:
• Constant current
Output Dynamic Current = (CPDout + CL) × VIOVDD × f
where:
• IPLLVDD — PLL supply current
• IVINQ — VIN quiescent current
• I2C I/O current
C
PDout = dynamic, transient power dissipation capacitance inter-
nal to the transceiver output pins.
CL = total load capacitance that an output pin sees outside the
transceiver.
• IIOVDD — I2S/TDM/PDM I/O current
• IVEXT1 or IVEXT2 — peripheral supply currents
• IDVDD — digital logic supply current
• ITRXVDD — A2B bus TX/RX current
V
IOVDD = voltage on a digital pin.
f = frequency of switching on the pin.
The dynamic current, due to switching activity on an input pin,
is calculated using the following equation:
• LVDS transceiver supply currents of A and B trans-
ceivers — transmit LVDS TX and receive LVDS RX
I2C activity and the resulting I/O current is considered negligi-
ble when compared to other currents. Therefore, the on-chip
I2C I/O current is not considered when calculating the current
consumption.
Input Dynamic Current = CPDin × VIOVDD × f
where:
C
PDin = dynamic, transient power-dissipation capacitance inter-
nal to the input pins of the transceiver.
IOVDD = the sum of input and output dynamic currents of all
I
pins internally supplied by the IOVDD pin.
f = frequency of switching on the pin.
I
I
VEXT2
Peripheral
Device(s)
VEXT1
I
VIN
I
I
BTRXVDD
ATRXVDD
I
I
I
PLLVDD
IOVDD
DVDD
I
I
VOUT2
VOUT1
I
+ I
1.9V
3.3V
VEXT2
VEXT1
VOUT2
IOVDD DVDD PLLVDD VOUT1
VIN
ATRXVDD BTRXVDD
VSSN
VREG1/2
2
I
VSSN
A B TRANSCEIVER
Figure 34. Current Flow Model
Rev. B
| Page 28 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Peripheral Supply Current
• The number of upstream data bits transmitted in a node =
number of upstream transmitted slots × (bits per slot +
parity bit) where the parity bit = 1. The number of
upstream transmitted slots is the sum of received upstream
slots and locally contributed slots.
Peripheral components that are external to the transceiver also
can be supplied through the voltage regulator outputs of VVOUT1
and VVOUT2. VVOUT1 can supply the current specified as IVEXT1 to
external devices. VVOUT2 can supply the current specified as
IVEXT2 to external devices.
• A side upstream transmitter activity level of a node.
(SRF bits + number of transmitted upstream data bits) ÷
1024.
When bus powered, peripheral supply current draw has a direct
impact on other nodes in the system. It is important to stay
within the thermal package limits and not exceed the specifica-
tion limits of IVSSN and VVIN in any of the A2B bus nodes.
LVDS Transmitter and Receiver Idle Current
The idle current, ITRXVDD_IDLE, depends on ITXVDD and IRXVDD at
0% activity level and A2B bus idle time.
Digital Logic Supply Current
The digital logic supply current IDVDD is a combination of static
current consumption and digital TX/RX current.
• B transceiver idle current. B Transceiver IBTRXVDD_IDLE
LVDS current results from B transceiver idle time.
A2B Bus TX/RX Current
The level of A2B bus activity directly influences current con-
sumption on both the LVDS transceivers related to A2B
transmitter and receiver processing.
• A transceiver idle current. A Transceiver IATRXVDD_IDLE
LVDS current results from A transceiver idle time.
• B transceiver idle time. B transceiver idle time is the time
when both the TX and RX of the B transceiver are idle.
The idle time of the B transceiver is derived by eliminating
the following activity levels from the B transceiver frame
cycle:
LVDS Transmitter and Receiver Supply Currents
The current ITRXVDD depends on ITXVDD and IRXVDD at 100% activ-
ity level and A2B bus activity:
• B transceiver downstream activity level of the current
node.
• Downstream LVDS transceiver current
• B transceiver IBTXVDD LVDS TX current results from
downstream TX activity level of the current node.
• A transceiver upstream activity level of the next in line
node.
• A transceiver IARXVDD LVDS RX current results from
downstream activity level of the previous node.
• A transceiver idle time is the time when both the TX and
RX of the A transceiver are idle.
• Upstream LVDS transceiver current
The idle time of the A transceiver is derived by eliminating
the following activity from the A transceiver frame cycle:
• A transceiver IATXVDD LVDS TX current results from
A side upstream activity level of the current node.
• A transceiver upstream activity level of the current
node.
• B transceiver IBRXVDD LVDS RX current results from
upstream activity level of the next in line node.
• B transceiver downstream activity level of previous
node.
Downstream/Upstream Activity Level
The sum of the LVDS transceiver currents is
The activity level for downstream data of TRX B is determined
by the following:
• Header bits for downstream. A2B systems use 64 down-
stream header bits referred to as a synchronization control
frame (SCF).
I
I
TRXVDD = IBRXVDD + IBTXVDD + IARXVDD + IATXVDD +
BTRXVDD_IDLE + IATRXVDD_IDLE
VREG1 AND VREG2 OUTPUT CURRENTS
Voltage regulator output currents are governed by the following
equations:
• The number of downstream data bits transmitted in
a node = the number of downstream transmitted slots ×
(bits per slot + parity bit) where the parity bit = 1. The
number of downstream transmitted slots does not include
the locally consumed slots.
I
VOUT2 is the current from VVOUT2 which is the sum of the LVDS
transmitter and receiver supply currents, peripheral supply cur-
rents, and I/O current.
I
VOUT2 = ITRXVDD + IIOVDD+ IVEXT2
IVOUT1 is the current from the VOUT1 pin which is the sum of PLL
supply current, IPLLVDD, digital logic supply current IDVDD
peripheral supply current, IVEXT1, and I2S/TDM/PDM I/O cur-
rent IIOVDD
VOUT1 = IPLLVDD + IVEXT1 + IDVDD + IIOVDD
• B side downstream transmitter activity level of a node.
(SCF bits + number of downstream transmitted data bits) ÷
1024.
,
The activity level for upstream data of TRX A is determined by
the following:
.
I
• Header bits for upstream. (SRF bits + total number of
received downstream data bits) ÷ 1024.
IIOVDD in a slave node can be sourced by either IVOUT1 or IVOUT2
but not both, depending on whether IIOVDD is supplied from
VOUT1 or VVOUT2.
V
Rev. B
|
Page 29 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
I
V
V
VEXT2 = peripheral supply current from VVOUT2.
CURRENT AT VIN (IVIN
)
VOUT1 = output voltage from VREG1.
VOUT2 = output voltage from VREG2
The current at the VIN pin (IVIN) of the transceiver is the sum of
currents IVOUT1 and IVOUT2 and the quiescent current, shown in
Figure 34 and in the following equation:
.
RESISTANCE BETWEEN NODES
I
VIN = IVOUT1 + IVOUT2 + IVINQ
Figure 35 shows the dc model of a system with a combination of
local and bus powered A2B slaves.
The A side node current is the line bias current from an earlier
node. In a bus powered node, it is also the power supply current
and a portion of this current supplies the next in line nodes.
A voltage drop of the dc bias is observed between the A2B nodes,
due to resistance and current consumption. Table 16 lists the
causes of the dc resistance between nodes (RBETWEEN) with exam-
ple resistance values.
IA = IVIN + IB + IVREGPERI
where:
Both bias supply and return currents are subject to resistance.
Therefore, some resistance values must be doubled (for exam-
ple, wire length resistance).
IB = B side current to the next node (= IVSSN return current and
IA of the next in line node).
I
VREGPERI = peripheral current supplied from IA by extra voltage
regulator, external to the transceiver (not illustrated in Figure 35
and Figure 36).
Table 16. Breakdown/Budget of Typical DC Resistance
Between Nodes
POWER DISSIPATION
Resistance
Each Qty Total Unit
The power dissipation of the transceiver is calculated using the
following equation:
Inductor DC Resistance
0.26
4
1
1
1.04
1.05
0.11
Ω
Ω
Ω
Short Circuit Protection Resistor 1.05
Power =
VIN × VVIN + (IVSSN)2 × RVSSN – IVEXT1 × VVOUT1 – IVEXT2 × VVOUT2
Positive Bias PMOS Switch
0.11
I
On-Resistance
where:
VIN = current at VIN pin.
VIN = voltage at VIN pin.
Negative Bias Switch
1.2
1
1.2
Ω
I
On-Resistance RVSSN
V
Resistance of Connections
Total RSUM
0.01
4
0.04
Ω
Ω
I
VSSN = B side current IB to the next node and return current
N/A1 N/A1 2.39
from the next node. The next node is the node connected to the
B terminal of the current node. See Figure 35.
Wire Length Resistance of Cable 0.121
1 N/A means not applicable.
2
0.242 Ω/m
R
VSSN = internal VSSN on resistance (see Table 16).
I
VEXT1 = peripheral supply current from VVOUT1.
BUS POWER
LOCAL POWER
I
Connections
Cable
SUM
Connections
Cable
V
NODEM
V
NODEn
<V
VIN max
V
V
V
IN
IN
IN
AD2426(W)/
AD2427(W)/
AD2428(W)
V
SSN
AD2427(W)/
AD2428(W)
AD2428(W)
R8
B
A
B
A
B
A
V
V
V
SS
V
V
SSN
SS
SSN
SS
Connections
Cable
Connections
Cable
I
SUM
Figure 35. A2B DC Power Model for a System with Local and Bus Powered Slaves
Rev. B
| Page 30 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
VOLTAGE REGULATOR CURRENT IN MASTER NODE
OR LOCAL POWERED SLAVE NODE
POWER ANALYSIS OF BUS POWERED SYSTEM
Figure 36 shows the dc model for a bus powered A2B system.
The bus power, required from a local powered node (master
node) for powering all nodes in the system, is calculated using
the following equation:
Power equations in this data sheet are used for power calcula-
tions in the SigmaStudio® software. The power equations are
also available in an Excel spreadsheet, provided by technical
support upon request.
ISUM = IVIN + IVSSN + IINRUSH + IVREGPERI
where:
SUPPLY VOLTAGE
I
I
VIN is the current to VVIN of the local powered mode.
The supply voltage (VVIN) level on a bus powered transceiver is
predictable and can be calculated using the following equations
derived from Figure 36.
VSSN is the return current from next in line slave node. It is equal
to the IA current supplied to the next in line node.
I
INRUSH is the inrush current required to charge capacitors on the
For the master node, the supply voltage is calculated as,
VIN pin at power-up.
I
VREGPERI is the input current of extra VREG for peripherals (not
V
NODEM = VREGM – VDIODE3
illustrated in Figure 35 and Figure 36).
V
VIN = VREGM – VDIODE1 for master
Analog Devices recommends a minimum IINRUSH of 150 mA
to support the components shown in the reference schematics.
The selected voltage regulator must be sized to meet ISUM for the
application.
For a slave node, the supply voltage is calculated as,
V
NODE = VNODE' – IA × RBETWEEN
VIN = VNODE – VDIODE1
V
where:
I
VSSN current is below 2 mA when the next in line node is a local
VNODE' is the VNODE voltage potential of the earlier node. The ear-
lier node is the node connected to the A side transceiver of the
current node.
powered slave with a circuit-based on the Designer Reference
section. TheISUM currentin most applicationsisless than 100 mA
if the next in line node is a local powered slave node.
R
BETWEEN is the connection resistance between the current and
More current, IVSSN, is drawn if the next in line node uses bus
power.The IVSSN maximum specification limits the bus power
draw of slave nodes, especially in a line of bus powered slaves.
earlier node, described in the Resistance Between Nodes section.
V
DIODE is the voltage drop of the Shottkey reverse polarity pro-
tection diode.
POWER DISSIPATION OF A2B BUS
The power dissipation of an A2B system is calculated as follows:
IA is the current that a bus powered slave node draws from an
earlier node.
Power Dissipation = ISUM × VVIN of master.
I
Connections
Cable
Connections
SUM
V
V
NODE
V
NODE0
M
NODEn
Cable
Connection
FB
D3
D1
<V
>V
V
VIN max
VIN min
V
IN
IN AD2426(W)/
AD2427(W)/
AD2428(W)
AD2427(W)/
AD2428(W)
A
B
A
B
A
B
AD2428(W)
I
VSSN
V
V
V
SS
V
V
SSN
SS
SSN
SSN
Connections
Cable
Connections
Cable
I
SUM
Figure 36. A2B Power Model for Bus Powered System
Rev. B
| Page 31 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
For a system with all in-line bus powered nodes, IA is calculated
cumulatively from the last in-line node as
THERMAL POWER
When calculating power, system designers must consider ther-
mal power. Thermal power calculations are based on the
package thermal characteristics, shown in the following
equation:
IA = IVIN + IB
where:
IA = current that a bus powered slave node draws from an earlier
node.
JA = thermal resistance
I
VIN = current at VIN pin.
(TJ – TA) ÷ power [°C/W] with airflow = 0 m/s
IB = B side return current from the next in line node. The next in
line node is the node connected to the B terminal of the current
node.
Table 17 provides the thermal power allowance example. These
values are derived from a JEDEC standard 2S2P test board. JA
values vary significantly and depend on system design and con-
ditions. For the example calculation in Table 17, the JA value
provided is determined using the JEDEC standard conditions.
REDUCING POWER CONSUMPTION
The following sections describe three methods that reduce
power consumption.
In this example (Table 17), a slave node with 292 mW of power
dissipation is used to provide the maximum estimated power.
The margin is calculated by subtracting the maximum estimated
power from the thermal power allowance.
Power-Down Mode
Any node in an A2B bus powered system can be shut down by
disconnecting the power supply in the previous slave node
(towards the master). Disconnecting a slave from the power
supply also powers down all of the following slaves (towards the
last slave).
Table 17. Thermal Power Allowance Example
Parameter
Example Value Unit
TA
105
125
20
°C
Standby Mode
The A2B bus enters standby mode by setting the
TJ
°C
Delta (TJ – TA)
°C
AD242X_DATCTL.STANDBY bit of the master. The SCF in
standby mode is 19 bits long, instead of 64 bits. In standby
mode, there is no upstream and no downstream traffic on the
A2B bus, and only a minimal SCF keeps all the slave nodes syn-
chronized. This keeps the A2B bus power in the lowest power
state while maintaining clock synchronization between nodes.
Using the equations in the Downstream/Upstream Activity
Level section, the bus activity level in standby mode is,
Example JA
31.6
633
292
341
°C/W
mW
mW
mW
Maximum Allowed Thermal Power
Maximum Estimated Power
Power Margin
• Downstream activity level = 19 ÷ 1024 = 1.9%
• Upstream activity level = 0%
The digital transceiver current, including the LVDS TX and RX
current, are subject to the activity levels. The LVDS TX and RX
current also are subject to idle current during the bus idle time.
Control Mode
In control mode, there are no data channels in a superframe.
The superframe only has the 64-bit SCF and SRF in the frame
with the control data embedded in the header bits. Therefore,
the A2B bus power is less when compared to normal mode,
which has data channels in the superframe. Using the equations
in the Downstream/Upstream Activity Level section, the bus
activity level in control mode is,
• Bus activity level downstream = 64 ÷ 1024 = 6.3%
• Bus activity level upstream = 64 ÷ 1024 = 6.3%
The LVDS TX and RX current also are subject to idle current
during the bus idle time.
Rev. B
|
Page 32 of 38
|
December 2019
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
DESIGNER REFERENCE
The following sections provide descriptions and layouts of some
VSENSE AND CONSIDERATIONS FOR DIODES
typical node configurations.
The relative difference between the voltage on the VIN pin,
An A2B-compliant master transceiver requires external compo-
nents to pass EMC and ESD tests in the automotive
environment and support full line diagnostics functionality.
Diodes are required for correct line diagnostics and to prevent
damage under line fault conditions. The master circuit must
also supply bias voltage for line diagnostics and power supply to
bus powered slaves.
An A2B-compliant, last in the line, local powered, slave node
transceiver requires external components to pass EMC and ESD
tests in the automotive environment. The circuit must allow for
full line diagnostics with properly terminated A2B bus bias and
properly terminated signals. The circuit must also electrically
isolate the local powered slave node from the earlier node to
prevent line faults triggered by the formation of ground loops
across power and communication wires.
An A2B-compliant, local powered, slave node transceiver
requires external components to pass EMC and ESD tests in the
automotive environment. The circuit must allow for full line
diagnostics with properly terminated A2B bus bias and properly
terminated signals (A-side). The local powered slave node
regenerates the bias voltage from its local supply and provides it
to the next node (B-side) for line diagnostics and as a voltage
supply for bus powered nodes. Diodes are required for correct
line diagnostics and damage prevention under line fault
conditions.
V
VIN, and the A2B bus bias voltage, VSENSE, is monitored by the
SENSE pin under steady state normal operating conditions. The
range must be within the values described in Table 18 for all line
diagnostics to function correctly.
Table 18. VVIN to VSENSE Range
Range
VIN to VSENSE
Min
Max
Unit
V
– 0.6
+0.5
V
The difference between VVIN and VSENSE is primarily influenced
by diode voltage drops and the on resistance of the PMOS.
(Contact your local Analog Devices representative for the latest
schematic circuit recommendations and bill of materials.)
Table 19 identifies which diodes cause voltage drops for each
node type.
Table 19. VVIN to VSENSEVoltage Dependencies
Node Type
VVIN to VSENSE Diode Dependencies
Master
D1, D3
D1, D3
D1
Locally Powered Slave
Bus Powered Slave
OPTIONAL ADD ON CIRCUITS
An A2B-compliant, bus powered, slave node transceiver
requires external components to pass EMC and ESD tests in the
automotive environment. The circuit must use the A2B bias (A-
side) as its low-pass filtered supply voltage (using inductors and
capacitors). A2B communication signals must be separated from
the dc content at the A-side transceiver by high-pass filtering
with ac coupling capacitors. Capacitors must also be used on the
B-side where the ac-coupled signal is merged with the recovered
bias, which is supplied through ac signal blocking inductors.
The bus powered slave node must include circuitry to forward
the recovered bias voltage to the next node and to perform line
diagnostics. A diode is required for correct line diagnostics and
damage prevention under line fault conditions.
An earlier node in the sequence can remotely power up the next
locally powered slave node over the A2B bus by switching the
bias voltage onto the A2B bus. The local powered slave node can
sense this bias voltage and use it as an enable input for power
switches or voltage regulators to awake the device from a very
low current sleep mode.
An optocoupler, shown in Figure 37, can differentiate input of
the bias voltage and ensures that the locally powered slave node
is electrically isolated. This avoids ground loops that can induce
noise and also trigger line fault detection. Current during sleep
is determined by the optocoupler transistor off current, the
resistor to ground (R12), and the power switch enable circuit.
Contact your local Analog Devices representative for the latest
schematic circuit recommendations and bill of materials for
each of these node configurations. The recommended circuit
and component selection must be followed for A2B automotive-
grade compliance.
VBAT
ABIASN
ENABLE
OPT1
R9
R12
ABIASP
Figure 37. Optional Power Supply Enable Circuit with Optocoupler
Rev. B
|
Page 33 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
• Where possible, flood unused PCB areas with connected
LAYOUT GUIDELINES
ground planes on all layers.
The transceivers are highly integrated devices, comprising both
digital sections for audio data, clocks, PLL, and analog A2B
transceiver sections. Use the following design rules to maximize
performance and signal integrity:
• Stitch ground planes at least every 5 mm.
• Do not obstruct power supply and ground return paths by
vias.
• Solder the exposed paddle underneath the transceiver
effectively to the PCB where it is locally connected to the
ground plane. Figure 38 shows transceiver foot print, rec-
ommended solder mask (matching exposed paddle), paste
mask (dividing exposed paddle), and stitching of the
ground plane.
• Use series resistors (≥33 Ω) near the source of clock and
fast data signals. Also consider footprints for small filter
capacitors for such signal traces.
• Avoid using right angle bends in signal routing. Use
rounded or 45 degree mitered bends instead.
• Use shortest possible signal path on connectors (inner row
of multirow, right angled connectors).
The solder paste under the exposed paddle is split into four
square areas, which minimizes solder wicking through
uncovered thermal vias and prevents sliding or tilting of
the chip during solder reflow. See Soldering Considerations
for Exposed-Pad Packages (EE-352), on the Analog Devices
web site. The exposed paddle is used for a thermal pathway
as well as for electrical connection.
• On multipin connectors, provide at least 3 mm spacing
around differential A2B pin pairs to ensure that A2B signal
pairs are closer to each other than to adjacent signals. The
spacing improves EMC performance.
Use low impedance static signals (ground) symmetrically
on connector pins adjacent to the A2B bus pairs when tight
spacing is required.
• Place power supply decoupling capacitors as close as possi-
ble to the transceiver chip with the smallest value capacitor
being closest to the pin.
• Route all traces as short as possible, especially the AP/AN
and BP/BN signals.
• Symmetrically route the AP/AN and BP/BN signals to sup-
press EMC. Match routing parasitic capacitance and
inductance.
• Symmetrically shield the AP/AN and BP/BN signals with
ground. Use shields that are at least 0.5 mm wide and
stitched generously with vias to the GND plane. Symmetry
is best achieved with flooded plane areas.
• Do not route switching signals or power supply traces next
to or underneath the AP/AN and BP/BN signals.
• Avoid using trace stubs, especially if they create an asym-
metry on the AP/AN and BP/BN signals. Symmetrically
route into and out of pads rather than branch out.
• Differential impedance trace of the AP/AN and BP/BN sig-
nals should be 100 Ω 10% (10 MHz to 100 MHz) on both
sides of the common-mode choke.
• Avoid unnecessary layer transitions for the AP/AN and
BP/BN signals. Match necessary layer transitions for differ-
ential signals.
• Use an impedance of 50 Ω 10% to ground on all traces.
• Magnetically separate common-mode chokes from each
other by at least 2 mm.
• Do not route ground or other signals on any layer under-
neath the common-mode chokes. Extend this exclusion at
least 2 mm from between the pads.
• For shielded wires, connect the shield to the local ground.
• Place one side of the inductors in the signal path and bridge
dc signals to the power and ground nets.
• Place termination resistors symmetrically and close to the
common-mode chokes.
Rev. B
|
Page 34 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
5.0 mm
0.4 mm
EPAD Pastemask Areas
0.5 mm
4 × 1.5 mm × 1.5 mm
Pad Pitch
EPAD 3.6 mm × 3.6 mm
Soldermask Opening
0.0508 mm larger than pads where
clearance permits, else 0.0254 mm
Pad 0.304 mm × 0.889 mm
1.5 mm
Thermal Vias
0.254 mm drill
0.5334 mm
Pads preferably tented/plugged
and no relief to plane layers
1.5 mm
0.7 mm
5.7 mm
Figure 38. Transceiver Footprint
Rev. B
| Page 35 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
OUTLINE DIMENSIONS
Figure 39 shows the outline dimensions for the 32-Lead
LFCSP_SS (CS-32-2).
Figure 40 shows the outline dimensions for the 32-Lead
LFCSP (CP-32-12).
DETAIL A
(JEDEC 95)
5.10
0.30
0.25
0.20
5.00 SQ
4.90
PIN 1
PIN 1
INDICATOR
INDICATOR AREA OPTIONS
(SEE DETAIL A)
32
25
24
1
0.50
BSC
3.70
3.60 SQ
3.50
EXPOSED
PAD
8
17
16
9
0.20 MIN
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
0.075~0.150
SEATING
(Step dimension)
PLANE
0.203 REF
Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_SS]
5 mm x 5 mm Body, With Side Solderable Leads
(CS-32-2)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
25
32
INDICATOR AREA OPTIONS
(SEE DETAIL A)
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.20 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm x 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
Rev. B
| Page 36 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
AUTOMOTIVE PRODUCTS
The AD2420W/AD2426W/AD2427W/AD2428W/AD2429W
models are available with controlled manufacturing to support
the quality and reliability requirements of automotive applica-
tions. Note that these automotive models may have
specifications that differ from the nonautomotive models;
therefore, designers should review the Specifications section of
this data sheet carefully. Only the automotive grade products
shown in Table 20 are available for use in automotive applica-
tions. Contact your local Analog Devices account representative
for specific product ordering information and to obtain the spe-
cific Automotive Reliability reports for these models.
Table 20. Automotive Products
Model1, 2, 3, 4
Temperature Range5
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Description
Package Option
AD2420WCCPZxx
AD2420WCCPZxx-RL
AD2426WCCSZ
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP_SS]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
CP-32-12
CP-32-12
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CS-32-2
CP-32-12
CP-32-12
AD2426WCCSZ-RL
AD2426WCCSZxx
AD2426WCCSZxx-RL
AD2427WCCSZ
AD2427WCCSZ-RL
AD2427WCCSZxx
AD2427WCCSZxx-RL
AD2428WCCSZ
AD2428WCCSZ-RL
AD2428WCCSZxx
AD2428WCCSZxx-RL
AD2429WCCPZxx
AD2429WCCPZxx-RL
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 RL = Supplied on Tape and Reel.
4 For model numbers ending in xx or xx-RL, xx denotes the die revision.
5 Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (TJ)
specification which is the only temperature specification.
Rev. B
| Page 37 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
ORDERING GUIDE
Model1
Temperature Range2
0°C to +70°C
Description
Package Option
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
CP-32-12
AD2420KCPZ
AD2420BCPZ
AD2426KCPZ
AD2426BCPZ
AD2427KCPZ
AD2427BCPZ
AD2428KCPZ
AD2428BCPZ
AD2429KCPZ
AD2429BCPZ
1 Z = RoHS Compliant Part.
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
32-Lead Frame Chip Scale Package [LFCSP]
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (TJ)
specification which is the only temperature specification.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16813-0-1/20(B)
Rev. B
| Page 38 of 38 | January 2020
相关型号:
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