AD1868NZ [ADI]
IC DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter;
| 型号： | AD1868NZ |
| 厂家： | 
ADI |
| 描述： | IC DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter |
| 文件： | 总12页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply
Dual 18-Bit Audio DAC
a
AD1868*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Dual Serial Input, Voltage Output DACs
Single +5 V Supply
0.004% THD+N (typ)
AD1868
18-BIT
DAC
V
V
L
L
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Low Pow er: 50 m W (typ)
108 dB Channel Separation (m in)
Operates at 8
؋
Oversam pling 16-Pin Plastic DIP or SOIC Package
–
+
V
18-BIT
SERIAL
REGISTER
LL
DL
S
V
L
O
V
APPLICATIONS
REF
NRL
CK
Portable Com pact Disc Players
Portable DAT Players and Recorders
Autom otive Com pact Disc Players
Autom otive DAT Players
AGND
NRR
DR
18-BIT
SERIAL
REGISTER
V
REF
LR
Multim edia Workstations
+
–
V
R
DGND
O
18-BIT
DAC
V
V
R
S
B
P RO D UCT D ESCRIP TIO N
T he AD1868 is a complete dual 18-bit DAC offering excellent
performance while requiring a single +5 V power supply. It is
fabricated on Analog Devices’ ABCMOS wafer fabrication pro-
cess. T he monolithic chip includes CMOS logic elements, bipo-
lar and MOS linear elements, and laser-trimmed thin-film
resistor elements. Careful design and layout techniques have re-
sulted in low distortion, low noise, high channel separation, and
low power dissipation.
T he AD1868 operates on +5 V power supplies. T he digital sup-
ply, VL, can be separated from the analog supply, VS, for re-
duced digital feedthrough. Separate analog and digital ground
pins are also provided. In systems employing a single +5 volt
power supply, VL and VS should be connected together. In bat-
tery operated systems, operation will continue even with reduced
supply voltage. T ypically, the AD1868 dissipates 50 mW.
T he DACs on the AD1868 chip employ a partially segmented
architecture. T he first three MSBs of each DAC are segmented
into seven elements. T he 15 LSBs are produced using standard
R-2R techniques. T he segments and R-2R resistors are laser
trimmed to provide extremely low total harmonic distortion.
T he AD1868 requires no deglitcher or trimming circuitry. Low
noise is achieved through the use of two noise-reduction capacitors.
T he AD1868 is packaged in either a 16-pin plastic DIP or a 16-
pin plastic SOIC package. Operation is guaranteed over the tem-
perature range of –35°C to +85°C and over the voltage supply
range of 4.75 V to 5.25 V.
P RO D UCT H IGH LIGH TS
1. Single-supply operation @ +5 V.
Each DAC is equipped with a high performance output ampli-
fier. T hese amplifiers achieve fast settling and high slew rate,
producing ±1 V signals at load currents up to ±1 mA. T he
buffered output signal range is 1.5 V to 3.5 V. Reference volt-
ages of 2.5 V are provided, eliminating the need for “False
Ground” networks.
2. 50 mW power dissipation (typical).
3. T HD+N is 0.004% (typical).
4. Signal-to-Noise Ratio is 97.5 dB (typical).
5. 108 dB channel separation (minimum).
6. Compatible with all digital filter chips.
7. 16-pin DIP and 16-pin SOIC packages.
8. No deglitcher required.
A versatile digital interface allows the AD1868 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 13.5 MHz. T his allows for
operation at 2×, 4×, 8×, or 16× the sampling frequency for each
channel. T he digital input pins of the AD1868 are T T L and
+5 V CMOS compatible.
9. No external adjustments required.
*P r otected by U.S. P atent Num ber s: 3,961,326; 4,141,004; 4,349,811;
4,857,862; and patents pending.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(typical at T = +25؇C and +5 V supplies unless otherwise noted)
AD1868–SPECIFICATIONS
A
Min
2.4
Typ
Max
Units
RESOLUT ION
18
Bit
DIGIT AL INPUT S
VIH
V
V
VIL
0.8
IIH, VIH = VL
IIL, VIL = DGND
Maximum Clock Input Frequency
1.0
1.0
µA
µA
MHz
13.5
ACCURACY
Gain Error
Gain Matching
Midscale Error
Midscale Error Matching
Gain Linearity Error
±1
±1
±15
±10
±3
% of FSR
% of FSR
mV
mV
dB
DRIFT (0°C to +70°C)
Gain Drift
Midscale Drift
±100
±100
ppm/°C
µV/°C
T OT AL HARMONIC DIST ORT ION + NOISE
0 dB, 990.5 Hz
AD1868N
AD1868N-J
AD1868N
AD1868N-J
AD1868N
AD1868N-J
0.004
0.004
0.020
0.020
2.0
0.008
0.006
0.08
0.08
5.0
%
%
%
%
%
%
–20 dB, 990.5 Hz
–60 dB, 990.5 Hz
2.0
5.0
CHANNEL SEPARAT ION 1 kHz, 0 dB
SIGNAL-T O-NOISE RAT IO (with A-Weight Filter)
D-RANGE (with A-Weight Filter)
108
95
NIL*
97.5
92
dB
dB
dB
86
OUT PUT
Voltage Output Pins (VOL, VOR)
Output Range (±3%)
Output Impedance
Load Current
±1
0.1
±1
V
Ω
mA
Bias Voltage Pins (VBL, VBR)
Output Voltage
Output Impedance
+2.5
350
V
Ω
POWER SUPPLY
Specification, VL and VS
Operation, VL and VS
+I, VL and VS = 5 V
4.75
3.5
5
5.25
5.25
14
V
V
mA
10
50
POWER DISSIPAT ION
70
mW
T EMPERAT URE RANGE
Specification
Operation
0
–35
–60
25
70
85
100
°C
°C
°C
Storage
*Above 115 dB.
Specifications subject to change without notice.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSO LUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2–
REV. A
AD1868
Typical Performance of the AD1868
–30
150
140
130
120
110
100
–60dB
–40
–50
–60
–70
–80
–90
–100
–20dB
0dB
3
4
0.5
2.5 4.5
6.5
8.5 10.5 12.5 14.5 16.5 18.5 20.5
FREQUENCY – kHz
10
10
FREQUENCY – Hz
Figure 2. Channel Separation vs. Frequency
Figure 1. THD+N vs. Frequency
8
–20
–30
–40
–50
–60
–60dB
6
0°C
4
2
25°C
0
–20dB
0dB
–2
–70
–80
–90
70°C
–4
–6
–100
–40
INPUT AMPLITUDE – dB
–10
0
–80
–60
–20
4.4
4.6
4.8
5.0
5.2
5.4
VOLTAGE SUPPLY
Figure 4. Gain Linearity Error vs. Input Am plitude
Figure 3. THD+N vs. Supply Voltage
90
–20
–40
–
60dB
80
70
60
50
40
–60
–
20dB
0dB
–80
–100
2
3
4
5
–50
–30 –10 10
30
50
70
90
110 130 140
10
10
10
10
TEMPERATURE – °C
SUPPLY MODULATION FREQUENCY – Hz
Figure 5. THD+N vs. Tem perature
Figure 6. Power Supply Rejection Ratio vs. Frequency
REV. A
–3–
AD1868
P IN CO NFIGURATIO N
P IN D ESIGNATIO NS
Digital Supply (+5 Volts)
11
12
13
14
15
16
17
18
19
10
11
12
13
14
15
16
VL
V
16
L
L
V
B
L
1
2
3
4
5
6
7
8
LL
Left Channel Latch Enable
Left Channel Data Input
Clock Input
V
DL
15
14
LL
DL
S
CK
V
O
DR
Right Channel Data Input
Right Channel Latch Enable
Digital Common
AD1868
13 NRL
CK
DR
LR
TOP VIEW
(Not To Scale)
AGND
12
11
10
9
DGND
VBR
VS
Right Channel Bias
LR
NRR
Analog Supply (+5 Volts)
Right Channel Output
Right Channel Noise Reduction
Analog Common
V
R
O
DGND
VOR
NRR
AGND
NRL
VOL
VS
V
V
R
S
B
Left Channel Noise Reduction
Left Channel Output
Analog Supply (+5 Volts)
Left Channel Bias
D EFINITIO N O F SP ECIFICATIO NS
Total H ar m onic D istor tion + Noise
T otal harmonic distortion plus noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the am-
plitudes of the harmonics and noise to the amplitude of the fun-
damental input frequency. It is usually expressed in percent (%)
or decibels (dB).
VBL
FUNCTIO NAL D ESCRIP TIO N
T he AD1868 is a complete, voltage output dual 18-bit digital
audio DAC which operates with a single +5 volt supply. As
shown in the block diagram, each channel contains a voltage
reference, an 18-bit DAC, an output amplifier, an 18-bit input
latch, and an 18-bit serial-to-parallel input register.
D -Range D istor tion
D-range distortion is the ratio of the amplitude of the signal at
an amplitude of –60 dB to the amplitude of the distortion plus
noise. In this case, an A-weight filter is used. T he value speci-
fied for D-range performance is the ratio measured plus 60 dB.
T he voltage reference section provides a reference voltage and a
false ground voltage for each channel. T he low noise bandgap
circuits produce reference voltages that are unaffected by
changes in temperature, time, and power supply.
Signal-to-Noise Ratio
T he signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale output is present to the ampli-
tude of the output with no signal present. It is expressed in
decibels (dB) and measured using an A-weight filter.
T he output amplifier uses both MOS and bipolar devices and
incorporates an NPN class-A output stage. It is designed to pro-
duce high slew rate, low noise, low distortion, and optimal fre-
quency response.
Gain Linear ity
Gain linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a lower level. A per-
fect D/A converter exhibits no difference between the ideal and
actual amplitudes. Gain linearity is expressed in decibels (dB).
Each 18-bit DAC uses a combination of segmented decoder
and R-2R architecture to achieve good integral and differential
linearity. T he resistors which form the ladder structure are fab-
ricated with silicon-chromium thin film. Laser trimming of
these resistors further reduces linearity error, resulting in low
output distortion.
Midscale Er r or
T he input registers are fabricated with CMOS logic gates.
T hese gates allow fast switching speeds and low power con-
sumption, contributing to the fast digital timing, low glitch, and
low power dissipation of the AD1868.
Midscale error is the difference between the analog output and
the bias when the twos complement input code representing
midscale is loaded in the input register. Midscale error is ex-
pressed in mV.
O RD ERING GUID E
TH D + N
@ FS
P ackage
O ption*
Model
SNR
95 dB
95 dB
95 dB
95 dB
AD1868N
AD1868R
AD1868N-J
AD1868R-J
0.008%
0.008%
0.006%
0.006%
N-16
R-16
N-16
R-16
*N = Plastic DIP; R = SOIC.
REV. A
–4–
AD1868
DAC, the AD1868 can continue to function at supply voltages
as low as 3.5 V. Because of its unique design, the power require-
ments of the AD1868 diminish as the battery voltage drops, fur-
ther extending the operating time of the system.
AD1868
18-BIT
DAC
V
V
V
L
L
L
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
–
+
18-BIT
SERIAL
REGISTER
LL
DL
S
POWER
SUPPLY
V
O
V
REF
NRL
AD1868
CK
V
V
V
L
16
B
1
2
L
0.1µF
V
AGND
NRR
LL
DL
CK
DR
15
14
S
18-BIT
SERIAL
REGISTER
L
O
3
4
4.7µF
4.7µF
V
REF
LR
NRL 13
0.1µF
12
5
6
DR
AGND
+
–
V
R
DGND
O
18-BIT
DAC
NRR 11
LR
V
R
10
9
DGND
O
7
8
V
V
R
S
B
V
S
V
R
B
Functional Block Diagram
Figure 7. Recom m ended Circuit Schem atic
ANALO G CIRCUIT CO NSID ERATIO NS
GRO UND ING RECO MMEND ATIO NS
NO ISE RED UCTIO N CAP ACITO RS
T he AD1868 has two ground pins, designated as AGND (Pin
12) and DGND (Pin 7). T he analog ground, AGND, serves as
the “high quality” reference ground for analog signals and as a
return path for the supply current from the analog portion of the
device. T he system analog common should be located as close
as possible to Pin 12 to minimize any voltage drop which may
develop between these two points, although the internal circuit
is designed to minimize signal dependence of the analog return
current.
T he AD1868 has two noise reduction pins designated as NRL
(Pin 13) and NRR (Pin 11). It is recommended that external
noise reduction capacitors be connected from these pins to
AGND to reduce the output noise contributed by the voltage
reference circuitry. As shown in Figure 7, each of these pins
should be bypassed to AGND with a 4.7 µF or larger capacitor.
T he connections between the capacitors, package pins and
AGND should be as short as possible to achieve the lowest
noise.
T he digital ground, DGND, returns ground current from the
digital logic portion of the device. T his pin should be connected
to the digital common node in the system. As shown in Figure
7, the analog and digital grounds should be joined at one point
in the system. When these two grounds are remotely connected
such as at the power supply ground, care should be taken to
minimize the voltage difference between the DGND and AGND
pins in order to ensure the specified performance.
USING VBL AND VBR
T he AD1868 has two bias voltage reference pins, designated as
VBR (Pin 8) and VBL (Pin 16). T hese pins supply a dc reference
voltage equal to the center of the output voltage swing. T hese
bias voltages replace “False Ground” networks previously required
in single-supply audio systems. At the same time, they allow dc-
coupled systems, improving audio performance.
Figure 8a illustrates the traditional approach used to generate
False Ground voltages in single-supply audio systems. T his cir-
cuit requires additional power and circuit board space.
P O WER SUP P LIES AND D ECO UP LING
T he AD1868 has three power supply input pins. VS (Pins 9 and
15) provides the supply voltages which operate the analog por-
tion of the device including the 18-bit DACs, the voltage refer-
ences, and the output amplifiers. T he VS supplies are designed
to operate with a +5 V supply. T hese pins should be decoupled
to analog common using a 0.1 µF capacitor. Good engineering
practice suggests that the bypass capacitors be placed as close as
possible to the package pins. T his minimizes the inherent induc-
tive effects of printed circuit board traces.
–V
+V
S
1
2
3
16
16-BIT
LATCH
S
16-BIT
DAC
DGND
15 TRIM
MSB
+V
L
SERIAL
INPUT
14
ADJ
REGISTER
I
I
NC
CLK
LE
4
5
6
7
13
12
OUT
OUT
VL (Pin 1) operates the digital portions of the chip including the
input shift registers and the input latching circuitry. VL is also
designed to operate with a +5 V supply. T his pin should be by-
passed to digital common using a 0.1 µF capacitor, again placed
as close as possible to the package pin. Figure 7 illustrates the cor-
rect connection of the digital and analog supply bypass capacitors.
AGND
CONTROL
LOGIC
11 SJ
R
DATA
10
9
F
V
NC
8
OUT
An important feature of the AD1868 audio DAC is its ability to
operate at reduced power supply voltages. T his feature is very
important in portable battery operated systems. As the batteries
discharge, the supply voltage drops. Unlike any other audio
AD1851
NC = NO CONNECT
Figure 8a. Schem atic Using False Ground
REV. A
–5–
AD1868
Figure 1 illustrates the typical T HD+N versus frequency perfor-
mance of the AD1868. It is evident that the T HD+N perfor-
mance of the AD1868 remains stable at all three levels through
a wide range of frequencies. A load impedance of at least 2 kΩ is
recommended for best T HD+N performance.
+
5V
AD1868
V
L
O
16
15
14
13
12
11
10
V
1
2
V
L
B
L
V
LL
DL
S
V
L
O
3
4
Analog Devices tests and grades all AD1868s on the basis of
T HD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the
DAC at 352.8 kHz (8× FS). T he test waveform is a 990.5 Hz
sine wave with 0 dB, –20 dB, and –60 dB amplitudes. A 4096-
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, and D-range. No deglitchers or external
adjustments are used.
NRL
CK
DR
5
6
7
8
AGND
LR
NRR
V
R
O
DGND
+
5V
V
S
9
V
R
B
V
R
O
D IGITAL CIRCUIT CO NSID ERATIO NS
INP UT D ATA
Figure 8b. Circuitry Using Voltage Biases
T he AD1868 eliminates the need for “False Ground” circuitry.
VBR and VBL generate the required bias voltages previously
generated by the “False Ground.” As shown in Figure 8b, VBR
and VBL may be used as the reference point in each output
channel. T his permits a dc-coupled output signal path. T his
eliminates ac-coupling capacitors and improves low frequency
performance. It should be noted that these bias outputs have
relatively high output impedance and will not drive output
currents larger than 100 µA without degrading the specified
performance.
T he AD1868 digital input port employs five signals: Data Left
(DL), Data Right (DR), Latch Left (LL), Latch Right (LR) and
Clock (CLK). DL and DR are the serial inputs for the left and
right DACs, respectively. Input data bits are clocked into the in-
put register on the rising edge of CLK. T he falling edges of LL
and LR cause the last 18 bits which were clocked into the serial
registers to be shifted into the DACs, thereby updating the re-
spective DAC outputs. For systems using only a single latch sig-
nal, LL and LR may be connected together. For systems using
only one DAT A signal, DR and DL may be connected together.
Data is transmitted to the AD1868 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Left and right channels share the Clock (CLK) signal.
D ISTO RTIO N P ERFO RMANCE AND TESTING
T he T HD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. T herefore, the T HD+N specification
provides a direct method to classify and choose an audio DAC
for a desired level of performance.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1868.
CLK
DL
DR
MSB
MSB
LSB
LSB
LL
LR
Figure 9. Control Signals
REV. A
–6–
AD1868
TIMING
AD1868 drops. T his extends the usable battery life. Finally, as
the battery supply voltage drops, the bias voltages and signal
swings also drop, preventing signal clipping and abrupt degra-
dation of distortion. Figure 3 illustrates that T HD+N perfor-
mance of the AD1868 remains constant through a wide range
of supply voltages.
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1868 are T T L and 5 V CMOS
compatible.
T he maximum clock rate of the AD1868 is specified to be at
least 13.5 MHz. T his clock rate allows data transfer rates of 2×,
4×, 8×, and 16× FS (where FS equals 44.1 kHz). T he applica-
tions section of this data sheet contains additional guidelines for
using the AD1868.
Automotive equipment rely on components which are able to
consistently perform in a wide range of temperatures. In addi-
tion, due to the limited space available in automotive applica-
tions, small size is essential. T he AD1868 is able to satisfy both
of these requirements. T he device has guaranteed specified per-
formance between 0°C and +70°C, and the 16-pin DIP or 16-
pin SOIC package is particularly attractive where overall size is
important.
> 74./ ns
>30ns
>30ns
CLK
>15ns
>40ns
>60ns
>40ns
LATCH
Since the AD1868 provides dc bias voltages, the entire signal
chain can be dc-coupled. T his eliminate ac-coupling capacitors
from the signal path, improving low frequency performance and
lowering system cost and size.
ENABLE (LE)
>30ns
>10ns
INTERNAL DAC INPUT REGISTER
>10ns
UPDATED WITH 18 MOST RECENT BITS
MSB
1st BIT
LSB
2nd BIT
NEXT
WORD
DATA
(18th BIT)
In summary, the AD1868 is an excellent choice for battery op-
erated portable or automotive digital audio systems. In the fol-
lowing sections, some examples of high performance audio
applications featuring the AD1868 are described.
BITS CLOCKED
TO SHIFT REGISTER
Figure 10. Input Signal Tim ing
AD 1868 with Sony CXD 2550P D igital Filter
AP P LICATIO NS O F TH E AD 1868
Figure 11 illustrates an 18-bit CD player design incorporating
an AD1868 DAC, a Sony CXD2550P digital filter and 2-pole
antialias filters. T his high performance, single supply design op-
erates at 8× FS and is suitable for portable and automotive ap-
plications. In this design, the CXD2550P filter transmits left
and right channel digital data to the AD1868. T he left and
right latch signals, LL and LR, are both provided by the word
clock signal (LRCKO) of the digital filter. T he digital data is
converted to low distortion output voltages by the output
amplifiers on the AD1868. Also, no deglitching circuitry or
external adjustments are required. Bypass capacitors, noise
reduction capacitors and the antialias filter details are omitted
for clarity.
T he AD1868 is a high performance audio DAC specifically de-
signed for portable and automotive digital audio applications.
T hese market segments have technical requirements fundamen-
tally different than those found in the high-end or home-use
market segments. Portable equipment must rely on components
which require low amounts of power to offer reasonable playing
times. Also, battery voltages drop as the end of the discharge
cycle is approached. T he AD1868’s ability to operate from a
single +5 V supply makes it a good choice for battery-operated
gear. As the battery voltage drops, the power dissipation of the
+5V POWER
SUPPLY
LEFT
AD1868
CXD2550P
CHANNEL
OUTPUT
1
2
3
4
5
6
7
8
9
16
15
14
13
12
11
TEST
V
L
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
SLOT
LRCK0
DATAL
DATAR
V
L
B
V
O
8Fs/4Fs
1
2
3
4
V
8
RIGHT
LL
DL
CK
DR
LR
S
S
CHANNEL
OUTPUT
V
L
7
6
5
NRL
AGND
NRR
V
V
AGND
DD
SS
BCKO
V
R
10
9
DGND
O
V
R
V
B
S
INIT
Figure 11. AD1868 with Sony CXD2550P Digital Filter
REV. A
–7–
AD1868
AD D ITIO NAL AP P LICATIO NS
Figures 12, 13, and 14 show connection diagrams for the
AD1868 with popular digital filter chips from NPC and
Yamaha. Each application operates at 8× FS operation. Please
refer to the appropriate sections of this data sheet for additional
information.
In addition to CD player designs, the AD1868 is suitable for
similar applications such as DAT , portable musical instru-
ments, Laptop and Notebook personal computers, and PC au-
dio I/O boards. T he circuit techniques illustrated are directly
applicable in those applications.
+5V POWER
SUPPLY
AD1868
SM5813
28
V
V
L
16
1
V
1
2
B
L
LEFT
CHANNEL
OUTPUT
LOW
PASS
FILTER
V
LL
DL
27
26
2
3
15
14
S
L
3
4
BCKO
WCKO
O
25
24
4
5
13
12
NRL
CK
DR
LR
AGND
5
6
DOL
DOR
23
22
6
7
11
10
NRR
V
7
DGND
V
R
DD
O
LOW
PASS
FILTER
RIGHT
CHANNEL
OUTPUT
V
2
8
V
S
21
20
19
9
8
9
V
1
V R
B
SS
SS
10
18
11
12
17
16
15
OW18
OW20
COB
13
14
Figure 12. AD1868 with NPC SM5813 Digital Filter
+5V POWER
SUPPLY
SM5818AP
AD1868
V
1
1
V
V
L
DD
16
15
V
16
B
L
LEFT
CHANNEL
OUTPUT
LOW
PASS
FILTER
2
3
4
2
3
V
S
LL
DL
15
14
BCKO
WDCO
L
14
O
4
13
12
13
12
CK
DR
NRL
AGND
NRR
5
6
5
6
DOR
DOL
11
10
9
11
LR
7
8
7
8
V
R
O
10
9
DGND
RIGHT
CHANNEL
OUTPUT
LOW
PASS
FILTER
V
V R
B
V
SS
S
Figure 13. AD1868 with NPC SM5818AP Digital Filter
REV. A
–8–
AD1868
+5V POWER
SUPPLY
YM3434
AD1868
16
V
V
L
B
1
2
1
16
L
LOW
PASS
FILTER
LEFT
CHANNEL
OUTPUT
V
15
14
2
3
15
14
LL
DL
16/18
ST
S
3
V
L
O
V
4
5
13
12
4
5
13
12
NRL
AGND
NRR
SS
V
2
CK
DR
DD
BCO
LR
6
7
8
6
7
8
11
10
11
10
WCO
DRO
V
R
DGND
O
LOW
PASS
FILTER
RIGHT
CHANNEL
OUTPUT
V
1
9
V
R
V
9
DD
DLO
B
S
Figure 14. AD1868 with Yam aha YM3434 Digital Filter
O TH ER D IGITAL AUD IO CO MP O NENTS AVAILABLE FRO M ANALO G D EVICES
+V
–V
–V
S
+V
S
16
S
1
2
3
18-BIT
LATCH
1
2
3
16
S
18-BIT
DAC
16-BIT
DAC
16-BIT
LATCH
DGND
15 TRIM
MSB
DGND
15 TRIM
MSB
14
+V
L
SERIAL
INPUT
REGISTER
+V
L
14
SERIAL
INPUT
REGISTER
ADJ
ADJ
I
13
I
NC
CLK
LE
I
4
5
6
7
I
OUT
NC
CLK
LE
OUT
4
5
6
7
13
12
OUT
OUT
AGND
12
AGND
CONTROL
LOGIC
CONTROL
LOGIC
11 SJ
11 SJ
R
R
DATA
10
DATA
10
9
F
F
V
–V
L
–V
L
8
9
OUT
V
8
OUT
AD1860
AD1856
NC = NO CONNECT
NC = NO CONNECT
AD 1860 18-Bit Audio D AC
AD 1856 16-Bit Audio D AC
Complete, No External Components Required
102 dB SNR Minimum
Complete, No External Components Required
16-Pin DIP or SOIC Package
Standard Pinout
16-Pin DIP or SOIC Package
Standard Pinout
Low Cost
REV. A
–9–
AD1868
–V
S
+V
S
–V
+V
16
S
16
1
1
2
3
S
16-BIT
LATCH
18-BIT
LATCH
16-BIT
DAC
18-BIT
DAC
DGND
2
3
15 TRIM
MSB
DGND
15 TRIM
MSB
+V
L
SERIAL
INPUT
+V
L
SERIAL
INPUT
14
14
ADJ
ADJ
REGISTER
REGISTER
I
I
I
NC
CLK
LE
4
5
6
7
13
NC
CLK
LE
I
OUT
4
5
6
7
13
12
OUT
OUT
OUT
AGND
12
AGND
CONTROL
LOGIC
CONTROL
LOGIC
11 SJ
11 SJ
R
DATA
10
F
R
DATA
NC
10
F
V
V
8
9
NC
OUT
8
9
OUT
AD1851
AD1861
NC = NO CONNECT
NC = NO CONNECT
AD 1851 16-Bit P CM Audio D AC
107 dB SNR Minimum
16 × FS Capability
AD 1861 18-Bit P CM Audio D AC
107 dB SNR Minimum
16 × FS Capability
±5 V Supply
±5 V Supply
+V
+V
S
–V
S
–V
1
24
23
1
24
23
S
S
AD1864
AD1865
TRIM
TRIM
TRIM
MSB
2
3
4
TRIM
MSB
2
3
4
REFERENCE
REFERENCE
22 MSB
I
REFERENCE
REFERENCE
22 MSB
I
I
21
20
19
18
17
OUT
OUT
I
21
20
19
18
17
OUT
OUT
5
6
7
8
AGND
SJ
AGND
SJ
5
6
7
8
AGND
SJ
AGND
SJ
R
F
R
F
R
F
R
F
–
+
–
+
V
V
–
+
OUT
OUT
–
+
V
V
OUT
OUT
+V
L
NC
9
16
15
+V
L
–V
L
9
16
15
10
DR
LR
DL
LL
18-BIT
DAC
18-BIT
LATCH
18-BIT
DAC
18-BIT
LATCH
10
DR
LR
DL
LL
18-BIT
DAC
18-BIT
LATCH
18-BIT
DAC
18-BIT
LATCH
11
12
14
13
11
12
14
13
DGND
CK
DGND
CK
NC = NO CONNECT
AD 1864 D ual 18-Bit Audio D AC
Complete, No External Components
High Performance
AD 1865 D ual 18-Bit Audio D AC
107 dB SNR Minimum
16 × FS Capability
Low Crosstalk
24-Pin DIP
T HD+N = 0.004% (typical)
T HD+N = 0.004% (typical)
±5 V Supply
REV. A
–10–
AD1868
–V
–V
VOLTAGE
REFERENCE
+V
16
1
2
S
S
NR
S
15
14
2
ADJ
3
TRIM
+V
L
4
5
6
7
NR
1
13
12
AGND
CLK
INPUT
&
DIGITAL
OFFSET
20-BIT
DAC
I
11
10
LE
OUT
R
F
DATA
–V
L
8
9
DGND
AD1862
AD 1862 20-Bit, Low Noise Audio D AC
110 dB SNR Minimum
T HD+N = 0.0019% (typical)
±1 dB Gain Linearity
16-Pin Plastic DIP
REV. A
–11–
AD1868
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N) P ackage
16
1
9
0.31
(7.87)
0.25
(6.35)
8
0.87 (22.1) MAX
0.035
(0.89)
0.18
(4.57)
MAX
0.18
(4.57)
0.125
(3.18)
MIN
0.011
(0.28)
0.3 (7.62)
0.033 (0.84)
0.1 (2.54)
0.018 (0.46)
P lastic SO IC (R) P ackage
16
9
0.419
0.299
(7.60)
(10.65)
8
1
0.413 (10.50)
0.012
(0.3)
0.104
(2.65)
0.050
(1.27)
REF
0.019 (0.49)
0.030
(0.75)
0.042 (1.07)
0.013 (0.32)
REV. A
–12–
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