AD1837AAS-REEL [ADI]
2 ADC, 8 DAC, 96 kHz, 24-Bit Codec; 2 ADC ， DAC， 8 ， 96千赫， 24位编解码器
| 型号： | AD1837AAS-REEL |
| 厂家： | 
ADI |
| 描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 文件： | 总24页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 ADC, 6 DAC,
96 kHz, 24-Bit ꢀ-ꢁ Codec
a
AD1838
FEATURES
Supports 256 ꢂ fS, 512 ꢂ fS, and 768 ꢂ fS Master
Mode Clocks
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and
Dynamic Range
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
On-Chip Volume Controls per Channel with
1024 Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-Emphasis Processing
The AD1838 is a high performance single-chip codec featuring
three stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit sigma-delta
modulator featuring Analog Devices’ patented technology,
(continued on Page 11)
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK
AVDD
PD/RST M/S
AVDD
AAUXDATA3
DLRCLK
CLOCK
CONTROL PORT
OUTLP1
OUTLN1
OUTRP1
OUTRN1
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
SERIAL DATA
I/O PORT
DBCLK
ꢀ-ꢁ
DAC
DIGITAL
FILTER
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
OUTLP2
OUTLN2
OUTRP2
OUTRN2
ꢀ-ꢁ
DAC
DIGITAL
FILTER
OUTLP3
OUTLN3
OUTRP3
OUTRN3
ꢀ-ꢁ
DAC
DIGITAL
FILTER
ADCLP
ADCLN
ꢀ-ꢁ
ADC
DIGITAL
FILTER
FILTD
FILTR
V
REF
ADCRP
ADCRN
ꢀ-ꢁ
ADC
DIGITAL
FILTER
AD1838
DGND DGND AGND AGND AGND AGND
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD1838–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD
) . . . . . . . . . . . . . . . . . . . . . . . 5.0 V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 MHz (256 ꢀ fS Mode)
DAC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0078125 kHz, 0 dBFS (Full Scale)
ADC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0078125 kHz, –1 dBFS
Input Sample Rate (fS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 kHz
Measurement Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hz to 20 kHz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 pF
Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 kΩ
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
Parameter
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
A-Weighted
Total Harmonic Distortion + Noise (THD + N)
Interchannel Isolation
Interchannel Gain Mismatch
Analog Inputs
100
101
103
105
–95
100
0.025
dB
dB
dB
dB
dB
–88.5
Differential Input Range ( Full Scale)
Common-Mode Input Volts
Input Impedance
Input Capacitance
VREF
–2.828
+2.828
V
V
kΩ
pF
V
2.25
4
15
2.25
DC Accuracy
Gain Error
Gain Drift
5
35
%
ppm/ºC
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
103
105
105
108
–95
110
dB
dB
dB
dB
–90
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
4.0
0.025
200
0.1
0.098
60
–100
0.1
%
dB
ppm/°C
Degrees
%
dB
dB
dB
De-Emphasis Gain Error
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance at Each Pin
Common-Mode Output Volts
1.0 (2.8)
180
2.25
Vrms (V p-p)
Ω
V
ADC DECIMATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
20
0.01
24
kHz
dB
kHz
dB
Stop-Band Attenuation
120
Group Delay
910
µs
REV. 0
–2–
AD1838
Parameter
Min
Typ
Max
Unit
ADC DECIMATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
40
0.01
48
120
kHz
dB
kHz
dB
Stop-Band Attenuation
Group Delay
460
µs
DAC INTERPOLATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
20
kHz
dB
0.01
Stop Band
Stop-Band Attenuation
Group Delay
24
55
kHz
dB
µs
340
DAC INTERPOLATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
37.5
89.954
kHz
dB
kHz
dB
0.01
55.034
55
Group Delay
160
µs
DAC INTERPOLATION FILTER, 192 kHz*
Pass Band
Pass-Band Ripple
kHz
dB
0.01
Stop Band
Stop-Band Attenuation
Group Delay
104.85
80
kHz
dB
µs
110
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current
2.4
V
V
V
V
0.8
ODVDD – 0.4
0.4
10
µA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD
Supply Voltage (ODVDD
Supply Current IANALOG
Supply Current IANALOG, Power-Down
Supply Current IDIGITAL
)
4.5
3.0
5.0
5.5
DVDD
95
67
72
V
V
mA
mA
mA
mA
)
84
55
64
1
Supply Current IDIGITAL, Power-Down
4
Dissipation
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
740
420
320
280
–70
–75
dB
dB
*Guaranteed by design.
Specifications subject to change without notice.
REV. 0
–3–
AD1838–SPECIFICATIONS
TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
tML
tPDR
MCLK High
MCLK Low
PD/RST Low
15
15
20
ns
ns
ns
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
tCOD
CCLK High
CCLK Low
40
40
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
15
20
25
tCOTS
DAC SERIAL PORT
Normal Mode (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
60
60
64 ꢀ fS
10
10
10
10
ns
ns
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
Packed 256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
15
15
256 ꢀ fS
10
5
10
10
ns
ns
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
ADC SERIAL PORT
Normal Mode (Master)
tABD
tALD
tABDD
ABCLK Delay
ALRCLK Delay Low
ASDATA Delay
25
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
Normal Mode (Slave)
tABH
tABL
fAB
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
60
60
64 ꢀ fS
5
ns
ns
tALS
tALH
ns
ns
To ABCLK Rising
From ABCLK Rising
15
Packed 256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
20
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
REV. 0
–4–
AD1838
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
tTBD
BCLK Delay
20
5
10
ns
ns
ns
ns
ns
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
tFSD
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
tTABD
tTDDS
tTDDH
15
15
TDM256 MODE (Slave)
fAB
BCLK Frequency
256 ꢀ fS
tTBCH
tTBCL
tTFS
BCLK High
BCLK Low
15
15
10
10
ns
ns
ns
ns
ns
ns
ns
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
tTFH
tTBDD
tTDDS
tTDDH
10
15
15
AUXILIARY INTERFACE
tAXDS
AAUXDATA Setup
10
10
15
64 ꢀ fS
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
tAXDH
tDXD
fABP
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
Slave Mode
tAXBH
tAXBL
tAXLS
tAXLH
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
15
15
10
10
ns
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
Master Mode
tAUXLRCLK
tAUXBCLK
AUXLRCLK Delay
AUXBCLK Delay
5
15
ns
ns
From AUXBCLK Falling
From MCLK Rising
Specifications subject to change without notice.
tMCLK
tMH
MCLK
tML
PD/RST
tPDR
Figure 1. MCLK and PD/RST Timing
REV. 0
–5–
AD1838
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
AVDD, DVDD, OVDD to AGND, DGND . . . –0.3 V to +6.0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . –0.3 V to ODVDD +0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD +0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C
*
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
–40
–65
+85
+150
ORDERING GUIDE
Temperature Range Package Description
–40oC to +85oC
52-Lead MQFP
Model
AD1838AS
Package Option
S-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD1838 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–6–
AD1838
PIN CONFIGURATION
48
50 49
47 46 45 44 43 42 41 40
51
52
39 DVDD
1
2
DVDD
CLATCH
CIN
38
37
36
DBCLK
DLRCLK
DAUXDATA
M/S
3
4
PD/RST
AGND
5
35
34
OUTLN1
OUTLP1
OUTRN1
OUTRP1
AGND
6
AGND
N/C
AD1838
TOP VIEW
33
32
31
7
(Not to Scale
)
8
N/C
9
N/C
10
11
12
13
30 AGND
-
AVDD
29 AVDD
OUTLN2
OUTLP2
28 OUTRP3
27 OUTRN3
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN FUNCTION DESCRIPTIONS
Input/
Pin No.
Mnemonic
Output
Description
1, 39
2
3
4
DVDD
CLATCH
CIN
PD/RST
AGND
OUTLNx
OUTLPx
OUTRNx
OUTRPx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
N/C
Digital Power Supply. Connect to digital 5 V supply.
Latch Input for Control Data
Serial Control Input
Power-Down/Reset
Analog Ground
DACx Left Channel Negative Output
DACx Left Channel Positive Output
DACx Right Channel Negative Output
DACx Right Channel Positive Output
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10 µF/100 nF.
Reference Filter Capacitor Connection. Recommended 10 µF/100 nF.
ADC Left Channel Negative Input
ADC Left Channel Positive Input
ADC Right Channel Negative Input
ADC Right Channel Positive Input
Not Connected
I
I
I
5, 10, 16, 24, 30, 34
6, 12, 25
7, 13, 26
8, 14, 27
9, 15, 28
11, 19, 29
17
18
20
21
22
O
O
O
O
I
I
I
I
23
31–33
35
M/S
I
ADC Master/Slave Select
36
37
38
DAUXDATA
DLRCLK
DBCLK
I
I/O
I/O
Auxiliary DAC Input Data
DAC LR Clock
DAC Bit Clock
40, 52
41–43
44
45
46
DGND
Digital Ground
DSDATAx
AAUXDATA3
ABCLK
ALRCLK
MCLK
I
I
I/O
I/O
I
DACx Input Data (Left and Right Channels)
Auxiliary ADC3 Digital Input
ADC Bit Clock
ADC LR Clock
Master Clock Input
47
48
49
50
51
ODVDD
ASDATA
COUT
Digital Output Driver Power Supply
ADC Serial Data Output
Output for Control Data
O
O
I
CCLK
Control Clock Input for Control Data
REV. 0
–7–
AD1838–TypicalPerformanceCharacteristics
5
0
0
–5
–50
–10
–15
–20
–25
–30
–100
–150
0
5
10
15
0
5
10
15
20
FREQUENCY – Hz
FREQUENCY – Normalized to fS
TPC 1. ADC Composite Filter Response
TPC 4. ADC High-Pass Filter Response, fS = 96 kHz
0
5
0
–5
–50
–100
–150
–10
–15
–20
–25
–30
0
50
100
kHz
150
200
0
5
10
15
20
FREQUENCY – Hz
TPC 2. ADC High-Pass Filter Response, fS = 48 kHz
TPC 5. DAC Composite Filter Response, fS = 48 kHz
0
0
–50
–100
–150
–50
–100
–150
0
0.5
1.0
1.5
2.0
0
50
100
kHz
150
200
FREQUENCY – Normalized to fS
TPC 3. ADC Composite Filter Response
(Pass Band Section)
TPC 6. DAC Composite Filter Response, fS = 96 kHz
REV. 0
–8–
TypicalPerformanceCharacteristics–AD1838
0.2
0
–50
0.1
0
–100
–150
–0.1
–0.2
0
10
20
30
40
50
0
50
100
kHz
150
200
kHz
TPC 7. DAC Composite Filter Response, fS = 192 kHz
TPC 9. DAC Composite Filter Response, fS = 96 kHz
(Pass Band Section)
0.1
0.05
0
0.1
0.05
0
–0.05
–0.1
–0.05
–0.1
0
5
10
15
20
0
20
40
60
80
100
kHz
kHz
TPC 8. DAC Composite Filter Response, fS = 48 kHz
(Pass Band Section)
TPC 10. DAC Composite Filter Response, fS = 192 kHz
(Pass Band Section)
REV. 0
–9–
AD1838
DEFINITIONS
Gain Drift
Dynamic Range
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
The ratio of a full-scale input signal to the integrated input noise in
the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic
range is measured with a –60 dB input signal and is equal to
(S/[THD + N]) +60 dB. Note that spurious harmonics are below
the noise with a –60 dB input, so the noise level establishes the
dynamic range. The dynamic range is specified with and without
an A-Weight filter applied.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel,
expressed in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins,
expressed in decibels of full scale.
Signal to (Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the pass band, expressed in decibels.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds.
More precisely, the derivative of radian phase with respect to
the radian frequency at a given frequency.
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Group Delay Variation
Pass-Band Ripple
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in microseconds.
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
GLOSSARY
The region of the frequency spectrum attenuated by the
digital decimator’s filter to the degree specified by stop-band
attenuation.
ADC–Analog-to-Digital Converter
DAC–Digital-to-Analog Converter
DSP–Digital Signal Processor
Gain Error
IMCLK–Internal Master Clock signal used to clock the ADC
and DAC engines
With identical near full-scale inputs, the ratio of actual output to
expected output, expressed as a percentage.
MCLK–External Master Clock signal applied to the AD1838
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
REV. 0
–10–
AD1838
(continued from Page 1)
Each set of differential output pins sits at a dc level of VREF and
swings 1.4 V for a 0 dB digital input signal. A single op amp
third order external low-pass filter is recommended to remove
high-frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the use
of op amps with low slew rate or low bandwidth may cause
high-frequency noise and tones to fold down into the audio
band; care should be exercised in selecting these components.
and a continuous-time voltage out analog section. Each DAC
has independent volume control and clickless mute functions.
The ADC comprises two 24-bit conversion channels with multibit
sigma-delta modulators and decimation filters.
The AD1838 also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1838 contains a flexible serial interface that allows for
glueless connection to a variety of DSP chips, AES/EBU receiv-
ers, and sample rate converters. The AD1838 can be configured
in Left-Justified, Right-Justified, I2S, or DSP-compatible serial
modes. Control of the AD1838 is achieved by means of an SPI-
compatible serial port. While the AD1838 can be operated from
a single 5 V supply, it also features a separate supply pin for its
digital interface that allows the device to be interfaced to other
devices using 3.3 V power supplies.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a two’s complement
encoded format. The word width can be selected from 16-bit,
20-bit, or 24-bit. The coding scheme is detailed in Table I.
The AD1838 is available in a 52-Lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
Table I. Coding Scheme
Code
Level
FUNCTIONAL OVERVIEW
ADCs
01111......1111
00000......0000
10000......0000
+FS
0 (Ref Level)
–FS
There are two ADC channels in the AD1838, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an oversampling
ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation).
Clock Signals
The DAC and ADC engines in the AD1838 are designed to
operate from a 24.576 MHz internal master clock (IMCLK).
This clock is used to generate 48 kHz and 96 kHz sampling on
the ADC and 48 kHz, 96 kHz and 192 kHz on the DAC,
although the 192 kHz option is only available on one DAC
pair. The stereo replicate feature can be used to copy this
DAC data to the other DACs if required.
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 Registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information
until read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description for
details of the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
To facilitate the use of the different MCLK values, the AD1838
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor of
1 (pass-through), 2 (doubling), or scaling by a factor of 2/3. The
default setting of the MCLK scaler is 2, which will generate
48 kHz sampling from a 12.288 MHz MCLK. Additional
sample rates can be achieved by changing the MCLK value.
For example, the CD standard sampling frequency of 44.1 kHz
can be achieved using an 11.2896 kHz MCLK. Figure 2 shows
the internal configuration of the clock scaler and converter engines.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1838 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1838. In most cases, this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
DACs
The AD1838 has six DAC channels arranged as three inde-
pendent stereo pairs, with six fully differential analog outputs
for improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of
the packed data modes may be used to access all six channels on a
single TDM data pin. A stereo replicate feature is included where the
DAC data sent to the first DAC pair is also sent to the other
DACs in the part. The AD1838 can accept DAC data at a sample
rate of 192 kHz on DAC 1 only. The stereo replicate feature
can then be used to copy the audio data to the other DACs.
REV. 0
–11–
AD1838
DAC ENGINE
48kHz/96kHz/192kHz
INTERPOLATION
FILTER
Σ-∆
ANALOG
OUTPUT
DAC
DAC I/P
MODULATOR
CLOCK SCALING
ꢂ 1
ꢂ 2
MCLK
IMCLK = 24.576MHz
12.288MHz
ꢂ 2/3
ADC ENGINE
48kHz/96kHz
ANALOG
INPUT
OPTIONAL
HPF
DECIMATOR/
FILTER
Σ-∆
ADC O/P
MODULATOR
Figure 2. Modulator Clocking Scheme
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
tCOTS
tCOE
tCDS tCDH
D9
D9
D8
CIN
D15
D14
D0
COUT
D8
D0
tCOD
Figure 3. Format of SPI Timing
RESET and Power-Down
parallel combination of 10 µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the FILTR pin should be limited to less than 50 µA.
PD/RST will power down the chip and set the control regis-
ters to their default settings. After PD/RST is de-asserted, an
initialization routine will run inside the AD1838 to clear all
memories to zero. This initialization lasts for approximately
20 LRCLK intervals. During this time, it is recommended that
no SPI writes occur.
Serial Control Port
The AD1838 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
DACs, and to read the ADC signal levels from the internal peak
detectors. The SPI control port is a 4-wire serial control port. The
format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to the
sample rate of the ADCs and DACs. Figure 3 shows the format
of the SPI signal.
Power Supply and Voltage Reference
The AD1838 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 µF should also be
provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP), or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data-word.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
REV. 0
–12–
AD1838
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, or Packed Mode 256. The word width
defaults to 24 bits but can be changed by reprogramming
Bits 3 and 4 in DAC Control Register 1.
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1838 to provide 8-in/8-out operation. In addition, this
mode supports glueless interface to a single SHARC DSP serial
port, allowing a SHARC DSP to access all eight channels of
analog I/O. In this special mode, many pins are redefined; see
Table II for a list of redefined pins. The auxiliary and the TDM
interfaces are independently configurable to operate as masters
or slaves. When the auxiliary interface is set as a master, by
programming the aux mode bit in ADC Control Register II, the
AUXLRCLK and AUXBCLK are generated by the AD1838.
When the auxiliary interface is set as a slave, the AUXLRCLK and
AUXBCLK need to be generated by an external ADC as shown in
Figure 13. The TDM interface can be set to operate as a master or
slave by connecting the M/S pin to DGND or ODVDD, respec-
tively. In master mode, the FSTDM and BCLK signals are outputs
and generated by the AD1838. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC. Slave
mode operation is available for 48 kHz and 96 kHz operation
(based on a 12.288 MHz or 24.576 MHz MCLK), and master
mode operation is available for 48 kHz only.
Packed Modes
The AD1838 has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256
refers to the number of BCLKs in each frame. The LRCLK is
low while data from a left channel DAC or ADC is on the data
pin, and high while data from a right channel DAC or ADC
is on the data pin. DAC data is applied on the DSDATA1
pin, and ADC data is available on the ASDATA pin.
Figures 7–10 show the timing for the packed mode. Packed Mode
is only available for 48 kHz (based on MCLK = 12.288MHz) and
when the M/S is low.
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
1 S MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 ꢂ fS.
3. BCLK FREQUENCY IS NORMALLY 64 ꢂ LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 4. Stereo Serial Modes
REV. 0
–13–
AD1838
tABH
tABP
ABCLK
tABL
tALS
tALH
ALRCLK
tADS
ASDATA
LEFT-JUSTIFIED
MODE
MSB
tADH
MSB-1
tADS
MSB
tADH
ASDATA
2
I S-JUSTIFIED
MODE
tADS
LSB
tADH
tADS
MSB
tADH
ASDATA
RIGHT-JUSTIFIED
MODE
Figure 5. ADC Serial Mode Timing
tDBH
tDBP
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
DSDATA
2
I S-JUSTIFIED
MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
DSDATA
RIGHT-JUSTIFIED
MODE
Figure 6. DAC Serial Mode Timing
REV. 0
–14–
AD1838
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1
LEFT
SLOT 5
RIGHT
ADC DATA
SLOT 2 SLOT 3 SLOT 4
SLOT 7 SLOT 8
SLOT 6
MSB
MSB–1
MSB–2
Figure 7. ADC Packed Mode 256
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3
LEFT 1 LEFT 2 LEFT 3
SLOT 5 SLOT 6 SLOT 7
RIGHT 1 RIGHT 2 RIGHT 3
DAC DATA
SLOT 4
SLOT 8
MSB
MSB–1
MSB–2
Figure 8. DAC Packed Mode 256
tABH
tABP
ABCLK
tABL
tALS
ALRCLK
ASDATA
tALH
tABDD
tADS
MSB
tADH
MSB-1
Figure 9. ADC Packed Mode Timing
tDBH
tDBP
DBCLK
tDBL
tDLS
DLRCLK
DSDATA
tDLH
tDDS
MSB
tDDH
MSB-1
Figure 10. DAC Packed Mode Timing
REV. 0
–15–
AD1838
Table II. Pin Function Changes in Auxiliary Mode
Pin Name
I2S Mode
Aux Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
I2S Data Out, Internal ADC
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
Not Connected
TDM Data Out to SHARC
TDM Data In from SHARC
AUX-I2S Data In 1 (from Ext. ADC)
AUX-I2S Data In 2 (from Ext. ADC)
AUX-I2S Data In 3 (from Ext. ADC)
TDM Frame Sync Out to SHARC (FSTDM)
TDM BCLK Out to SHARC
LRCLK for ADC
BCLK for ADC
DLRCLK (I)/AUXLRCLK(I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out. Driven by Ext. LRCLK
from ADC in slave mode. In master mode,
driven by MCLK/512.
DBCLK (I)/AUXBCLK(I/O)
DAUXDATA(O)
BCLK In/Out Internal DACs
Not Connected
AUX BCLK In/Out. Driven by Ext. BCLK from
ADC in slave mode. In master mode, driven by
MCLK/8.
AUX-I2S Data Out (to Ext. DAC)
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
CH
8TH
CH
ASDATA1
TDM (OUT)
INTERNAL
ADC L1
INTERNAL
ADC R1
AUX_ADC R3
AUX_ADC R2
AUX_ADC R4
AUX_ADC L4
AUX_ADC L2
AUX_ADC L3
ASDATA
32
MSB TDM
MSB TDM
1ST
CH
8TH
CH
DSDATA1
TDM (IN)
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
AUX DAC L4
AUX DAC R4
DSDATA1
32
AUX
2
LRCLK I S
RIGHT
LEFT
(FROM AUX ADC #1)
AUX
2
BCLK I S
(FROM AUX ADC #1)
AAUXDATA1 (IN)
(FROM AUX ADC #1)
2
2
I S – MSB LEFT
I S – MSB RIGHT
AAUXDATA2 (IN)
(FROM AUX ADC #2)
2
2
I S – MSB LEFT
I S – MSB RIGHT
AAUXDATA3 (IN)
(FROM AUX ADC #3)
2
2
I S – MSB LEFT
I S – MSB RIGHT
AUX BCLK FREQUENCY IS 64 ꢂ FRAME RATE; TDM BCLK FREQUENCY IS 256 ꢂ FRAME RATE.
Figure 11. Aux-Mode Timing
REV. 0
–16–
AD1838
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC #1
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC #1
SLAVE
ASDATA FSTDM
BCLK DSDATA1
LRCLK
BCLK
DBCLK/AUXBCLK
DAC #1
SLAVE
DLRCLK/AUXLRCLK
DAUXDATA
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
DSDATA2/AAUXDATA1
ADC #2
SLAVE
DSDATA3/AAUXDATA2
AAUXDATA3
MCLK
AD1838
MASTER
Figure 12. Aux-Mode Connection to SHARC (Master Mode)
30MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN).
SHARC
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC #1
MASTER
LRCLK
BCLK
DATA
MCLK
ADC #1
SLAVE
ASDATA FSTDM
BCLK DSDATA1
LRCLK
BCLK
DBCLK/AUXBCLK
DAC #1
SLAVE
DLRCLK/AUXLRCLK
DAUXDATA
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
DSDATA2/AAUXDATA1
ADC #2
SLAVE
DSDATA3/AAUXDATA2
AAUXDATA3
MCLK
AD1838
SLAVE
Figure 13. Aux-Mode Connection to SHARC (Slave Mode)
REV. 0
–17–
AD1838
CONTROL/STATUS REGISTERS
DAC Volume Control
The AD1838 has 13 control registers, 11 of which are used to
set the operating mode of the part. The other two registers,
ADC Peak 0 and ADC Peak 1, are read-only and should not
be programmed. Each of the registers is 10-bits wide with the
exception of the ADC peak reading registers, which are six-bits
wide. Writing to a control register requires a 16-bit data frame to
be transmitted. Bits 15 to 12 are the address bits of the required
register. Bit 11 is a read/write bit. Bit 10 is reserved and should
always be programmed to 0. Bits 9 to 0 contain the 10-bit value
that is to be written to the register or, in the case of a read operation,
the 10-bit register contents. Figure 3 shows the format of the SPI
read and write operation.
Each DAC in the AD1838 has its own independent volume
control. The volume of each DAC can be adjusted in 1024
linear steps by programming the appropriate register. The
default value for this register is 1023, which provides no attenu-
ation, i.e., full volume.
ADC Control Registers
The AD1838 register map has five registers that are used to
control the functionality and to read the status of the ADCs. The
function of the bits in each of these registers is discussed below.
ADC Peak Level
These two registers store the peak ADC result from each channel
when the ADC peak readback function is enabled. The peak
result is stored as a 6-bit number from 0 dB to –63 dB in 1 dB
steps. The value contained in the register is reset once it has
been read, allowing for continuous level adjustment as required. Note
that the ADC peak level registers use the six most significant
bits in the register to store the results.
DAC Control Registers
The AD1838 register map has eight registers that are used to control
the functionality of the DAC section of the part. The function
of the bits in these registers is discussed below.
Sample Rate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC
Control III should be programmed appropriately, based on the
master clock frequency.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control III should be
programmed appropriately based on the master clock frequency.
Power-Down/Reset
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a similar manner to the DAC power-down.
This bit controls the power-down status of the DAC section.
By default, normal mode is selected. But by setting this bit, the
digital section of the DAC stage can be put into a low power
mode, thus reducing the digital current. The analog output
section of the DAC stage is not powered down.
High-Pass Filter
The ADC signal path has a digital high-pass filter. Enabling this
filter will remove the effect of any dc offset in the analog input
signal from the digital output codes.
DAC Data-Word Width
These two bits set the word width of the DAC data. Compact
Disc (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
Dither
Enabling the dither function will add a small amount of random
charge to the sampling capacitors on the ADC inputs. This will
eliminate the effect of any idle tones that could occur if there
were no input signal present.
DAC Data Format
The AD1838 serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I2S, LJ, RJ, or DSP modes. Details of these interface modes are
given in the Serial Data Port section of this datasheet.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Data Format
De-Emphasis
The AD1838 serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I2S, LJ, RJ, or DSP modes.
The AD1838 provides built-in de-emphasis filtering for the three
standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
Master/Slave Auxiliary Mode
Each of the six DACs in the AD1838 has its own independent
mute control. Setting the appropriate bit will mute the DAC
output. The AD1838 uses a clickless mute function that attenu-
ates the output to approximately –100 dB over a number of cycles.
When the AD1838 is operating in the auxiliary mode, the auxiliary
ADC control pins, AUXBCLK and AUXLRCLK, which connect
to the external ADCs, can be set to operate as a master or slave.
If the pins are set in slave mode, one of the external ADCs should
provide the LRCLK and BCLK signals.
Stereo Replicate
Setting this bit copies the digital data sent to the stereo pair
DAC1 to the three other stereo DACs in the system. This
allows all three stereo DACs to be driven by one digital data
stream. Note that in this mode, DAC data sent to the other
DACs is ignored.
ADC Peak Readback
Setting this bit enables ADC peak reading. See the ADC section
for more information.
REV. 0
–18–
AD1838
Table III. Control Register Map
Register
Address
Register
Name
Reset
Setting (Hex)
Description
Type
Width
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DACCTRL1
DACCTRL2
DACVOL1
DACVOL2
DACVOL3
DACVOL4
DACVOL5
DACVOL6
RES
DAC Control 1
DAC Control 2
DAC Volume – Left 1
DAC Volume – Right 1
DAC Volume – Left 2
DAC Volume – Right 2
DAC Volume – Left 3
DAC Volume – Right 3
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
10
10
10
10
10
10
10
10
10
10
6
000
000
3FF
3FF
3FF
3FF
3FF
3FF
Reserved
Reserved
000
000
000
000
000
Reserved
RES
Reserved
ADC Left Peak
ADCPeak0
ADCPeak1
ADCCTRL1
ADCCTRL2
ADCCTRL3
Reserved
ADC Right Peak
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
R
6
R/W
R/W
R/W
R/W
10
10
10
10
Table IV. DAC Control I
FUNCTION
DAC Data
Format
DAC Data-
Word Width
Power-Down
Reset
Address
R/W RES De-Emphasis
Sample Rate
15, 14, 13, 12 11
0000
10
0
9, 8
7, 6, 5
000 = I2S
001 = RJ
010 = DSP
4, 3
2
1, 0
0
00 = None
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
0 = Normal
1 = Power-Down
00 = 8× (48 kHz)
01 = 4× (96 kHz)
10 = 2× (192 kHz)
11 = 8× (48 kHz)
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
011 = LJ
11 = Reserved
100 = Pack Mode 256
101 = Reserved
110 = Reserved
111 = Reserved
Table V. DAC Control II
FUNCTION
MUTE DAC
Stereo
Address R/W RES Reserved Replicate
Reserved Reserved OUTR3 OUTL3 OUTR2 OUTL2 OUTR1 OUTL1
15, 14,
13, 12
11
0
10
0
9
0
8
7
0
6
0
5
4
3
2
1
0
0001
0 = Off
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
1 = Replicate
1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute
REV. 0
–19–
AD1838
Table VI. DAC Volume Control
FUNCTION
Table VII. ADC Peak
FUNCTION
Four
Fixed
Bits
Address
R/W
11
RES DAC Volume
Address
R/W RES Six Data Bits
15, 14, 13, 12
10
0
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
15, 14, 13, 12
11
1
10 9, 8, 7, 6, 5, 4
000000 = 0.0 dBFS
000001 = –1.0 dBFS
3, 2, 1, 0
0000
0010 = DACL1
0011 = DACR1
0100 = DACL2
0101 = DACR2
0110 = DACL3
0111 = DACR3
0
0000000000 = 1/1024
0000000001 = 2/1024
0000000010 = 3/1024
1111111110 = 1022/1024
1111111111 = 1023/1024
0010 = LeftADC
1011 = RightADC
0
000010 = –2.0 dBFS These
four bits
are always
zero.
111111 = –63.0 dBFS
Table VIII. ADC Control I
FUNCTION
ADC
Sample
Address
R/W
RES
Dither
Filter
Power-Down
Rate
Reserved
15, 14, 13, 12
1100
11
0
10
0
9
8
7
6
5, 4, 3, 2, 1, 0
0 = Disabled
1 = Enabled
0 = All Pass
1 = High Pass
0 = Normal
1 = Power-Down
0 = 48 kHz
1 = 96 kHz
0, 0, 0, 0, 0, 0
0, 0, 0, 0, 0, 0
Table IX. ADC Control II
FUNCTION
R/W
RES
Master/Slave
Aux Mode
ADC
Data Format
ADC Data-
Word Width
ADC MUTE
Right
Address
RES
Reserved
Left
15, 14, 13, 12
1101
11
0
10
0
9
8, 7, 6
000 = I2S
001 = RJ
010 = DSP
5, 4
3, 2
0, 0
1
0
0 = Slave
1 = Master
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = On
1 = Mute
0 = On
1 = Mute
011 = LJ
100 = Packed 256
101 = Reserved
110 = Auxiliary 256
111 = Reserved
Table X. ADC Control III
FUNCTION
ADC
R/W
IMCLK
DAC
ADC
Address
RES RES Reserved Clocking Scaling
Peak Readback
Test Mode
Test Mode
15, 14, 13, 12 11
1110
10
0
9, 8
0, 0
7, 6
5
4, 3, 2
1, 0
0
00 = MCLK ꢀ 2
01 = MCLK
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
1 = Enabled Peak Readback
All Others Reserved All Others Reserved
10 = MCLK ꢀ 2/3
11 = MCLK ꢀ 2
REV. 0
–20–
AD1838
600Z
47ꢄF 5.76kꢃ
5.76kꢃ
AUDIO
INPUT
+
120pF NPO
68pF
NPO
11kꢃ
100pF
NPO
OUTLNx
OUTLPx
237ꢃ
11kꢃ
3.01kꢃ
ADCxN
OP275
270pF
NPO
VREF
1nF
NPO
AUDIO
OP275
OUTPUT
604ꢃ
2n2F
NPO
100pF
NPO
560pF
NPO
5.76kꢃ
5.76kꢃ
1nF
NPO
5.62kꢃ
15kꢃ
150pF
NPO
5.62kꢃ
750kꢃ
237ꢃ
ADCxP
OP275
VREF
Figure 14. Typical ADC Input Filter Circuit
Figure 15. Typical DAC Output Filter Circuit
REV. 0
–21–
AD1838
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
52-Lead Plastic Quad Flatpack [MQFP]
(S-52)
13.45 (0.5295)
13.20 (0.5197) SQ
12.95 (0.5098)
2.45 (0.0965)
MAX
0.95 (0.0374)
0.80 (0.0315)
0.65 (0.0256)
39
27
40
26
SEATING
PLANE
10.11 (0.3980)
10.00 (0.3937) SQ
9.91 (0.3902)
7.80
(0.3071)
REF
TOP VIEW
(PINS DOWN)
VIEW A
PIN 1
52
14
1
13
0.38 (0.0150)
0.22 (0.0087)
0.65 (0.0256)
BSC
0.23 (0.0091)
0.13 (0.0051)
2.10 (0.0827)
2.00 (0.0787)
1.95 (0.0768)
7ꢅ
0ꢅ
0.25 (0.0098)
MIN COPLANARITY
VIEW A
ROTATED 90ꢅ CCW
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. 0
–22–
–23–
–24–
相关型号：
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