AD1803JRUZ-REEL_技术文档

Modem/Telephony Codec

AD1803

FUNCTIONAL BLOCK DIAGRAM

VOLTAGE

FEATURES

Low power modem/telephony codec

16-bit oversampling Σ-Δ converter technology

Intel® AC ‘97 Rev 2.1-compliant modem codec

implementation

AC ‘97 or DSP style serial interface

Supports all modem/fax standards, including V.90

Multiple crystal/clock rates supported

Programmable gain, attenuation, and mute

On-chip signal filters

AVDD

AGND

V

REF

REFERENCE

AD1803

DVDD

DGND

BIT_CLK

SYNC

G[1]/MIC

Rx

+20dB

MUX

ADC

FILTER

Σ-Δ ADC

FILT

SDATA_IN

SDATA_OUT

RESET

PWM BLOCK

G[4]/MOUT

DAC FILTER

+ GAIN

/ATTEN

DAC

FILTER

Σ-Δ MODULATOR

Tx

Digital interpolation and decimation filters

Analog output low pass

Programmable sample rates

CONTROL

REGISTERS

From 6.4 kHz to 16 kHz

With 1 Hz, 8/7 Hz, and 10/7 Hz resolution

ADDRESS

REGISTER

G[0]

G[2]

Digital codec engine with variable sample rate

conversion

Digital monitor speaker output

24-lead TSSOP

G[3]/WAKE

G[5]

REGISTER CONTROL LOGIC

CLK_OUT

XTALO

G[6]

G[7]

0.6 μm CMOS technology

Operation from 3.3 V or 5 V supply

Advanced power management

XTALI

Figure 1.

APPLICATIONS

Modems (PC and embedded)

Voice and telephony

Fax machines, answering machines, speakerphones

PBX systems

Smart appliances

GENERAL DESCRIPTION

The AD1803 is a low power, 16-bit codec for modem,

voice/handset, and telephony applications. It can also

be used as a cellular telephone interface.

The AD1803 supports advanced power management with

several power saving modes. The codec supports seven general-

purpose input/output (GPIO) pins and a wake interrupt signaling

mechanism on GPIO events.

The AD1803 is an Intel AC '97 Rev 2.1-compliant modem

codec (refer to documentation about the Intel AC '97) with

selectable AC '97 or a DSP-style serial interface.

The AD1803JRUZ is a lead-free environmentally friendly

product. It is manufactured using the most up-to-date mate

rials and processes. The coating on the leads of each device is

100% pure tin electroplate. The device is suitable for lead-free

applications and can withstand surface-mount soldering at up to

255°C ( 5°C). In addition, it is backward compatible with

conventional tin-lead soldering processes. This means that the

electroplated tin coating can be soldered with tin-lead solder

pastes at reflow temperatures of 220°C to 235°C.

The AD1803 codec uses high performance Σ-Δ ADCs and

DACs with programmable gain/attenuation. It has a digital

Σ-Δ monitor output with selectable mix from ADC and DAC

channels for call progress monitoring.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights ofthird parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD1803

TABLE OF CONTENTS

Features .............................................................................................. 1

Extended Status and Control Register..................................... 17

Line DAC/ADC Sample Rate Control Register ..................... 18

DAC/ADC Level Control Register........................................... 19

GPIO Pin Configuration Register............................................ 20

GPIO Pin Polarity/Type Register............................................. 20

GPIO Sticky Pin Register .......................................................... 20

GPIO Pin Wake-Up Mask......................................................... 21

GPIO Pin Status Register .......................................................... 21

Miscellaneous Modem AFE Status and Control Register..... 21

Configuration 1 Register........................................................... 22

Configuration 2 Register........................................................... 23

Bank 1—GPIO Initial States Register...................................... 24

Bank 1—Clock Pad Control Register ...................................... 24

Bank 2 - Monitor Output Control Register ............................ 25

Version ID Register.................................................................... 25

Vendor ID1 Register .................................................................. 26

Vendor ID2 Register .................................................................. 26

Applications..................................................................................... 27

Application Circuits................................................................... 27

Typical Initialization Sequence Immediately After First

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

Typical Supply Current................................................................ 5

Timing Specifications .................................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Environmental Conditions.......................................................... 8

Package Characteristics ............................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Theory of Operation ...................................................................... 11

Serial Interface Mode Selection................................................ 11

Serial Interface Behavior and Protocol When in AC '97

Mode ............................................................................................ 11

AC '97 Interface Modes ............................................................. 11

Serial Interface Behavior and Protocol When in DSP Mode 12

Register Banks............................................................................. 14

Register Access Restrictions...................................................... 14

General-Purpose I/O Pin Operation ....................................... 14

Control Register Map..................................................................... 15

Control Register Details................................................................. 17

Extended Modem ID Register .................................................. 17

RESET

.......................................................................................... 29

Typical Codec Power-Up Sequence......................................... 30

Typical Codec Power-Down Sequence.................................... 31

Typical Chip Power-Down Sequence ...................................... 31

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

12/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Figure 18...................................................................... 28

Changes to Ordering Guide .......................................................... 32

8/01—Revision 0: Initial Version

Rev. A | Page 2 of 32

AD1803

SPECIFICATIONS

TEST CONDITIONS

Test conditions for the AD1803 are as follows, unless otherwise noted.

General Test Conditions

DAC Output Test Conditions

Temperature at 25°C

0 dB attenuation relative to full scale

Input 0 dB

Mute Off

Digital supply at 3.3 V/5 V

Analog supply at 3.3 V/5 V

Sample rate (f_S) at 8 kHz

Input signal at 1008 Hz

Analog output pass band at 20 Hz to 4 kHz

ADC FFT size at 512

DAC FFT size at 4096

V_IH@ 2.1 V

V_IL@ 1.2 V

10 kΩ output load

ADC Input Test Conditions

Autocalibrated

0 dB PGA gain

Mute off

Input: 1.0 dB relative to full scale

V

_OH@ 2.9 V

_OL@ 0.3 V

I

_OH@ −2.0 mA

I_OL@ +2.0 mA

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC RECEIVE PATH

Full-Scale Input Voltage¹

AD1803 Rx Input

Resistance—Rx Input²

0 dB Gain

PGA gain = 0 dB, offset error = 0% of FS

0 dBm

1.56

2.2

V rms

V p-p

2.1

2.3

110

10

15

kΩ

pF

+20 dB Gain

Capacitance—Rx Input²

Rx Programmable Gain

Gain Step Size³

0 dB to 42.5 dB

1.0

41.5

1.5

42.5

2.0

43.5

dB

Input Gain Span⁴

Analog-to-Digital Converter

Dynamic Range⁵

Dynamic Range^{2, 5}

THD + N

−60 dB input, PGA gain = 0 dB

−60 dB input, PGA gain = 6 dB

−60 dB input, PGA gain = +12 dB

−1 dB input referenced to full scale

85

90

−90

80

1

dB

% of FS

−85

5

Signal-to-Intermodulation Distortion²CCIF method

Offset Error

DAC TRANSMIT PATH

Digital-to-Analog Converter

Dynamic Range⁵

THD + N

0 V analog input, PGA gain = 0 dB

−60 dB input, output gain = 0 dB

−1 dB input referenced to full scale

85

−75

80

dB

mV

Signal-to-Intermodulation Distortion²CCIF method

Total Out-of-Band Energy²

DC Offset

Measured from 0.555 × f_Sto 100 kHz

−40

100

Programmable Gain/Attenuator

Step Size³

Output Attenuation Span

Full-Scale Output Voltage

Tx Output

+12 dB to −34.5 dB

0 dBm

1.0

45.5

1.5

46.5

2.0

48

dB

2.1

2.2

15

100

2.3

V p-p

pF

Tx Pin Capacitance

Tx Load Capacitance

Rev. A | Page 3 of 32

AD1803

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

MONITOR OUTPUT

Digital-to-Analog Converter

Dynamic Range^{2, 5}

THD + N^{2, 5}

−60 dB input, A-weighted

50

0.316

−50

dB

%

dB

1

−40

Programmable Gain/Attenuator

Step Size²

Output Attenuation Span²

−18 dB to +45 dB

2.4

3.0

63

3.6

dB

DIGITAL DECIMATION AND INTERPOLATION

FILTERS²

Pass-Band Edge

Pass-Band

−0.22 dB point

−3.0 dB point

0.445 × f_SHz

0.490 × f_SHz

Pass-Band Ripple

Transition Band

Stop-Band Edge⁶

Stop-Band Rejection

Group Delay

0.0

−0.2

0.555 × f_SHz

dB

0.445 × f_S

0.555 × f_S

78.0

Hz

dB

s

Plus 3 dB roll-off

21/f_S

Group Delay Variation Over Pass Band

0 kHz to 4 kHz

0 kHz to 8 kHz

0.45

1.30

16

μs

kHz

Sample Rate

6.4

STATIC DIGITAL

V_IH, High Level Input Voltage

V_IL, Low Level Input Voltage

V_OH, High Level Output Voltage

V_OL, Low Level Output Voltage

Input Leakage Current

Output Leakage Current

POWER SUPPLY

Digital Inputs

0.65 × DVDD

0.9 × DVDD

V

0.35 × DVDD

V

I_OH= −0.5 mA

I_OL= +0.5 mA

V

0.1 × DVDD

+10

V

−10

μA

+10

AVDD Range

3.3 V/5 V

3.0/4.75

3.6/5.25

V

DVDD Range

3.3 V/5 V

Analog and Digital Supply Current

Power Supply Rejection⁷

CLOCK

5 V, see Table 2

3.3 V, see Table 2

100 mV p-p, signal @ 1 kHz

40

dB

Input Clock Frequency

Recommended Clock Duty Cycle

12.288

45

24.576

50

32.768

55

MHz

%

¹RMS values assume sine wave input.

²Guaranteed by design, not production tested.

³All steps tested.

⁴The ADC gain is achieved using a 0 dB to 22.5 dB variable gain stage and a 20 dB fixed gain stage. The 22.5 dB to 42.5 dB gain steps are achieved by enabling the 20 dB gain stage.

⁵THD + N referenced to full scale.

⁶The stop band repeats itself at multiples of 64 × f_S, where f_Sis the sampling frequency. The digital filter attenuates to −78.0 dB or better across the frequency spectrum,

except for a range 0.555 × f_Swide at multiples of 64 × f_S.

⁷At both analog and digital supply pins (both ADCs and DACs).

Rev. A | Page 4 of 32

AD1803ꢀ

TYPICAL SUPPLY CURRENT

Typical supply current is for most common modes of operation. All currents in mA, unless otherwise noted.

Table 2.

Resource

3.3 V

5.0 V

Register Writes to Enter Mode

GPIO Weak Pull-Up Current per Pin

Default settings after power-on RESET

~100

~140 μA

RESET is Asserted

XTALI Off (All Down)¹

<30.0

1.4

1.0

<40.0 μA

2.4

1.7

Default settings after power-on RESET

5C:R34P4 = 1

5C:R34P4 = 1, 64b1:XTLP = 1

5C:CLKEA = 1

XTALI Enabled: Nominal Power

XTALI Enabled: Low Power

CLK_OUT Pin Running²

1.6

3.2

RESET is Deasserted and Analog and Digital Codec

in Full Power Mode

SPORT and CLK_OUT Active^{2, 3}

2.6

2.2

1.7

1.9

7.3

8.2

9.2

9.3

10.2

6.4

Default settings after power-on RESET

64b1:XTLP = 1

5C:CLKED = 0

3E:VPDN = 0

3E:APDN = 0

XTALI in Low Power Mode^{2, 3}

CLK_OUT Inactive (Low)³

V_REFPowered Up³

ADC Enabled

DAC Enabled^{3, 5}

ADC + DAC Enabled^{3, 5}

ADC, DAC, + MON Enabled^{3, 4, 5}

ADC, DAC, + MON Enabled^{3, 5, 6}

5.7

4.3

4.5

12.4

13.7

14.7

14.9

16.3

3E:DPDN = 0

3E:APDN = DPDN = 0

3E:APDN = DPDN = 0, 5E:GPMON = 1

¹Assumes all inputs are static (not switching) and all output loads are capacitive (nonresistive).

²Excludes current drawn by CLK_OUT pin board loading.

³Assumes the serial interface is configured in AC '97 primary mode with 20 pF loads on the SDATA_IN pin and BIT_CLK pin. Typical current is approximately 0.8 mA less if the

serial interface is configured in DSP mode with 20 pF loads on the SYNC pin, BIT_CLK pin, and SDATA_IN pin (due to a lower BIT_CLK frequency).

⁴Assumes a 20 pF load on the G[4]/MOUT pin.

⁵Assumes no DAC load, 0.6 mA should be added if a 600 Ω load is used.

⁶Assumes the G[4]/MOUT pin is loaded with a 1 kΩ resistor in series with a parallel 4.7 kΩ resistor and 100 nF capacitor combination tied to digital ground. This filter, with the

output taken from the middle node, has a 1500 Hz corner to filter out high-frequency Σ-Δ noise. It generates an approximate 1 V p-p output when using a 5 V digital supply

with the monitor output configured as first order (Bit MMD1 and Bit MMD0 set to 10 in Register 0x60 Bank 2) if the filter output load is greater than or equal to 20 kΩ.

Rev. A | Page 5 of 32

AD1803ꢀꢀ

TIMING SPECIFICATIONS

Table 3.

Parameter¹

Symbol

Min

Typ

Max

Unit

SERIAL PORT— AC '97 MODE

RESET Active Low Pulse Width

t_{RST_LOW}

t_RST2CLK

t_{SYNC_HIGH}

t_SYNC2CLK

1.0

μs

ns

μs

ns

MHz

ns

ps

ns

kHz

μs

ns

RESET Inactive to BIT_CLK Start-Up Delay

SYNC Active High Pulse Width (Warm RESET)

SYNC Inactive to BIT_CLK Start-Up Delay (Warm RESET)

BIT_CLK Frequency

BIT_CLK Period

BIT_CLK Output Jitter²

BIT_CLK High Pulse Width

BIT_CLK Low Pulse Width

SYNC Frequency

162.8

1.3

162.8

12.288

81.4

t_{CLK_PERIOD}

750

44.76

t_{CLK_HIGH}

t_{CLK_LOW}

36.62

40.69

48.0

SYNC Period

t_{SYNC_PERIOD}

t_SETUP

t_HOLD

20.8

Setup to Falling Edge of BIT_CLK

Hold from Falling Edge of BIT_CLK

Propagation Delay

BIT_CLK Rise Time

BIT_CLK Fall Time

SYNC Rise Time

SYNC Fall Time

SDATA_IN Rise Time

SDATA_IN Fall Time

SDATA_OUT Rise Time

SDATA_OUT Fall Time

End of Slot 2 to BIT_CLK, SDATA_IN Low (MLNK Set)

Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)

Rising Edge of RESET to Hi-Z Delay (ATE Test Mode)

10.0

t_CO

15

6

t_RISECLK

t_FALLCLK

t_RISESYNC

t_FALLSYNC

t_RISEDIN

t_FALLDIN

t_RISEDOUT

t_FALLOUT

t_{S2_PDOWN}

t_SETUP2RST

t_OFF

2

4

6

1000

15

25

SERIAL PORT—DSP MODE

RESET Active Low Pulse Width

RESET Inactive to BIT_CLK Start-Up Delay

BIT_CLK Frequency

BIT_CLK Period

BIT_CLK Output Jitter²

SYNC Frequency

SYNC Period

Setup to Falling Edge of BIT_CLK

Hold from Falling Edge of BIT_CLK

Propagation Delay

BIT_CLK Rise Time

BIT_CLK Fall Time

SYNC Rise Time

SYNC Fall Time

SDATA_IN Rise Time

SDATA_IN Fall Time

SDATA_OUT Rise Time

SDATA_OUT Fall Time

t_{RST_LOW}

t_RST2CLK

1.0

μs

ns

MHz

ns

ps

kHz

μs

ns

162.8

4.096

244.14

t_{CLK_PERIOD}

750

8

125

t_{SYNC_PERIOD}

t_SETUP

t_HOLD

10.0

t_CO

15

6

t_RISECLK

t_FALLCLK

t_RISESYNC

t_FALLSYNC

t_RISEDIN

t_FALLDIN

t_RISEDOUT

t_FALLDOUT

t_SETUP2RST

t_OFF

2

4

Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)

Rising Edge of RESET to Hi-Z Delay (ATE Test Mode)

15

25

¹Guaranteed over operating temperature range and supply power.

²Output jitter is directly dependent on crystal input jitter.

Rev. A | Page 6 of 32

AD1803ꢀ

TIMING DIAGRAMS

BIT_CLK

SYNC

t_{RST_LOW}

t_RST2CLK

t_RISECLK

t_RISESYNC

t_RISEDIN

t_FALLCLK

t_FALLSYNC

t_FALLDIN

RESET

BIT_CLK

RESET

Figure 2. Cold

SDATA_IN

t_{SYNC_HIGH}

t_SYNC2CLK

SYNC

SDATA_OUT

t_RISEDOUT

t_FALLDOUT

BIT_CLK

Figure 6. Signal Rise and Fall Time

RESET

Figure 3. Warm

t_{CLK_LOW}

BIT_CLK

t_{CLK_HIGH}

t_{CLK_PERIOD}

BIT_CLK

t_{SYNC_LOW}

SYNC

SDATA_IN

t_{SYNC_HIGH}

t_{SYNC_PERIOD}

t_CO

Figure 4. Clock Timing

Figure 7. Propagation Delay

SLOT 2

SLOT 1

SYNC

BIT_CLK

t_SETUP

WRITE

TO 0x56

DATA

MLNK

DON’T

CARE

BIT_CLK

SYNC

SDATA_OUT

t_{S2_PDOWN}

SDATA_OUT

SDATA_IN

NOTES

t_HOLD

1. BIT_CLK IS NOT TO SCALE.

Figure 5. Data Setup and Hold

Figure 8. AC Link Low Power Mode Timing

Rev. A | Page 7 of 32

AD1803ꢀꢀ

ABSOLUTEꢀMAXIMUMꢀRATINGSꢀꢀ

Table 4.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating

Parameter

Rating

Power Supplies

T_AMB= T_CASE− (P_D× θ_CA)

Digital (DVDD)

Analog (AVDD)

−0.3 V to +6.0 V

10.0 mA

−0.3 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

0°C to 70°C

where:

Input Current (Except Supply Pins)

Analog Input Voltage (Signal Pins)

Digital Input Voltage (Signal Pins)

Operating Ambient Temperature

Storage Temperature

T_CASEis the case temperature in °C,

P_Dis the power dissipation in W,

θ_CAis the thermal resistance (case-to-ambient),

θ_JAis the thermal resistance (junction-to-ambient),

θ_JCis the thermal resistance (junction-to-case).

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

PACKAGE CHARACTERISTICS

Table 5.

Package

θ_JA

θ_JC

θ_CA

TSSOP

83.8°C/W

15.6°C/W

68.2°C/W

ESD CAUTION

Rev. A | Page 8 of 32

AD1803ꢀ

PINꢀCONFIGURATIONꢀANDꢀFUNCTIONꢀDESCRIPTIONSꢀ

1

24

23

22

21

20

19

18

17

16

15

14

13

CLK_OUT

G[5]

G[6]

G[7]

AVDD

Tx

2

DGND

3

DVDD

4

XTALO

AD1803

TOP VIEW

(Not to Scale)

5

XTALI

6

BIT_CLK

SDATA_IN

SDATA_OUT

SYNC

AGND

7

V

REF

8

FILT

Rx

9

10

RESET

G[1]/MIC

G[0]

G[4]/MOUT 11

12

G[3]/WAKE

G[2]

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic

Pin No.

I/O

Description

ANALOG SIGNALS

DVDD

DGND

AVDD

AGND

Rx

Tx

FILT

V_REF

3

2

I

O

I

Digital Supply. Range: 5.0 V 10% or 3.3 V 10% (independent of AVDD).

Digital Ground. Must be at same potential as AGND.

Analog Supply. Range is 5.5 V through 3.0 V (independent of DVDD).

Analog Ground. Must be at same potential as DGND.

Receive (ADC) input.

Transmit (DAC) output.

ADC Filter Bypass. Requires 1 μF capacitor to AGND.

Voltage Reference. Requires 1 μF capacitor to AGND.

21

19

16

20

17

18

I

CLOCK SIGNALS

XTALI

5

I

Crystal or Clock Input (12.288 MHz, 24.576 MHz, or 32.768 MHz). This clock input is neces-

sary only if the AD1803 is configured in either AC '97 primary or DSP mode, or if a wake

interrupt from an event is required (in any mode). This pin must be tied to DVDD or DGND

(not floated) when clock input is not necessary. If a crystal is used, it must be parallel

resonant first harmonic, and tied between this pin and the XTALO pin with load capacitance

specified by the crystal supplier. See the XTAL1 bit and the XTAL0 bit in Register 0x5C for

further details.

XTALO

CLK_OUT

4

1

O

Crystal Output. This pin should be floated when a crystal is not used.

Buffered version of clock present on the XTALI pin, unless disabled. See the CLKED bit and

CLKEA bit in Register 0x5C for further details.

SERIAL INTERFACE SIGNALS¹

RESET

10

I

Active Low Power-Down. Level of power-down is determined by bits in Register 0x5C. This

pin must be asserted (driven low) as power is first applied until the supply is stable. The

AD1803 is RESET exclusively by an internal power-on RESET circuit.

BIT_CLK

SYNC

6

9

I/O

Serial Data Clock. Output if the AD1803 configured in AC '97 primary or DSP mode. Input if

the AD1803 is configured in any AC '97 secondary mode.

Serial Data Frame Sync. Output if the AD1803 is configured in DSP mode. Input if the

AD1803 is configured in any AC '97 mode.

SDATA_IN

SDATA_OUT

7

8

O

I

Serial Data Output from AD1803.

Serial Data Input to AD1803.

Rev. A | Page 9 of 32

AD1803ꢀꢀ

Mnemonic

Pin No.

I/O

Description

GENERAL-PURPOSE I/O AND

BARRIER INTERFACE SIGNALS²

G[0]^{3, 4}

G[1]/MIC^{3, 5}

14

15

I/O

I

General-Purpose I/O.

I

Analog MIC Input. See Bit GPMIC in Register 0x5E.

General-Purpose I/O. Also used to select serial interface mode.

General-Purpose I/O.

Wake Interrupt Output (see the GPWAK bit in Register 0x5E). This pin selects the serial

interface mode. When serving as WAKE, this pin is driven high if selected GPIO pins receive

selected logic levels (see Register 0x52 and Register 0x4E).

General-Purpose I/O.

Monitor Output. See the Configuration 2 Register section.

General-Purpose I/O.

G[2]^{3, 4, 6}

13

12

I/O

O

G[3]/WAKE^{3, 4, 6}

G[4]/MOUT^{3, 4}

11

I/O

O

I/O

G[5]^{3, 4}

G[6]^{3, 4}

G[7]^{3, 4}

24

23

22

General-Purpose I/O.

¹See the G[3]/WAKE pin and the G[2] pin for serial interface mode selection.

²See Register 0x4C through Register 0x54 and Bank 1 Register 0x60 for the general-purpose I/O pin control.

³By default the G[7] pin, G[6] pin, G[5] pin, G[4] pin, G[3] pin, G[2] pin, and G[1] pin serve as inputs with weak (~30 kΩ equivalent) internal pull-up devices enabled.

⁴Input voltage on the G[7] pin, G[6] pin, G[5] pin, G[4] pin, G[3] pin, G[2] pin, and G[0] pin must not exceed DVDD by more than 0.3 V.

⁵Input voltage on Pin G[1] must not exceed AVDD by more than 0.3 V.

6

RESET

The states of the G[3/WAKE] pin and G[2] pin are sampled when

is deasserted (driven from low to high) for the first time after power is applied to select AD1803 serial

interface mode. Once sampled, serial interface mode can be changed only by removing power from the AD1803.

G[3]/WAKE

High/High

High Low

Low High

Low

G[2]

Serial interface mode

AC ‘97

Low

Mode, primary device (ID: 00)

Mode, secondary device (ID: 01)

Mode, secondary device (ID: 10)

DSP mode

Rev. A | Page 10 of 32

AD1803ꢀ

THEORYꢀOFꢀOPERATIONꢀ

SERIAL INTERFACE MODE SELECTION

By default the AD1803 uses Slot 5 to send and receive sample

data, but this can be changed to Slot 10 or Slot 11. See the

SPCHN bit, SPGBP bit, SPDSS bit, SPISO bit, SPDL1 bit, and

SPDL0 bit in Register 0x5E for additional AC '97 mode con-

figuration enhancements.

RESET

When power is first applied to the AD1803,

must be

RESET

asserted (

pin driven low), and kept asserted until the

RESET

power has stabilized. While

is asserted, the AD1803’s

serial interface mode is chosen by the state of Pin 12

(G[3]/WAKE) and Pin 13 (G[2]).

AC '97 INTERFACE MODES

Table 7.

Primary Mode

Pin 12 Pin 13 Mode Chosen

RESET

Entered if G[3] pin and G[2] pin are high when the

is deasserted for the first time:

High

Low

High

Low

High

Low

AC '97 Mode—Primary Device (ID: 00)

AC '97 Mode—Secondary Device (ID: 01)

AC '97 Mode—Secondary Device (ID: 10)

DSP Mode

•

AD1803 is the timing master: drives BIT_CLK at

12.288 MHz.

Note that Pin 12 and Pin 13 have weak pull-up devices internal

to the AD1803 that are enabled by default. Therefore, if these

•

AD1803 accepts the 48 kHz SYNC timing signal.

AD1803 requires a crystal or clock on XTALI (see the

RESET

pins are floated, AC '97 primary mode is chosen. When

RESET

XTAL1 bit and XTAL0 bit in Register 0x5C for frequency).

Secondary Mode

Entered if the G[3] pin is high and G[2] pin is low when the

is deasserted (

pin driven high) for the first time after

power is applied, the states of Pin 12 and Pin 13 are latched,

locking in serial interface mode. Subsequent changes of the

logic level presented on Pin 12 and Pin 13 have no effect on

serial port mode until power is removed from the AD1803.

RESET

pin is deasserted for the first time or if the G[3] pin is

RESET

low and the G[2] pin is high when the

for the first time:

pin is deasserted

RESET

After this first deassertion of

, Pin 12 and Pin 13 take

on new roles and serve as general-purpose I/O control pins.

The AD1803 does not need an active clock source for proper

operation during this mode selection.

•

AD1803 is the timing slave: accepts BIT_CLK at

12.288 MHz.

SERIAL INTERFACE BEHAVIOR AND PROTOCOL

WHEN IN AC '97 MODE

•

AD1803 accepts the 48 kHz SYNC timing signal.

AD1803 does not require a crystal or clock on XTALI

(see the XTAL1 bit and XTAL0 bit in Register 0x5C for

The AD1803 serial interface is compatible with the AC '97

Rev 2.1 specification as either a primary or a secondary

modem/handset codec device. Consult this specification

for complete behavioral details.

RESET

frequency), unless wake from an event during

desired. XTALI okay here?

is

SLOT #

SYNC

0

1

2

3

4

5

6

7

8

9

10

11

12

TAG

CMD

PCM

L

PCM

R

LINE1

PCM

LFE

LINE2

DAC

HSET

DAC

I/O

SDATA_OUT

SDATA_IN

ADDR

DATA

DAC CENTER L SURR R SURR

CTRL

(OUTPUT FROM CONTROLLER/DSP – INPUT TO AD1803)

TAG STATUS STATUS

ADDR DATA

PCM

L

PCM

R

LINE1

ADC

MIC

ADC

RSRVD RSRVD RSRVD

LINE2

ADC

HSET

AD

I/O

STATUS

(INPUT TO CONTROLLER/DSP – OUTPUT FROM AD1803)

Figure 10. AC '97 Interface Timing

Rev. A | Page 11 of 32

AD1803ꢀꢀ

SERIAL INTERFACE BEHAVIOR AND PROTOCOL

WHEN IN DSP MODE

While the AD1803 provides 16-bit ADC sample output, only

15-bit DAC sample input is possible because of this. If the LSB

of the word into the AD1803 is set to 0, no control frame is

requested and the next frame is another data frame. If the

LSB of the word into the AD1803 is set to 1, a control frame

is requested and the next frame is a control frame.

In DSP mode, the AD1803 requires a clock on XTALI to func-

tion properly. This clock can be created by placing a crystal

between Pin XTALI and Pin XTALO with appropriate trim

capacitors. Alternatively, a clock can be driven directly onto

the XTALI pin from an external source, in which case XTALO

must be floated. When the AD1803 serial interface is configured in

DSP mode, the clock presented on the XTALI pin is assumed to

be 24.576 MHz. However, a 12.288 MHz or 32.768 MHz clock

could be used instead, providing

When a control frame is requested, an extra frame is inserted

between data frames avoiding an interruption of codec sample

data flow. The 16-bit control word into the AD1803 consists of

(from MSB to LSB):

•

A register read/write request bit (0 to request a write, 1 to

request a read).

•

A register write informs the AD1803 of the true clock

frequency before the codec is enabled.

The 6 MSBs of a 7-bit register address (where the LSB is

removed to save space since it is always a 0).

•

It is acceptable to have the serial port bit clock and frame

sync run at rates different from the start-up nominal until

the AD1803 is informed of the true XTALI clock frequency.

A byte select bit (0 to select the lower byte of the 16-bit

control register addressed, 1 to select the upper byte of

the 16-bit control register addressed).

RESET

Within 1 ms after

is deasserted and the AD1803 receives

•

Eight bits of data that are written into the addressed register

if a write is requested. Otherwise, these last eight bits are

ignored.

a clock on XTALI, the AD1803 begins driving a 4.096 MHz bit

clock onto the BIT_CLK pin (assuming a 24.576 MHz XTALI

clock). Approximately 100 μs later, the AD1803 begins driving

an 8 kHz frame sync onto the SYNC pin (again assuming a

24.576 MHz XTALI clock). If the AD1803 receives an XTALI

clock that is higher/lower than the expected 24.576 MHz default,

these frequencies are scaled up/down (lineally) until the AD1803

is informed of the actual XTALI clock frequency by a write to

the XTAL1 and XTAL0 bits in Register 0x5C. See the XTAL1

and XTAL0 bits for further details including allowed alternate

XTALI frequencies.

While it seems peculiar to have a 7-bit register address with

the LSB dropped when sent to the AD1803, it should be noted

that AD1803 register addresses are defined by the AC '97 specifica-

tion, whether configured in an AC '97 mode or in DSP mode.

While the AC ’97 Rev 2.1 specification reserves odd addresses

for future feature expansion, there was no room in the DSP mode

control word for this unused bit. The 16-bit control word out

of the AD1803 consists of, from MSB to LSB, eight unused bits

that are always set to 0, followed by eight bits of data that reflect

the contents of the register addressed within the current frame, if

a read was requested. Otherwise, they are all set to 0.

Each serial interface frame consists of a single 16-bit word sent

into the AD1803 on the SDATA_OUT pin, and a single 16-bit

word sent out of the AD1803 on the SDATA_IN pin. These words

are simultaneously transferred during the first 16 clocks of the

BIT_CLK pin after the start of a frame. The start of a frame is

marked by one BIT_CLK long high pulse of the SYNC pin one

BIT_CLK period before the first bit in the frame. Data is trans-

mitted MSB first. Logic levels on all pins (SYNC, SDATA_IN,

and SDATA_OUT) are updated on BIT_CLK rising edges, and

should be sampled on BIT_CLK falling edges.

RESET

When serial interface frames first commence after

deasserted, there are 512 bits per frame (8 kHz frame rate/

is

4.096 MHz bit clock rate) where only the first 16 bits per frame

are typically utilized. Bits out of the AD1803 after the first 16

are typically set to 0, and bits into the AD1803 after the first 16

are typically ignored. However, when a control frame is requested

via the control frame request bit in a data frame, the control

frame is inserted between data frames and placed 256 bits after

the start of the data frame that requested the control frame. This

control frame is marked by an additional 1-bit long clock pulse,

high of the SYNC pin. Note that the spacing between data frames

is never affected by the insertion of a control frame.

By default, all frames are designated as data frames for delivery

of two’s complement DAC and ADC samples to and from the

AD1803 codec. To deliver control information into the part,

the LSB of the word into the AD1803 is stolen, from what

might otherwise have been DAC data, to serve as a control

frame request bit.

Rev. A | Page 12 of 32

AD1803ꢀ

The frame rate at startup is 8 kHz and there are exactly 512 bits

from the start of one data frame to the next; this changes as soon

as the codec is enabled (the codec is powered down by default

after power is first applied to the AD1803). Whenever the

codec is enabled, the frame rate is switched from 8 kHz to the

programmed codec sample rate, and whenever the codec is

powered down again, the frame rate switches back to 8 kHz. With

the bit clock always fixed at 4.096 MHz, this gives rise to a first

cause of variation in the number of bits between starts of data

frames. A second cause of a varying number of bits between

starts of data frames is the presence of a subtle jitter in the asser-

tion of frame sync when the codec is enabled. On average, there

is an exact match between the programmed sample rate and the

frame rate; the frame sync itself varies up to 4% of a sample

period from the ideal assertion point in time.

When the serial interface is in DSP mode, it is possible to access

only the upper or lower 8-bit byte of a 16-bit control register at

a time. While this is sufficient for manipulating many of the

AD1803 features, some features require more than eight control

bits and span multiple 8-bit bytes and/or multiple 16-bit words.

To allow all bits of a feature to take effect simultaneously, writes

to certain control bytes of certain registers are actually held in

holding latches until a particular control byte of the feature is

written. Note that a read of a control register always returns the

contents of a holding latch (if present for that register), which

does not necessarily reflect the control setting currently being

used by the AD1803. The only feature that incorporates this com-

plication is the codec sample rate, which writes to the lower byte

of Register 0x40 and does not take effect until the upper byte of

Register 0x40 is written.

FRAME TYPES:

SYNC

FREQUENCY: 8kHz WHEN CODEC DISABLED, AND EQUAL TO SAMPLE RATE WHEN CODEC ENABLED

BIT_CLK

FREQUENCY: 4.096MHz

DATA FRAME (16 BITS):

SDATA_OUT

T15 T14 T13 T12 T11 T10 T9

T8

T7

T6

T5

T4

T3

T2

T1

CR

C0

INPUT TO AD1803 (15 TRANSMIT SAMPLE DATA BITS, PLUS CONTROL FRAME REQUEST BIT)

SDATA_IN

C15 C14 C13 C12 C11 C10 C9

C8

C7

C6

C5

C4

C3

C2

C1

OUTPUT FROM AD1803 (16 CAPTURE SAMPLE DATA BITS)

CONTROL FRAME (16 BITS):

SDATA_OUT

RW A6

A5

A4

A3

A2

A1

B

W7 W6 W5 W4 W3 W2 W1 W0

INPUT TO AD1803 (READ/WRITE, ADDRESS, AND BYTE SELECT, FOLLOWED BY EIGHT BITS OF

REGISTER WRITE DATA)

SDATA_IN

R7

R6

R5

R4

R3

R2

R1

R0

OUTPUT FROM AD1803 (EIGHT ZEROS, FOLLOWED BY EIGHT BITS OF REGISTER READ DATA ADDRESSED

BY THIS FRAME)

Figure 11. Frame Types

FRAME INSERTED IF REQUESTED BY CR BIT

FRAME ORDERING:

SYNC

DATA FRAME

T15:1, CR

CONTROL FRAME

DATA FRAME

RW, A6:1,

B, W7:0

SDATA_OUT

SDATA_IN

IGNORED

T15:1, CR

IGNORED

C15:0

R7:0

C15:0

PERIOD EQUALS 1/8kHz WHEN CODEC IS DISABLED AND

PROGRAMMED SAMPLE PERIOD WHEN CODEC IS ENABLED

Figure 12. Frame Ordering

Rev. A | Page 13 of 32

AD1803ꢀꢀ

Table 8. Voice Features

Feature

REGISTER BANKS

AD1803

Register addresses are based on the Intel AC '97 specification.

Because the AC '97 specification lacks sufficient vendor defined

register space to control all extended features of the AD1803,

some control registers must be accessed indirectly using register

banks. See the BNK1 and BNK0 bits in Register 0x5C for details.

Power Supply

Maximum Sampling Frequency 16 kHz

3 V to 5 V

Differential Handset Output

Single-Ended Line Output

Output Full-Scale Range

Output Attenuation Steps

Input Line/MIC Mux

Input Full-Scale Range

Input 0 dB/20 dB Gain Block

PGA, 0 dB to 22.5 dB Range

Single-Ended Input

No

Yes, 600 Ω load

2.2 V p-p

+12 dB to −34.5 dB

Yes

0.777 V rms, 2.2 V p-p

Yes

REGISTER ACCESS RESTRICTIONS

Nearly all control registers can be read from or written to at any

time. Below is a list of restrictions that must be followed to ensure

proper operation of the AD1803:

•

The clock frequency delivered to the AD1803 on XTALI

must be identified (via a write to the XTAL1 bit and

XTAL0 bit in Register 0x5C) before the codec is enabled

(via a write of 0 to Bits DPDN or APDN in Register 0x3E).

Differential Input

Input Resistance

No

10 kΩ min varies with gain

(see Table 9)

During ADC calibration, codec sample rate (Register 0x40),

and ADC source and gain level must not be changed. Cali-

bration is initiated each time the AD1803’s ADC is enabled

(see Bit APDN in Register 0x3E) and whenever a 1 is written

to Bit ADCAL in Register 0x5C. Completion of calibration

is determined by polling the ADCAL bit.

Table 9. Input Resistance vs. Gain Setting

20 dB

PGA Gain (dB) Gain Block

PGA Gain (dB) R_IN(kΩ)

0.0 to 22.5

Disabled

Enabled

0.0 to 22.5

20.0 to 42.5

100

10

GENERAL-PURPOSE I/O PIN OPERATION

Refer to Registers 0x4C through 0x54 and Register 0x60 for

complete details (see Figure 13).

Rev. A | Page 14 of 32

AD1803ꢀ

CONTROLꢀREGISTERꢀMAPꢀꢀ

CONFIG (REG. 0x4C[n])

0 = OUTPUT

1 = INPUT

G[n] OUTPUT DATA

AC'97 MODES: FROM AC-LINK SLOT12

DSP MODE: FROM REG. 0x54

G[n] PIN

POLARITY (REG. 0x4E[n])

0 = CMOS

1 = OPEN DRAINS

INTERRUPT

OTHER INTERRUPT SOURCES

WAKE ENABLE (REG. 0x52[n])

DVDD

WEAK MOS

Q

S

R

POLARITY (REG. 0x4E[n])

0 = ACTIVE HIGH

1 = ACTIVE LOW

TRIGGERED BY "0" WRITE TO:

STATUS (REG. 0x54[n])

STICKY (REG. 0x50[n])

AC '97 MODE SLOT 12, OR

GPIO STATUS (REG. 0x54[n])

1

0

STICKY (REG. 0x50[n])

0 = NONSTICKY INPUT

1 = STICKY INPUT

Figure 13. Conceptual Diagram of GPIO Pin Behavior

Table 10. Register Summary (Direct Mapped Registers)

Table 11. Register Summary (Indirect Mapped Registers)

Address

0x3C

0x3E

0x40

0x46

0x4C

0x4E

0x50

0x52

0x54

0x56

0x5C

0x5E

0x7A

0x7C

0x7E

Register Name

Address

Register Name

Extended Modem ID

Extended AD1803 Status and Control

Line DAC/ADC Sample Rate Control

AD1803 DAC/ADC Level Control

GPIO Pin Configuration

GPIO Pin Polarity/Type

GPIO Pin Sticky

GPIO Pin Wake-Up Mask

GPIO Pin Status

Miscellaneous Modem AFE Status and Control

Configuration 1

0x60

0x64

0x60

Bank 1—GPIO initial states

Bank 1—clock pad control

Bank 1—monitor output control

Configuration 2

Version ID

Vendor ID1

Vendor ID2

Rev. A | Page 15 of 32

AD1803ꢀꢀ

Table 12. Register Map

Adr/Bnk

0x3C

0x3E

Default

0xX00X

0xFF00

0x3E80

0x8080

0x00FF

0x0000

0x00FF

0x0000

0x18C0

0x0018

0x0000

0x0077

0x4000

0x0002

0x4144

0x5380

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ID1

ID0

0

LIN1

GSTA

SR0

Res

DPDN

APDN

VPDN

GPDN

0

DSTA

SR3

ADL3

GC3

GP3

GS3

GW3

GI3

ASTA

SR2

ADL2

GC2

GP2

GS2

GW2

GI2

VSTA

SR1

ADL1

GC1

GP1

GS1

GW1

GI1

0x40

SRG1

SRG0

SR13

SR12

SR11

SR10

SR9

SR8

SR7

ADM

GC7

GP7

GS7

GW7

GI7

0

SR6

0

SR5

ADS

GC5

GP5

GS5

GW5

GI5

0

SR4

ADG20

GC4

GP4

GS4

GW4

GI4

0

0x46

DAM

0

DAL4

DAL3

DAL2

DAL1

DAL0

ADL0

GC0

GP0

GS0

GW0

GI0

0x4C

0x4E

0

GC6

GP6

GS6

GW6

GI6

0

0x50

0

0x52

0

0x54

0

0x56

0

MLNK

0

L1B2

Res

L1B1

Res

L1B0

Res

0x5C

0x5E

Res

BNK1

BNK0

R34PM

XTAL1

XTAL0

ACSEL

ADCAL

CLKED

SPDL1

GPIV7

Res

VER7

0

CLKEA

SPDL0

GPIV6

Res

VER6

1

Res

GPIV5

Res

MAM

VER5

0

Res

GPIV4

Res

MAL4

VER4

0

Res

GPIV3

XTLP

MAL3

VER3

0

GPBAR

GPWAK

GPMON

GPMIC

SPCHN

SPGBP

SPDSS

SPISO

Res

0x60/1

0x64/1

0x60/2

0x7A

0x7C

0x7E

0

GPIV2

COS2

MAL2

VER2

1

GPIV1

COS1

MAL1

VER1

0

GPIV0

COS0

MAL0

VER0

0

MMD1

MMD0

MDM

MDL4

MDL3

MDL2

MDL1

MDL0

0

1

0

1

0

1

0

1

0

Rev. A | Page 16 of 32

AD1803

CONTROL REGISTER DETAILS

EXTENDED MODEM ID REGISTER

Address D15

0x3C ID1

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

ID0

0

LIN1

0xX00X

A write to this register has no effect on the states of bits within this register, but does trigger Register 0x3E and Bank 2 Register 0x60 to be

cleared to their default states, powering down the AD1803’s codec resources.

Bit Name Description

ID1, ID0

Interface Identification. These bits can be read to determine the AD1803’s serial interface mode of operation. Serial interface mode

is chosen by the states of Pin 13 and Pin 12 when RESET is deasserted (RESET pin driven from low to high) for the first time after

power is applied to the AD1803.

00 = AC link primary (mode chosen if Pin 12 is high and Pin 13 is high on first deassertion of RESET).

01 = AC link secondary (mode chosen if Pin 12 is high and Pin 13 is low on first deassertion of RESET).

10 = AC link secondary (mode chosen if Pin 12 is low and Pin 13 is high on first deassertion of RESET).

11 = DSP link (mode chosen if Pin 12 is low and Pin 13 is low on first deassertion of RESET).

LIN1

Modem Line 1 Supported. For AC '97 compatibility, this bit returns a 1 when read to indicate that the AD1803 supports AC '97

modem line 1 features.

EXTENDED STATUS AND CONTROL REGISTER

Address D15 D14 D13 D12 D11

D10

D9

D8

D7 D6 D5 D4 D3

D2

D1

D0

Default

0x3E

Res¹Res¹Res¹Res¹DPDN APDN VPDN GPDN

0

DSTA ASTA VSTA GSTA 0xFF00

¹Res = reserved bit. To ensure future compatibility, reserved bits should be set to 0 when written and ignored when read.

RESET

This register is forced to its default when power is first applied to the AD1803, the

any value.

pin is driven low, or Register 0x3C is written with

Bit Name

Description

DPDN

DAC Power-Down. When this bit is set to 1 (default), all DAC resources within the AD1803 are powered down, and all DAC data sent

over the serial interface is ignored. When this bit is set to 0, the digital DAC resources are powered up. The analog DAC resources are

powered up only if the voltage reference of the AD1803 is powered up (Bit VPDN in this register is set to 0), and the analog codec of

the AD1803 is selected as the partner to the digital codec of the part (Bit ACSEL in Register 0x5C is set to 0).

0 = Enable digital DAC resources; conditionally enable analog DAC resources.

1 = Power-down all AD1803 DAC resources (default).

APDN

ADC Power-Down. When this bit is set to 1 (default), all ADC resources within the AD1803 are powered down, and all ADC data-words

sent out of the AD1803 over the serial interface are midscale (zero) and tagged invalid if the serial interface is configured in an AC '97

mode. When this bit is set to 0, the digital ADC resources within the AD1803 are powered up. The analog ADC resources within the

AD1803 are powered up only if both the voltage of the AD1803 reference is powered up (Bit VPDN in this register is set to 0), and the

analog codec of the AD1803 is selected as the partner to the digital codec of the part (Bit ACSEL in Register 0x5C is set to 0). Each

time the analog codec is powered up, an ADC dc offset calibration is automatically initiated. This calibration requires approximately

104 sample periods (defined by Register 0x40). It cannot be started until after the voltage reference is powered up (set Bit VPDN in

this register to 0), which requires about 48 ms. Bit VSTA in this register can be polled first to determine if the voltage reference is

powered up and then Bit ADCAL in Register 0x5C can be polled to determine if calibration is complete. During calibration, codec

sample rate, ADC source, and ADC gain level must not be changed.

0 = Enable AD1803 digital ADC resources; conditionally enable AD1803 analog ADC resources.

1 = Power-down all AD1803 ADC resources (default).

VPDN

Voltage Reference Power-Down. Writes to this bit initiate codec voltage reference power-up and power-down sequences. Bit VSTA in

this register can be polled to monitor current voltage reference status. Until the voltage reference is powered up, the analog ADC and

DAC channels of the AD1803 ignore the settings of Bit APDN and Bit DPDN and the part remains powered down.

0 = Enable voltage reference.

1 = Power-down voltage reference (default).

Rev. A | Page 17 of 32

AD1803ꢀꢀ

Bit Name

Description

GPDN

GPIO Power-Down. Setting this bit affects the behavior of the AD1803 only when it is configured in an AC '97 mode (see Register

0x3C). This bit determines whether the logic levels received on the general-purpose input/output (GPIO) pins are reflected on the

bits in Slot 12 of the AC '97 link, and whether or not the states of bits in Slot 12 determine the logic levels to drive out of GPIO pins

that are configured as outputs. See Bit SPGBP in Register 0x5E for mapping. Contrary to the AC '97 specification, the setting of this bit

does not actually control the power-up/power-down state of the GPIO pins. AD1803 GPIO pins are powered up and perform the

functions they are assigned by programming Register 0x4C through Register 0x54 and Register 0x5E.

0 = Slot 12 output bits reflect logic levels received on GPIO pins. Slot 12 input bits determine logic bevels to drive out GPIO pins

configured as outputs.

1 = Slot 12 output bits all 0 (default). Slot 12 input bits are ignored.

DSTA

ASTA

VSTA

DAC Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for DAC power-up/power-down status

changes initiated by writes to Bit DPDN in this register. Because the AD1803 responds to a write of Bit DPDN before it is possible to

read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no effect on AD1803

behavior.

ADC Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for ADC power-up/power-down status

changes initiated by writes to Bit APDN in this register. Because the AD1803 responds to a write of Bit APDN prior to it being possible

to read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no effect on

AD1803 behavior.

Voltage Reference Status. This bit can be polled to monitor the status of the codec voltage reference of the AD1803. When read as a

0, the voltage reference is powered down or in the process of powering up. When read as a 1, the voltage reference is powered up or

in the process of powering down. Approximately 48 ms after Bit VPDN in this register is set to a 0, this bit transitions from a 0 to a 1

indicating that the voltage reference is fully powered up. Approximately 0.8 ms after VPDN is set to a 1, this bit transitions from a 1 to

a 0 indicating that the voltage reference is fully powered-down. If a clock is driven onto the XTALI pin (rather than generated by a

crystal placed between the XTALI pin and XTALO pin), and it is desired to stop this clock for additional system power savings, stop the

clock after this bit falls to 0. Writes to this bit have no effect on the behavior of the AD1803.

GSTA

GPIO Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for DAC power-up/power-down

status changes initiated by writes to Bit GPDN in this register. However, since the AD1803 responds to a write of Bit GPDN prior to it

being possible to read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no

effect on the behavior of the AD1803.

LINE DAC/ADC SAMPLE RATE CONTROL REGISTER

Address D15

0x40 SRG1

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

SRG0

SR13

SR12

SR11

SR10

SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 0x3E80

This register is forced to its default only when power is first applied to the AD1803. Do not write to this register while an ADC calibration is in

progress (see Bit APDN in Register 0x3E and Bit ADCAL in Register 0x5C).

When the AD1803 serial interface is configured in DSP mode, writes to the lower byte of this register are temporarily placed in a holding

register and do not actually take effect until the upper byte is written. This ensures that the 16-bit sample rate only takes effect as a whole.

Reads of the lower byte of this register return the contents of this holding register that do not necessarily reflect the current sample rate.

Bit Name

Description

SRG1,

SRG0

Sample Rate Granularity. These bits select the LSB weighting of the Bits SR[13:0] (Sample Rate Select). These bits select a

fundamental LSB weighting of either 1 Hz, 8/7 Hz, or 10/7 Hz for Bits SR[13:0].

00 = SR[13:0] LSB weight is 1 Hz.

01 = SR[13:0] LSB weight is 8/7 Hz.

10 = SR[13:0] LSB weight is 10/7 Hz.

11 = Reserved.

SR13 to

SR0

Sample Rate Select. Bits SRG[1:0] (Sample Rate Granularity), these bits define the sample rate for both the ADC and DAC codec

channels. Permitted settings of SR[13:0] range from 6400 to 16000 when SRG[1:0] = 00, 5600 to 14,000 when SRG[1:0] = 01, and

4480 to 11,200 when SRG[1:0] = 10. The default sample rate is 16,000 Hz.

Rev. A | Page 18 of 32

AD1803ꢀ

DAC/ADC LEVEL CONTROL REGISTER

Address D15

D14 D13 D12

D11

D10

D9

D8

D7

D6 D5

D4

D3

D2

D1

D0

Default

0x46 DAM

0

DAL4 DAL3 DAL2 DAL1 DAL0 ADM

0

ADS ADG20 ADL3 ADL2 ADL1 ADL0 0x8080

This register is forced to its default only when power is first applied to the AD1803.

The states of Bit ADS, Bit ADG20, and Bit ADL3 to Bit ADL0 in this register must not be changed while an ADC calibration is in progress if

the analog codec of the AD1803 is in use (see Bit APDN in Register 0x3E and Bit ADCAL in Register 0x5C).

Bit Name

Description

DAM

DAC Mute.

0 = DAC output enabled.

1 = DAC output muted (forced to midscale) (default).

DAL4 to DAL0

DAC Attenuation Level Select. Least significant bit represents −1.5 dB. This attenuation is valid when the AD1803’s analog

codec is used with the digital codec of the AD1803 (Bit ACSEL in Register 0x5C = 0).

00000 = +12.0 dB gain (default).

11111 = −34.5 dB attenuation.

ADC Mute.

0 = ADC samples passed.

1 = ADC samples substituted with midscale (0) data (default).

Analog ADC Input Select. The state of this bit has no effect on ADC behavior unless Bit ACSEL in Register 0x5C is set to 0

(default). This selects the analog codec of the AD1803 to partner with the digital codec of the part. If this bit is used to select

the MIC input as the ADC input of the AD1803, Pin 15 must first be assigned to serve as this MIC input rather than its default

role as a GPIO pin. This is done by setting Bit GPMIC in Register 0x5E to 1.

ADM

ADS

0 = Pin 16 (Rx input) selected as AD1803 ADC input source (default).

1 = Pin 15 (MIC input) selected as AD1803 ADC input source (requires GPMIC in Register 0x5E set to 1).

ADG20

AD1803 Analog ADC 20 dB Gain Enable. The state of this bit has no effect on ADC behavior unless Bit ACSEL in Register 0x5C is

set to 0 (default). This selects the analog codec to partner with the digital codec. Total ADC gain is the summation due to this

bit and Bit ADL3 to Bit ADL0.

0 = 0 dB gain (default).

1 = 20 dB gain.

ADL3 to ADL0

AD1803 ADC Gain Level Select. The state of these bits has no effect on ADC behavior unless Bit ACSEL in Register 0x5C is set to

0 (default). This selects the AD1803’s analog codec to partner the AD1803’s digital codec.

0000 = 0.0 dB gain (default).

1111 = 22.5 dB gain.

Rev. A | Page 19 of 32

AD1803

GPIO PIN CONFIGURATION REGISTER

Address D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x4C

0

GC7

GC6

GC5

GC4

GC3

GC2

GC1

GC0

0x00FF

This register is forced to its default only when power is first applied to the AD1803.

Bit Name Description

GC7 to

General-Purpose I/O Pin Configuration. These bits define the directionality of GPIO pins with corresponding numbers. By default, all

GC2, GC0 GPIO pins serve as inputs, but with weak (~100 μA with a 3.3 V supply, ~140 μA with a 5.0 V supply) pull-up devices internal to the

AD1803 enabled. See Register 0x4E to disable these weak pull-up devices. Note that GPIO Pin 1 is always an input and cannot serve

as an output. Also, note that bits in this register are ignored if the GPIO pin they control has been assigned to serve an alternate

special purpose (see bits in Register by more than 0.3 V). GPIO Pin 1 is sourced by the analog supply (Pins AVDD and AGND). All

other GPIO pins are sourced by the digital supply (Pin DVDD and Pin DGND).

0 = GPIO pin serves as an output.

1 = GPIO pin serves as an input (default).

GC1

GPIO Pin 1 is always an input (default=1) and cannot serve as an output. Any writes to this register will be ignored.

GPIO PIN POLARITY/TYPE REGISTER

Address D15

D14

D13

D12

D11

D10

D9 D8 D7

GP7

D6

D5

D4

D3

D2

D1

D0

Default

0x4E

0

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0x00FF

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

GP7 to GP0

GPIO Input Polarity/Output Driver Type Select. These bits control GPIO pins with corresponding numbers. The effect they have is

dependent on GPIO pin directionality (see Register 0x4C). When a GPIO pin serves as an input, these bits select the logic level

necessary to set a sticky status bit which is used to trigger an interrupt (see Registers 0x50 and 0x52). When serving as an input,

these bits determine whether a weak pull-up receives a low, the weak pull-up is disabled. If an input is set to active low, and

therefore nominally receives a high, the weak pull-up is enabled. Meanwhile, when a GPIO pin serves as an output, these bits

determine whether a CMOS or open drain with weak pull-up driver is activated.

If a GPIO pin is defined as an input (corresponding GC bit in Register 0x4C is set to 1)

0 = Input is active high, weak pull-up disabled.

1 = Input is active low, weak pull-up enabled (default).

If a GPIO pin is defined as an output (corresponding GC bit in Register 0x4C is set to 0).

0 = Output driver is CMOS.

1 = Output driver is open drain with weak pull-up enabled (default).

GPIO STICKY PIN REGISTER

Address D15

D14

D13

D12

D11

D10

D9 D8 D7

GS7

D6

D5

D4

D3

D2

D1

D0

Default

0x50

0

GS6

GS5

GS4

GS3

GS2

GS1

GS0

0x0000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name Description

GS7 to GS0 GPIO Sticky Control. These bits control GPIO pins with corresponding numbers. They determine whether a read of Register 0x54

returns either the current logic level received on a GPIO pin, or a sticky status bit which indicates if a selected logic level (see

Register 0x4E) has been received since this sticky status bit was last cleared. Sticky status bits are cleared by writes to their

associated control bits in Register 0x54, and whenever the current GPIO pin received logic level is selected as the Register 0x54

return value.

0 = Reads of Register 0x54 return current state of GPIO pin, sticky status bit cleared (default).

1 = Reads of Register 0x54 return a sticky status bit set by GPIO pin level selected by Register 0x4E.

Rev. A | Page 20 of 32

AD1803

GPIO PIN WAKE-UP MASK

Address D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x52

0

GW7 GW6 GW5 GW4 GW3 GW2 GW1 GW0 0x0000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name Description

GW7 to

GW0

GPIO Wake-Up Mask Control. A GPIO pin triggers an interrupt providing that it is enabled to cause interrupts by the corresponding

numbered bit in this register, and it has its associated sticky status bit set. For the associated sticky status bit to be set, the GPIO

input must first be enabled to be sticky by the GS bit in Register 0x50, and then the logic level selected by a GP bit in Register 0x4E

must be received on the associated GPIO pin. When an interrupt is triggered, Pin 12 is driven high providing Pin 12 is enabled to

serve as an interrupt output (see GPWAK bit in Register 0x5E). If the AD1803’s serial interface is configured in an AC '97 mode,

interrupts are also reflected on Bit 0 of Slot 12 of each frame, even if Pin 12 is not enabled to respond to an interrupt. Also in AC '97

mode, if RESET is asserted when an interrupt is triggered, the SDATA_IN pin is driven from low (default during RESET) to high to

wake an AC '97 controller. Refer to the AC '97 specification for complete details. Activated GPIO pins can trigger interrupts. The

source of the interrupt can be determined by reading Register 0x54.

0 = GPIO pin disabled from causing interrupts (default).

1 = GPIO pin enabled to cause interrupts (providing corresponding GS bit in Register 0x50 = 1).

GPIO PIN STATUS REGISTER

Address D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x54

0

GI7

GI6

GI5

GI4

GI3

GI2

GI1

GI0

0x00FF

This register is forced to its default only when power is first applied to the AD1803.

Bit Name Description

GI7 to GI0 GPIO Status. Each bit corresponds with a GPIO pin of the same number. When a bit is read, it reflects either the current logic level

received on a GPIO pin or the state of the sticky status bit that is set if a selected logic level has been received on a GPIO pin since

the last time the sticky status bit was cleared (see Register 0x4E, Register 0x50, and Register 0x52). When a bit is written with a 0, the

associated sticky status bit is cleared. Note that it is not necessary to write a 1 to a bit after writing a 0 since it is the act of writing a 0

to a bit itself that clears the sticky status bit. When a bit is written with a 1, the associated sticky status bit is unaffected. If the

AD1803’s serial interface is configured in DSP mode (see Register 0x3C), writes to this register also control the logic level driven out

on the GPIO pins provided that a GPIO pin is configured as an output (see Register 0x4C) and is serving as a GPIO pin (see

Register 0x5E). If the AD1803’s serial interface is configured in an AC '97 mode, GPIO output states are determined by the bits in ac

link slot 12 rather than writes to this register (see Bit SPGBP in Register 0x5E and the AC '97 specification for further details).

MISCELLANEOUS MODEM AFE STATUS AND CONTROL REGISTER

Address D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x56

0

MLNK

0

LIB2

LIB1

LIB0

0x0000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

MLNK

AC Link Disable. This bit has no effect on the behavior of the AD1803 unless it is configured as an AC '97 primary device (see

Register 0x3C). When this is the case, writing a 1 to this bit puts the AC '97 link interface into a sleep mode by causing the AD1803

to drive the BIT_CLK pin low within one BIT_CLK period after the completion of Slot 2 (the slot in which writes to control registers

occur). While in this sleep mode, an AC '97 controller can wake the AD1803 interface either by pulsing the SYNC pin, or by

asserting and then deasserting the RESET pin. Refer to the AC '97 specification for complete details. Note that the interface is put

to sleep, regardless of interface mode, if the RESET pin is asserted.

LIB2 to LIB0

Loopback Modes.

000 = No loopback. Normal signal pathways engaged (default).

001 = Analog loopback. Analog ADC output to analog DAC input (at analog interface to digital codec).

010 = Local loopback. DAC output to ADC input (at analog pins).

011 = Digital loopback. Digital DAC output to digital ADC input (at digital interface to analog codec).

1xx = No loopback. Normal signal pathways engaged.

Rev. A | Page 21 of 32

AD1803

CONFIGURATION 1 REGISTER

Address D15 D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x5C

Res¹BNK1 BNK0 R34PM XTAL1 XTAL0 ACSEL ADCAL CLKED CLKEA Res¹Res¹Res¹Res¹Res¹Res¹0x18C0

¹Res = reserved bit. To ensure future compatibility, reserved bits should be set to 0 when written and ignored when read.

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

BNK1, BNK0

Register Bank Select. Since the AC '97 specification lacks sufficient vendor specified register space to control all extended

features of the AD1803, some control registers must be accessed indirectly using register banks selected by these bits.

00 = Reserved.

01 = Bank 1: AD1803 I/O control registers.

10 = Bank 2: AD1803 codec control registers.

11 = Reserved.

R34PM

RESET Power Mode Select. When this bit is set to 0, the AD1803 is completely powered down whenever the RESET pin is

asserted (driven low). This bit overrides the settings of all other power control bits. When this bit is set to 1, various features of

the AD1803 remains powered up during RESET as individually enabled by their related control bits (see other bits in this

register)

0 = During RESET, power down the AD1803.

1 = During RESET, allow enabled features to remain powered up (default).

XTAL1, XTAL0 Clock Identification. With the exception of the serial interface, which is always clocked by the BIT_CLK pin, these bits identify the

clock source and frequency to be used by all other resources within the AD1803. The default setting of these bits is dependent

on the chosen AD1803 serial interface configuration (see Register 0x3C). There are three reasons why it might be desirable to

alter from the default setting:

If the BIT_CLK is the default clock source, but the BIT_CLK has excessive edge noise that interferes with codec performance, than

a crystal or other clean clock source could be taken from the XTALI pin instead.

If the BIT_CLK is the default clock source, but the BIT_CLK is stopped during a period of time when AD1803 functionality is still

necessary, such as ring validation and wake-up signaling during D3-Cold, then the clock source could be switched to the XTALI

pin while the BIT_CLK is suspended.

If the XTALI is the default clock source and the default crystal frequency is not the one actually used, the correct crystal

frequency must be identified prior to the ADC, DAC, or barrier interface being enabled (see Register 0x3E). Also note that if

the AD1803 is the master of BIT_CLK (serial interface in AC '97 primary mode or DSP mode), BIT_CLK cannot be at its proper

frequency until the AD1803 is informed what clock frequency it is receiving. Until then, the BIT_CLK frequency is off by the

ration of the actual to the default assumed frequency. As a final caution, if the clock frequency is chosen to be 32.768 MHz

(setting 01 of these bits), and the AD1803 is chosen to be an AC '97 primary device, the AD1803 is incapable of producing the

AC '97 specified 12.288 MHz BIT_CLK because there is no integer divisor between these frequencies. In this situation, the

AD1803 violates the AC '97 specification and outputs a 16.384 MHz BIT_CLK.

00 = 12.288 MHz from BIT_CLK (default if in an AC '97 secondary mode).

01 = 32.768 MHz from XTALI.

10 = 24.576 MHz from XTALI (default if in either AC '97 primary mode or DSP mode).

11 = 12.288 MHz from XTALI.

ACSEL

Analog Codec Select. This bit selects the analog codec that is used in conjunction with the digital codec of the AD1803.

0 = AD1803 analog codec selected (default).

1 = Reserved.

ADCAL

ADC Calibration/Recalibration. Writing a 1 to this bit initiates a dc offset calibration of the codec’s ADC channel, which requires

approximately 104 sample periods (defined by Register 0x40). ADC calibration is automatic each time the analog ADC of the

AD1803 is enabled. When this bit is read, a 1 is returned if calibration is in progress and a 0 is returned when calibration is

completed or not in progress. During calibration, the ADC returns midscale (zero) samples. During calibration, codec sample

rate, ADC source, and ADC gain must not be changed.

CLKED

CLK_OUT Enable While RESET Is Deasserted (Driven High). This bit controls the operation of the CLK_OUT pin while the RESET

pin is deasserted. See Bit CLKEA for CLK_OUT operation while RESET is asserted. Each time RESET is deasserted (driven from low

to high), this bit is automatically set to 1 to ensure that a clock is always available to hardware outside the AD1803 after a RESET.

If this clock is not needed, this bit should be set to 0 by software after each RESET for optimal power savings.

0 = When RESET is deasserted, CLK_OUT is driven low.

1 = When RESET is deasserted, CLK_OUT reflects clock on XTALI (default after deassertion of RESET).

Rev. A | Page 22 of 32

AD1803

Bit Name

Description

CLKEA

CLK_OUT Enable While RESET Is Asserted (Driven Low). This bit controls the operation of the CLK_OUT pin while the RESET pin

is asserted. See Bit CLKED for CLK_OUT operation while RESET is deasserted. If Bit R34PM is set to 0, this bit is ignored, and

CLK_OUT is driven low while RESET is asserted.

0 = When RESET is asserted, CLK_OUT is driven low.

1 = When RESET is asserted, CLK_OUT reflects clock received on XTALI (providing R34PM set to 1) (default).

CONFIGURATION 2 REGISTER

Address

D15

D14

D13

D12

GPMIC

D11

SPCHN

D10

SPGBP

D9

SPDSS

D8

SPISO

D7

SPDL1

D6

SPDL0

D5

Res¹

D4

D3

D2

D1

D0

Default

0x5E

GPBAR

GPWAK

GPMON

Res¹Res¹Res¹Res¹Res¹0x0018

¹Res = reserved bit. To ensure future compatibility, reserved bits should be set to 0 when written and ignored when read.

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

GPBAR

GPIO Interface Select.

0 = Use AD1803 Pin 24, Pin 23, and Pin 22 as G[5], G[6], and G[7] respectively (default).

1 = Reserved.

GPWAK

GPMON

GPMIC

SPCHN

G[3]/Wake Interrupt Signal Select.

0 = Use AD1803 Pin 12 as GPIO[3] (default).

1 = Use AD1803 Pin 12 as Wake Interrupt (see Register 0x52).

GP[4]/Monitor Output Select.

0 = Use AD1803 Pin 11 as GPIO[4] (default).

1 = Use AD1803 Pin 11 as Σ-Δ monitor output (see Register 0x60 Bank 2).

GP[1]/MIC Input Select.

0 = Use AD1803 Pin 15 as G[1] (default).

1 = Use AD1803 Pin 15 as analog MIC input (see Bit ADS in Register 0x46).

Serial Port Chaining Mode Enabled. This bit is ignored unless the AD1803 is in an AC '97 serial interface

mode (see Register 0x3C). This bit can be used to chain multiple AC '97 devices to a single 4-wire AC '97 link. Consult Analog

Devices, Inc. for further details.

0 = ADI chaining mode disabled (default).

1 = ADI chaining mode enabled.

SPGBP

SPDSS

Serial Port GPIO Bit Placement Select. This bit is ignored unless the AD1803 is configured in an AC '97 serial

interface mode (see Register 0x3C). Writes to this bit take effect on the current serial interface frame.

0 = State of AD1803 G[7] through G[0]0 reflected on Bits [1:4] of Slot 12 (default).

1 = State of AD1803 G[7] through G[0] reflected on Bits [19:12] of Slot 12

Serial Port Data Slot Size Select. This bit is ignored unless the AD1803 is configured in an AC '97 serial interface mode (see Register

0x3C). When set to 1, the four LSBs of all 20-bit data slots are dropped, allowing a simpler connection with a DSP. Writes to this bit

take effect during the current frame, but can distort the current frames slot alignment. As a result, when the state of this bit is

changed, all data slots sent to the AD1803 should be set to zero and all data slots received from the part should be ignored.

0 = Data slots are 20 bits (default).

1 = Data slots are 16 bits.

SPISO

Serial Port Isolate. When this bit is set to 1, the AD1803 serial interface is isolated from the outside system whenever RESET is

asserted. This is achieved by ignoring the signals received on serial interface input pins and driving serial interface output pins

weakly (less than 200 μA), rather than with nominal output drive strengths. This bit should be set to 1 prior to a controller on the

other side of the part’s serial interface losing power if the AD1803 continues to receive power. It can also be set to 1 to save power

if the part’s serial interface input pins continue to make transitions while RESET is asserted.

SPDL1,

SPDL0

Serial Port Data Slot Location Select. These bits are ignored unless the AD1803 is configured in an AC '97 serial interface mode (see

Register 0x3C). Writes to these bits take effect during the current frame, but data sent during the current frame can be distorted or

dropped. For reliable operation, these bits should not be changed while the codec is enabled.

00 = AD1803 uses Slot 5 to send and receive sample data (default).

01 = AD1803 uses Slot 10 to send and receive sample data.

10 = AD1803 uses Slot 11 to send and receive sample data.

11 = Reserved.

Rev. A | Page 23 of 32

AD1803

BANK 1—GPIO INITIAL STATES REGISTER

Address D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

GPIV7 GPIV6 GPIV5 GPIV4 GPIV3 GPIV2 GPIV1 GPIV0 0x0000

This register is forced to its default only when power is first applied to the AD1803.

D5

D4

D3

D2

D1

D0

Default

0x60

0

Bit Name

Description

GPIV7 to

GPIV0

GPIO Pin Initial Value. When RESET is deasserted for the first time after power is applied to the AD1803, the states of all GPIO pins

are sampled and stored in this register. Writes to this register and subsequent logic level changes on GPIO pins have no effect on the

values reported by reads of this register. While the sampled states of GPIO Pin 2 and Pin 3 are used by the AD1803 to determine serial

interface mode (see Register 0x3C), all remaining GPIO pins are available for use, if beneficial, as identification bits to host software or

hardware. Immediately after power is first applied to the AD1803, all GPIO pins by default serve as inputs, but with weak pull-up

devices internal to the enabled AD1803. Since these pull-up devices have an effective resistance of about 30 kΩ, external resistors of

less than 8 kΩ tied to digital ground (DGND pin) must be used for logic lows to be sampled.

BANK 1—CLOCK PAD CONTROL REGISTER

Address D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x64

0

Res¹Res¹Res¹Res¹XTLP COS2

COS1

COS0

0x0077

¹Res = reserved bit. To ensure future compatibility, reserved bits should be set to 0 when written and ignored when read.

This register is forced to its default only when power is first applied to the AD1803.

Bit Name

Description

XTLP

Crystal Oscillator Low Power Mode Enable. Depending on board design and crystal used, this bit can be set to 1 to engage

a crystal oscillator low power mode, which saves up to 0.7 mA. This mode reduces the amount of energy that an AD1803

provides to keep a crystal oscillating, but otherwise has no effect on AD1803 behavior. If a clock is driven onto the XTALI pin

from an external source, rather than generated by a crystal connected between the XTALI pin and XTALO pin, the optimal

setting for this bit is 1, although with only a slight power benefit.

0 = Normal power mode (default).

1 = Low power mode.

COS2 to COS0

CLK_OUT Pin Drive Strength Select. This bit can be used to reduce EM emissions, or three-state the CLK_OUT pin. 000 = 0% of

full drive strength (pad three-stated).

001 = 13% of full drive strength.

010 = 25% of full drive strength.

011 = 38% of full drive strength.

100 = 63% of full drive strength.

101 = 75% of full drive strength.

110 = 88% of full drive strength.

111 = 100% of full drive strength (default).

Rev. A | Page 24 of 32

AD1803

BANK 2—MONITOR OUTPUT CONTROL REGISTER

Address D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

D0

Default

0x62

MMD1 MMD0 MDM MDL4 MDL3 MDL2 MDL1 MDL0 Res Res MAM MAL4 MAL3 MAL2 MAL1 MAL0 0x4000

This register is forced to its default only when power is first applied to the AD1803.

Bit Name Description

MMD1,

MMD0

Monitor Output Mode. The monitor output of the AD1803 provides a programmable mix of the ADC and DAC signals passing

through the codec of the part. Pin 11 serves as the monitor output, providing Bit GPMON in Register 0x5E is set to 1. Otherwise,

Pin 11 serves its default role as a GPIO pin. When the monitor output is enabled (powered up) using Bits MDM[1:0], the monitor

output is in the form of digital Σ-Δ modulator bit stream with a maximum edge rate (carrier) of 512 kHz. One of two different Σ-Δ

modulator types can be activated: Either a first order that generates 6 dB more signal swing than the other choice but has more

inband noise and idle tones or a third order that has half the signal swing but significantly superior inband noise and negligible

idle tones. To extract the signal from the Σ-Δ modulator noise, it is recommended that the monitor output be filtered by connecting

Pin 11 to a 1 kΩ resistor in series with a parallel 4.7 kΩ resistor and 100 nF capacitor combination which is then tied to digital ground

(DVDD pin). This filter, with the output taken from the middle node, has a 1500 Hz corner to filter out high frequency Σ-Δ noise. It

generates an approximate 1 V p-p output when using a 5 V digital supply with the monitor output configured as a first order (MMD1 and

MMD0 set to 10) if the filter output load is greater than or equal to 20 kΩ. Other filter networks can also be used, perhaps to save

power or increase effective output signal swing, but for long term reliability, care must be taken to ensure that the monitor output

never sources more than 5 mA. The recommended filter dissipates approximately 1 mA.

00 = Reserved.

01 = Monitor output powered down and driven low (default).

10 = Monitor enabled, first-order Σ-Δ output, signal swing: 0% to 100% ones (best signal amplitude).

11 = Monitor enabled, third-order Σ-Δ output, signal swing: 25% to 75% ones (best signal SNR post filter).

MDM

Monitor Output DAC Mix Mute. If both ADC and DAC mix are muted, the monitor output should be powered down (MDM[1:0] set to

10) to achieve a quieter mute.

0 = DAC mix level determined by bits MDL4 to MDL0 (default).

1 = DAC mix is muted.

MDL4 to

MDL0

Monitor Output DAC Mix Level. Unless muted by the MDM bit in this register, these bits control the amount of DAC signal that is

mixed into the monitor output. Representation is two’s complement with an LSB weighting of 3 dB and a permissible range of +45

dB to −18 dB. If the analog codec of the AD1803 is in use (ACSEL set to 0), the DAC signal mixed is taken before this attenuation is

applied. In either case, the DAC signal mixed is always taken before the mute bit DAM in Register 0x46 is applied.

01111 = +45 dB.

00000 = 0 dB (default).

11010 = −18 dB.

MAM

Monitor Output ADC Mix Mute. If both ADC and DAC mix are muted, the monitor output should probably be powered down

(MAM[1:0] set to 10) to achieve a quieter mute.

0 = ADC mix level determined by bits MAL[4:0] (default).

1 = ADC mix is muted.

MAL4 to

MAL0

Monitor Output ADC Mix Level. Unless muted by the MAM bit in this register, these bits control the amount of ADC signal that is

mixed into the monitor output. Representation is two’s complement with an LSB weighting of 3 dB and a permissible range of

+45 dB to −18 dB. The ADC signal mixed is always taken after the gain specified by Bit DAL4 to Bit DAL0 in Register 0x46 is applied,

but before the mute bit ADM in Register 0x46 is applied.

01111 = +45 dB.

00000 = 0 dB (default).

11010 = −18 dB.

VERSION ID REGISTER

Address D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7A

0

VER7 VER6 VER5 VER4 VER3 VER2 VER1 VER0 0x0002

Bit Name

Description

VER7 to VER0 AD1803 Version. Writes to this register have no effect. The latest version of the AD1803 is 0x0002.

Rev. A | Page 25 of 32

AD1803

VENDOR ID1 REGISTER

Address D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7C

0

1

0

1

0

1

0

1

0

0x4144

Writes to Register 0x7C and Register 0x7E have no effect. When read, Address 0x7C and Address 0x7E return 0x4144 and 0x5380, respectively,

which, taken together, map to ADS in ASCII followed by Address 0x80. ADS is registered in the AC '97 specification to identify Analog

Devices as the vendor, and the final byte of Address 0x80 is used to identify the AD1803 (vendor selected value).

VENDOR ID2 REGISTER

Address D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7E

0

1

0

1

0

1

0

0x5380

Rev. A | Page 26 of 32

AD1803

APPLICATIONS

APPLICATION CIRCUITS

SPEAKER

LM386

3.3V

AUX

AD1803 MODEM

LITELINK DAA CPC5610

VCC

3.3V

MODEM DATAPUMP

CORE-VDD

3.3V

AUX

G[4]/MOUT

DVDD

Tx

T^X–

T^X+

AVDD

1

2

3

4

LINK-VDD

R^X–

R^X+

RESET

BIT_CLK

SYNC

Rx

FLAG

BIT_CLK

SYNC

G1/MIC

G[0]

XTALO

XTALI

OH

SDATA_OUT

SDATA_IN

SDATA_OUT

SDATA_IN

RING

CID

911_DETECT

G[5]

G[6]

G[7]

RING

CID

RJ11

CLK_OUT

XTALO

XTALI

G[2]

24.576MHz

G[3]WAKE

PRIMARY CODEC ID = 00

LMV331

Figure 14. PC/Embedded Modem

AD1881A AUDIO CODEC

LINE_OUT

DVDD

TO SPEAKER_OUT JACK

FROM LINE_IN JACK

AGND

3.3V

AUX

EAPD/CIN

5V

AVDD

LINE_IN

PC_BEEP

CD_IN

RESET

BIT_CLK

SYNC

SDO

SDI[0]

SDI[1]

FROM CD_IN ATAPI CONNECTOR

FROM MIC JACK

RESET

AMR/

CNR/

ACR

MIC

BIT_CLK

SYNC

CONNECTOR

SDATA_OUT

SDATA_IN

CS1

CS0

XTALO

XTALI

PHONE_IN

PRIMARY CODEC ID = 00

3.3V

AUX

AD1803 MODEM

LITELINK DAA CPC5610

VCC

3.3V

AUX

G[4]/MOUT

DVDD

Tx

TX–

Tx+

AVDD

1

2

3

4

RX–

RESET

Rx

Rx+

BIT_CLK

G1/MIC

G[0]

SYNC

OH

SDATA_OUT

SDATA_IN

RING

CID

G[5]

RING

CID

RJ11

G[6]

CLK_OUT

XTALO

XTALI

G[7]

G[2]

24.576MHz

G[3]WAKE

SECONDARY CODEC ID = 01

Figure 15. Audio Modem Riser

Rev. A | Page 27 of 32

AD1803

3.3V

AUX

AD1803 AUDIO CODE

G[4]/MOUT

DVDD

T1

Tx

AVDD

MONO PHONE

1

2

3

4

+

–

RESET

BIT_CLK

RESET

AMR/

CNR/

ACR

Rx

BIT_CLK

RELAY

HYBRID

SYNC

SDO

SDI[0]

G1/MIC

G[0]

SYNC

OH

CONNECTOR

SDATA_OUT

SDATA_IN

RING

DC HOLD

G[5]

RJ11

G[6]

CLK_OUT

XTALO

XTALI

G[7]

3.3V

G[2]

24.576MHz

G[3]WAKE

RING DETECT

PRIMARY CODEC ID = 00

Figure 16. Modem Riser with Discrete DAA

AD1803 CODEC

3.3V

DVDD

AVDD

CLK_OUT

CLKIN

FL1

RESET

BITCLK

SYNC

RESET

BIT_CLK

SYNC

SCLK

TFS

RFS

DT

SDATA_OUT

SDATA_IN

SDATA_OUT

XTALO

DR

SDATA_IN

24.576MHz

G[2]

XTALI

WAKE

G[3]/WAKE

IRQE/FP4

ADSP-218x

DSP MODE

Figure 17. Interfacing AD1803 to ADSP-218x DSP

AD1881A AUDIO CODEC

AD1803 HANDSET CODEC

RESET

BIT_CLK

SYNC

BIT_CLK

G[2]

BIT_CLK

SYNC

SDO

SYNC

G[3]/WAKE

SDATA_OUT

CHAIN_IN

SDATA_IN

SDI0

PRIMARY CODEC ID = 00

SECONDARY CODEC ID = 10

SDI PIN CONFIGURED FOR

CHAINING

SDI1

AC '97

DIGITAL

CONTROLLER

AD1803 MODEM CODEC

RESET

BIT_CLK

G[2]

SYNC

G[3]/WAKE

SDATA_OUT

SDATA_IN

SECONDARY CODEC ID = 01

Figure 18. Codec Chaining Allows Several Analog Devices AC ‘97 Codecs to be Connected to One AC Link Controller Port

Rev. A | Page 28 of 32

AD1803

the XTALI pin from an external source rather than generated

TYPICAL INITIALIZATION SEQUENCE

IMMEDIATELY AFTER FIRST RESET

by a crystal connected between the XTALI and XTALO pins,

the optimal setting for this bit is 1, although with only a slight

power benefit.

Step 1: Write to Register 0x5C (Configuration 1 Register).

Bits[14:13]—BNK1, BNK0 (register bank select). These bits

should be set to 01 in preparation for Step 2.

Bits[2:0]—COS2 to COS0 (CLK_OUT pin drive strength

select). These bits should be set to select the optimal output

driver strength for the CLK_OUT pin to soften edges and

reduce EMI emissions.

RESET

Bit[12]—R34PM (

have the AD1803 drive a clock out on the CLK_OUT pin while

RESET

power mode select). If it is desired to

is asserted, this bit must be changed from its default

setting of 0 to 1, otherwise, the AD1803 is completely powered

RESET RESET

Step 3: Write to Register 0x5E (Configuration 2 Register).

Bit[14]—GPWAK (G[3]/Wake interrupt signal select). If an

interrupt/wake output signal is desired, this bit must be changed

from its default setting of 0 to 1. This enables Pin 12 to serve

this role rather than a default role as a general-purpose I/O pin.

When serving as an interrupt/wake flag, Pin 12 is driven high

whenever a qualifying event has occurred.

down whenever

is asserted (

pin driven low).

Bits[11:10]—XTAL1, XTAL0 (clock identification): If the clock

presented on pin XTALI is not 24.576 MHz, the default setting

of these bits must be changed to identify the actual XTALI

frequency provided.

Bit[9]—ACSEL (analog codec select). While this bit can be

updated at any time, and even while the codec is enabled, it is

recommended to set this bit prior to enabling the codec. This

bit selects an analog codec used in conjunction with the digital

codec within the AD1803. When set to 0, which is the default,

the analog codec within the AD1803 is used.

Bit[13]—GPMON (G[4]/Monitor output select): If the monitor

output feature is used, this bit must be changed from its default

setting of 0 to 1. This enables Pin 11 to serve this role rather

than a default role as a general-purpose I/O pin. When serving

as a monitor output, Pin 11 outputs a Σ-Δ bit stream consisting

of a selectable mix of the signals present on the ADC and DAC

channels.

Bit[8]—ADCAL (ADC calibration recalibration). Until the

codec is enabled, writes to this bit have little purpose.

Bit[12]—GPMIC (GPI[1]/MIC input select). If a second select-

able ADC input source is desired, the setting of this bit must be

changed from its default of 0 to 1. This switches the role of Pin 15

from a general-purpose input flag to an analog MIC input.

RESET

Bit[7]—CLKED (CLK_OUT enable while

is deasserted).

pin driven high)

to a 1. This enables the CLK_OUT pin to

provide a buffered version of the clock received on the XTALI

RESET

RESET RESET

Immediately after

RESET

is deasserted (

this bit is always

Bit[11], Bit[10], Bit[9], Bit[7], and Bit[6]—SPCHN, SPGBP,

SPDSS, SPDL1, and SPDL0. These bits affect the operation of

the AD1803 only if in an AC '97 serial interface mode.

pin following every deassertion of

this clock low and save power, this bit must be set to 0 after every

RESET

. Therefore, to stop

deassertion of

. Stopping CLK_OUT saves about 1.5 mA

Bit[8]—SPISO (serial port isolate). See the Typical Codec

Power-Down Sequence section for further details.

plus any addition current saved by not driving the board load

that might be present. Note that CLK_OUT can also be

permanently three-stated using bits COS2 to COS0 in Register

0x64 Bank 1.

Step 4: Read Register 0x60 (Bank 1—GPIO Initial States

Register).

RESET

pin driven high), the first time

As

is deasserted (

RESET

Bit[6]—CLKEA (CLK_OUT enable while

is asserted).

after power is applied to the AD1803, the states of all general-

purpose I/O pins are sampled and stored in this register. While

the sampled states of GPIO Pin 2 and Pin 3 are used by the

AD1803 to determine serial interface mode, all remaining GPIO

pins are available for use, if beneficial, as identification bits to

a host software.

This bit must be changed from its default of 0 to 1 if it is desired

to have the CLK_OUT pin provide a clock output while the

RESET RESET

AD1803 is

(

pin driven low). Note that Bit R34PM

can override the behavior selected by the state of this bit.

Step 2: Write to Register 0x64 (Bank 1—Clock Pad Control

Register).

Step 5: Write to Register 0x4C through Register 0x54 (GPIO

Bit[3]—XTLP (crystal oscillator low power mode enable).

Depending on board design and crystal used, this bit can be

set to 1 to engage a crystal oscillator low power mode, which

saves up to 0.7 mA. This mode reduces the amount of energy

that an AD1803 provides to keep a crystal oscillating, but other-

wise has no effect on AD1803 behavior. If a clock is driven onto

control registers).

Rev. A | Page 29 of 32

AD1803

These registers determine the behavior of the GPIO pins of the

AD1803. After power is first applied to the AD1803, all GPIO

pins default as inputs, but with weak (~100 μA) pull-up devices

within the part enabled to pull any floated GPIO pins high. As

needed, these pins can be reconfigured to serve as interrupt

sources, active high or low, sticky or unsticky, or general-purpose

outputs with open-drain or CMOS drivers. The weak pull-up

device can also be disabled to save power. The settings of these

registers, like most registers within the AD1803, are unaffected

Each time the analog codec of the AD1803 is powered up, an ADC

calibration is automatically initiated. This calibration requires

approximately 104 sample periods (defined by Register 0x40),

but can’t be started until after the voltage reference of the part is

powered up (by setting Bit VPDN to 0). The voltage reference

requires about 48 ms to start up. Bit VSTA in this register can be

polled first to determine if the voltage reference is powered up,

and then Bit ADCAL in register 0x5C can be polled to determine

if calibration is completed. During calibration, the codec sample

rate (Register 0x40) and ADC source and gain levels (Bit ADS,

Bit ADG20, and Bit ADL[3:0] in Register 0x46) must not be

changed.

RESET

by a

and are set to their defaults only when power is first

applied to the AD1803. The most practical order is 0x4E, 0x4C,

0x50, 0x54, and finally 0x52.

Bit[9]—VPDN (voltage reference power-down). If the analog

codec of the AD1803 is used, this bit must be set to 0 to power

up the part’s voltage reference. Until the voltage reference is

powered up, the analog codec channels of the AD1803 ignore

the setting of Bit APDN and Bit DPDN and remain powered

down. Once this bit is set to 0, approximately 48 ms are necessary

to power up the voltage reference. Bit VSTA in this register can

be polled to monitor the status of the voltage reference.

Step 6: Write to Register 0x40 (Line DAC/ADC Sample Rate

Control Register) and Register 0x46 (DAC/ADC Level Control

Register).

These registers determine the codec sample rate and channel

attenuation levels. While these register can be updated at any

time, including while the codec is enabled, establishing desired

settings prior to enabling the codec is recommended.

TYPICAL CODEC POWER-UP SEQUENCE

Bit[8]—GPDN (GPIO power-down). Contrary to this bit’s

name, its setting has no effect on the operation of the AD1803

when configured in DSP mode. When the AD1803 is configured

in an AC '97 mode, this bit must be set to 0 for Slot 12 to access

GPIO pins.

Step 7: Write to Register 0x3E (Extended Status and Control

Register).

Bit[11]—DPDN (DAC power-down). This bit must be set to 0

for the DAC codec channel of the AD1803 to be enabled. While

this bit is set to 1 (default), all DAC resources within the part are

powered down and all data words sent to the AD1803 over the

serial interface are ignored. When this bit is set to 0, the digital

DAC resources within the part are powered up. The analog DAC

resources within the part are powered up only if the voltage

reference of the AD1803 is powered up (Bit VPDN in this

register is set to 0), and the analog codec of the AD1803 is

selected as the partner to the digital codec of the part

(Bit ACSEL in register 0x5C is set to 0).

Bit[3]—DSTA (DAC status). This bit exists solely for AC '97

compatibility. Its purpose is to provide a handshake for DAC

power-up/power-down status changes initiated by writes to

Bit DPDN. However, because the AD1803 responds to a write

of Bit DPDN prior to it being possible to read this bit in a

following serial interface frame, there is no reason to poll this

status bit.

Bit[2]—ASTA (ADC status). This bit exists solely for AC '97

compatibility. Its purpose is to provide a handshake for ADC

power-up/power-down status changes initiated by writes to

Bit APDN. Because the AD1803 responds to a write of Bit APDN

prior to it being possible to read this bit in a following serial

interface frame, there is no reason to poll this status bit.

Bit[10]—APDN (ADC power-down): This bit should be set to

0 for the ADC codec channel of the part to be enabled. While

this bit is set to 1 (default), all ADC resources within the AD1803

are powered down, and all data words sent out of the part over

the serial interface are set to midscale (zero). When this bit is

set to 0, the digital ADC resources within the AD1803 are

powered up. The analog ADC resources within the part are

powered up only if the voltage reference of the AD1803 is

powered up (Bit VPDN in this register is set to 0), and the analog

codec of the AD1803 is selected as the partner to the digital

codec of the part (Bit ACSEL in Register 0x5C is set to 0).

Bit[1]—VSTA (voltage reference status). This bit can be polled

to monitor the status of the voltage reference. When read as a 0,

the voltage reference is either powered down or in the process

of powering up. When read as a 1, the voltage reference is either

powered up or in the process of powering down. Approximately

48 ms after VPDN is set to a 0, this bit transitions from a 0 to a

1 indicating that the voltage reference is powered up.

Rev. A | Page 30 of 32

AD1803

Bit[0]—GSTA (GPIO status). This bit exists solely for AC '97

compatibility. Its purpose is to provide a handshake for power-

up/power-down status changes initiated by writes to Bit GPDN.

Because the AD1803 responds to a write of Bit GPDN prior to

it being possible to read this bit in a following serial interface

frame, there is no reason to poll this status bit.

potential clicks caused by the DAC output tracking the voltage

reference as it falls to 0 volts when powered down, and rises to

~1.25 V when powered back up.

Bit[8]—GPDN (GPIO power-down). This bit can be set to any

value because it has no effect on AD1803 operation when in

DSP mode.

Step 8: Write to Register 0x5C (Configuration 1 Register).

Bit[1]—VSTA (voltage reference status). This bit can be polled

to determine the status of the part’s voltage reference. When

read as a 0, the voltage reference is either powered down or in

the process of powering up. When read as a 1, the voltage

reference is either powered up or in the process of powering

down. Within 0.8 ms after VPDN is set to 0, this bit transitions

from 1 to 0, indicating that the voltage reference is completely

powered down. If a clock is driven onto the XTALI pin, and it is

desired to stop this clock for additional system power savings,

this clock must not be stopped until after this bit falls to a 0.

The purpose of this write is to change the register bank selection

in preparation for Step 9. The value written to Register 0x5C at

this time should be identical to the value from Step 1, except

with Bits[14:13] (BNK1, BNK0) set to 10.

Step 9: Write to Register 0x62 Bank 2 (Monitor Output Control

Register).

Writes to this register have no purpose unless a pin has been

assigned to serve as a monitor output (see Step 3 in the Typical

Initialization Sequence Immediately After First section). This

register can be written to power up and power down the monitor

channel, select the mix of ADC and DAC channels delivered to

the monitor output, and select the order of the Σ-Δ monitor

output bit stream.

TYPICAL CHIP POWER-DOWN SEQUENCE

Once the codec is powered down to the level desired, no add-

RESET

itional power can be saved unless the AD1803 receives a

ignoring power potentially saved by stopping the clock on

the CLK_OUT pin or disabling GPIO pin drivers, which have

RESET

,

TYPICAL CODEC POWER-DOWN SEQUENCE

resistive loads. When a

is received by the AD1803, the

serial interface automatically powers down, leaving the internal

clock generation and distribution circuitry of the part as the final

significant power consumer to be addressed. If Bit R34PM in

There are two ways to power down the codec. The first way is to

RESET

simply assert

(drive

pin low). This clears register

0x3E to its initial power-up default, powering down the ADC,

DAC, and voltage reference of the AD1803. A second method is

outlined below.

RESET

Register 0x5C is set to a 0 before

circuitry is powered down as well when

the consequence that wake-up on ring and ability to source a clock

RESET

is asserted, this clock

RESET

is asserted, with

Step 1: Write to Register 0x3E (Extended Status and Control

Register).

on the CLK_OUT pin during

is lost. This leaves silicon

leakage current, typically less than 100 μA, plus inadvertent serial

interface loading as the final power drains. Inadvertent serial

interface loading can be due to either the AD1803 receiving

intermediate or switching logic levels on its BIT_CLK, SYNC,

or SDATA_OUT input pins, or the presence of resistive loads to

a potential other than DGND (AD1803 digital ground) on the

SDATA_IN or BIT_CLK output pins. This inadvertent serial

interface loading can be eliminated if Bit SPISO (Serial Port

Isolate) in Register 0x5E is set to 1 before the part receives a

Bit[11]—DPDN (DAC power-down). This bit must be set to 1

to power down the DAC channel of the AD18103.

Bit[10]—APDN (ADC power-down). This bit must be set to 1

to power down the ADC channel of the AD18103.

Bit[9]—VPDN (voltage reference power-down). This bit can be

set to 1 to power down the voltage reference of the AD1803 and

save approximately 200 μA, but it can be desirable to leave the

voltage reference powered up. Leaving it powered up saves about

48 ms from a future codec power-up sequence, and avoids

RESET

with the consequence that output BIT_CLK is driven

RESET

low weakly (<200 μA drive current) whenever

is asserted.

Rev. A | Page 31 of 32

AD1803ꢀꢀ

OUTLINEꢀDIMENSIONSꢀꢀ

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 19. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD1803JRU-REEL

AD1803JRUZ-REEL¹

Temperature Range

Package Description

Package Option

RU-24

0°C to +70°C

24-Lead Thin Shrink Small Outline Package [TSSOP]

¹Z = Pb-free part.

registered trademarks are the property of their respective owners.

C02562-0-12/06(A)

Rev. A | Page 32 of 32


型号：	AD1803JRUZ-REEL
厂家：	ADI
描述：	IC SPECIALTY TELECOM CIRCUIT, PDSO24, LEAD FREE, MO-153-AD, TSSOP-24, Telecom IC:Other 电信光电二极管电信集成电路
文件：	总32页 (文件大小：5147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD1803JRUZ-REEL [ADI]

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