AD15700/PCB_技术文档

1 MSPS 16-/14-Bit

Analog I/O Port

AD15700

FUNCTIONAL BLOCK DIAGRAM

FEATURES

16-Bit A/D Converter

1 MSPS

VDD_DAC

DGND_DAC

S/(N + D): 90 dB Typ @ 250 kHz

No Pipeline Delay

14-Bit D/A Converter

14-BIT DAC

VREF

VOUT_DAC

AGND_DAC

Settling Time: 1 ꢀs

S/N: 92 dB Typ

2 80 MHz Amplifiers

30 V/ꢀs Slew Rate

–IN1

+IN1

14-BIT DATA LATCH

CS_DAC

DIN

CONTROL

LOGIC

+VS1

SCLK

SERIAL INPUT REGISTER

VOUT1

–VS1

Rail-to-Rail Input and Output

Output Current 15 mA

2 Gain Setting Center Tapped Resistors

Resistor Ratio Tracking: 2 ppm/ꢁC

Unipolar Operation

COMMON

RA1

RB1

AD15700

1.5kꢂ

RC1

REF

SPI^®/QSPI™/MICROWIRE™/DSP Compatible

132 mW Typical Power Dissipation

REFGND

RPAD1

4R

IND(4R)

OVDD

OGND

4R

2R

R

INC(4R)

INB(2R)

APPLICATIONS

SERIAL

PORT

Optical MEMS Mirror Control

Industrial Process Control

Data Acquisition

Instrumentation

Communication

INA(R)

SWITCHED

CAP DAC

SER/PAR

INGND

VOUT2

BUSY

16

PARALLEL

INTERFACE

D[15:0]

CS_ADC

RD

+VS2

+IN2

CLOCK

SAR ADC

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

OB/2C

–IN2

–VS2

BYTESWAP

GENERAL DESCRIPTION

PD

AVDD

RESET

The AD15700 is a precision component to interface analog input

and output channels to a digital processor. It is ideal for area-

limited applications that require maximum circuit density. The

AD15700 contains the functionality of a 16-bit, 1 MSPS charge

redistribution SAR analog-to-digital converter that operates from

a 5 V power supply. The high speed 16-bit sampling ADC incor-

porates a resistor input scaler that allows various input ranges, an

internal conversion clock, error correction circuits, and both serial

and parallel system interface ports. The AD15700 also contains a

14-bit, serial input, voltage output DAC that operates from a 5 V

supply and has a settling time of 1 ms. Two single- or split-supply

voltage feedback amplifiers with rail-to-rail input and output

characteristics featuring 80 MHz of small signal bandwidth and

10 mV/∞C offset drift provide ADC and DAC buffering capability.

The center tapped 3 kW resistors are precision resistor networks

with 2 ppm/∞C ratio tracking that provide low gain drift when

used for scaling.

1.5kꢂ 1.5kꢂ

AGND_ADC

RPAD2

RA2 RB2 RC2

WARP

CNVST

IMPULSE

DVDD

DGND

ADC

PRODUCT HIGHLIGHTS

1. Fast Throughput ADC.

The AD15700 incorporates a high speed, 1 MSPS, 16-bit

SAR ADC.

2. Superior ADC INL.

The 16-bit ADC has a maximum integral nonlineariy of

2.5 LSB with no missing codes.

3. Two Precision Resistor Networks with 2 ppm/∞C Ratio

Tracking for Gain Setting.

4. Low Power Consumption.

The ADC, DAC, and amp functions are electrically isolated from

each other to provide maximum design flexibility. Input and

output signal conditioning circuits for the converters can be easily

configured with short interconnects under the device at the board

level. The AD15700 is available in a 10 mm CSPBGA package.

Typically 132 mW at maximum performance levels.

5. Industrial Temperature Range: –40∞C to +85∞C.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD15700–SPECIFICATIONS

(–40ꢁC to +85ꢁC, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless

16-BIT ADC ELECTRICAL CHARACTERISTICS ^{otherwise noted.)}

Parameter

Condition

Min

Typ

Max

Unit

RESOLUTION

16

Bits

ANALOG INPUT

Voltage Range

Common-Mode Input Voltage

Analog Input CMRR

Input Impedance

VIND – VINGND

VINGND

f_IN= 100 kHz

±4 REF, 0 V to 4 REF, ±2 REF (See Table I)

–0.1

+0.5

V

dB

74

See Table I

THROUGHPUT SPEED

Complete Cycle

Throughput Rate

Time between Conversions

Complete Cycle

Throughput Rate

In Warp Mode

In Normal Mode

In Impulse Mode

1

ms

1

1000

1

1.25

800

1.5

666

kSPS

ms

0

kSPS

ms

Complete Cycle

Throughput Rate

kSPS

DC ACCURACY

Integral Linearity Error

No Missing Codes

–2.5

16

+2.5

+45

LSB¹

Bits

LSB

Transition Noise

0.7

Bipolar Zero Error ², T_MINto T_MAX

±5 V Range, Normal or

Impulse Modes

–45

Other Range or Mode

±0.1%

% of FSR

LSB

Bipolar Full-Scale Error², T_MINto T_MAX

Unipolar Zero Error², T_MINto T_MAX

Unipolar Full-Scale Error², T_MINto T_MAX

Power Supply Sensitivity

–0.38

–0.18

–0.76

+0.38

+0.18

+0.76

AVDD = 5 V ± 5%

±9.5

AC ACCURACY

Signal-to-Noise

f_IN= 20 kHz

f_IN= 250 kHz

89

90

dB³

dB

Spurious-Free Dynamic Range

Total Harmonic Distortion

f

_IN= 250 kHz

100

–100

90

30

9.6

dB

MHz

f_IN= 20 kHz

f_IN= 250 kHz

f

–96

Signal-to-(Noise + Distortion)

–3 dB Input Bandwidth

_IN= 20 kHz

88.5

f_IN= 250 kHz, –60 dB Input

SAMPLING DYNAMICS

Aperture Delay

Aperture Jitter

2

5

ns

ps rms

ns

Transient Response

Full-Scale Step

250

3.0

REFERENCE

External Reference Voltage Range

External Reference Current Drain

2.3

2.5

200

V

mA

1 MSPS Throughput

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

–0.3

+2.0

–1

+0.8

DVDD + 0.3

+1

V

mA

I_IH

–1

–2–

REV. A

AD15700

Parameter

Condition

Min

Typ

Max

Unit

DIGITAL OUTPUTS

Data Format

Parallel or Serial 16-Bit

Pipeline Delay

Conversion Results Available Immediately

after Completed Conversion

V_OL

V_OH

I_SINK= 1.6 mA

I_SOURCE= –570 mA

0.4

V

OVDD – 0.6

POWER SUPPLIES

Specified Performance

AVDD

4.75

2.7

5

5.25

V

DVDD

OVDD

Operating Current⁴

AVDD

15

7.2

37

84

15

mA

mW

DVDD⁵

OVDD⁵

Power Dissipation^{5, 6}

666 kSPS Throughput⁷

100 SPS Throughput⁷

1 MSPS Throughput⁴

95

112

125

1

In Power-Down Mode⁸

TEMPERATURE RANGE

Specified Performance

T_MINto T_MAX

–40

+85

∞C

NOTES

¹LSB means Least Significant Bit. With the ±5 V input range, one LSB is 152.588 mV.

²These specifications do not include the error contribution from the external reference.

³All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

⁴In Warp Mode.

⁵Tested in Parallel Reading Mode.

⁶Tested with the 0 V to 5 V range and VIN – VINGND = 0 V.

⁷In Impulse Mode.

⁸With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND, respectively.

Specifications subject to change without notice.

Table I. Analog Input Configuration

Input Voltage Range

IND(4R)

INC(4R)

INB(2R)

INA(R)

Input Impedance¹

±4 REF

V_IN

INGND

V_IN

INGND

V_IN

INGND

V_IN

REF

INGND

V_IN

1.63 kW

948 W

711 W

948 W

711 W

Note 2

±2 REF

± REF

0 V to 4 REF

0 V to 2 REF

0 V to REF

V_IN

NOTES

¹Typical analog input impedance.

²For this range, the input is high impedance.

REV. A

–3–

AD15700

(–40ꢁC to +85ꢁC, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)

16-BIT ADC TIMING CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Unit

Refer to Figures 14 and 15

Convert Pulsewidth

t₁

t₂

5

ns

ms

Time between Conversions

(Warp Mode/Normal Mode/Impulse Mode)

1/1.25/1.5

Note 1

CNVST LOW to BUSY HIGH Delay

BUSY HIGH All Modes Except in Master Serial Read after

Convert Mode (Warp Mode/Normal Mode/Impulse Mode)

Aperture Delay

End of Conversion to BUSY LOW Delay

Conversion Time (Warp Mode/Normal Mode/Impulse Mode)

Acquisition Time

t₃

t₄

30

ns

ms

0.75/1/1.25

t₅

t₆

t₇

t₈

t₉

2

ns

ms

ns

10

0.75/1/1.25

1

10

RESET Pulsewidth

Refer to Figures 16, 17, and 18 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay

(Warp Mode/Normal Mode/Impulse Mode)

DATA Valid to BUSY LOW Delay

Bus Access Request to DATA Valid

Bus Relinquish Time

t₁₀

ms

t₁₁

t₁₂

t₁₃

20

5

ns

40

15

Refer to Figures 20 and 21 (Master Serial Interface Modes)²

CS_ADC LOW to SYNC Valid Delay

CS_ADC LOW to Internal SCLK Valid Delay

CS_ADC LOW to SDOUT Delay

CNVST LOW to SYNC Delay (Read During Convert)

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Asserted to SCLK First Edge Delay ³

Internal SCLK Period³

t₁₄

t₁₅

t₁₆

t₁₇

10

ns

25/275/525

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

4

ns

ms

25

15

9

4.5

2

40

Internal SCLK HIGH³

Internal SCLK LOW³

SDOUT Valid Setup Time³

SDOUT Valid Hold Time³

SCLK Last Edge to SYNC Delay³

CS_ADC HIGH to SYNC HI-Z

3

10

CS_ADC HIGH to Internal SCLK HI-Z

CS_ADC HIGH to SDOUT HI-Z

BUSY HIGH in Master Serial Read after Convert³

CNVST LOW to SYNC Asserted Delay

Master Serial Read after Convert

See Table II

0.75/1/1.25

SYNC Deasserted to BUSY LOW Delay

t₃₀

25

ns

Refer to Figures 22 and 24 (Slave Serial Interface Modes)

External SCLK Setup Time

External SCLK Active Edge to SDOUT Delay

SDIN Setup Time

SDIN Hold Time

External SCLK Period

t₃₁

t₃₂

t₃₃

t₃₄

t₃₅

t₃₆

t₃₇

5

3

5

25

10

ns

16

External SCLK HIGH

External SCLK LOW

NOTES

¹In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

²In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C_Lof 10 pF; otherwise, the load is 60 pF maximum.

³In serial master Read during Convert Mode. See Table II.

Specifications subject to change without notice.

–4–

REV. A

AD15700

Table II. Serial Clock Timings in Master Read after Convert

DIVSCLK[1]

DIVSCLK[0]

0

1

0

1

Symbol

Unit

SYNC to SCLK First Edge Delay Minimum

Internal SCLK Period Minimum

Internal SCLK Period Maximum

Internal SCLK HIGH Minimum

Internal SCLK LOW Minimum

SDOUT Valid Setup Time Minimum

SDOUT Valid Hold Time Minimum

SCLK Last Edge to SYNC Delay Minimum

BUSY HIGH Width Maximum (Warp)

BUSY HIGH Width Maximum (Normal)

BUSY HIGH Width Maximum (Impulse)

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₈

4

20

50

70

25

24

22

4

60

2

2.25

2.5

20

ns

ms

25

40

15

9

4.5

2

100

140

50

49

22

30

140

3

3.25

3.5

200

280

100

99

22

89

300

5.25

5.5

5.75

3

1.5

1.75

2

I

1.6mA

OL

TO OUTPUT

1.4V

C

L

60pF

500mA

I

OH

IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD

C

OF 10pF; OTHERWISETHE LOAD IS 60pF MAXIMUM.

L

Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, C_L= 10 pF

0.8V

2V

t

DELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timing

REV. A

–5–

AD15700

(T = –40ꢁC to +85ꢁC, V _DAC = 5 V, V_REF= 2.5 V, unless otherwise noted.)

14-BIT DAC ELECTRICAL CHARACTERISTICS

A

DD

Parameter

Condition

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution

1 LSB = V_REF/2¹⁴= 153 mV

when V_REF= 2.5 V

14

Bits

LSB

ppm/∞C

LSB

Relative Accuracy, INL

Differential Nonlinearity

Gain Error

Gain Error Temperature Coefficient

Zero Code Error

±0.15

–0.3

±0.1

0.1

±1.0

±0.8

0

Guaranteed Monotonic

–1.75

0

0.5

Zero Code Temperature Coefficient

±0.05

ppm/∞C

OUTPUT CHARACTERISTICS

Output Voltage Range

0

V_REF–1 LSB

V

Output Voltage Settling Time

Digital-to-Analog Glitch Impulse

To 1/2 LSB of FS, C_L= 10 pF

1 LSB Change around the

Major Carry

1

ms

10

nV–s

Digital Feedthrough

All 1s Loaded to DAC,

V_REF= 2.5 V

Tolerance Typically 20%

DV_DD±10%

0.05

6.25

nV–s

kW

LSB

DAC Output Impedance

Power Supply Rejection Ratio

±1.0

DAC REFERENCE INPUT

Reference Input Range

Reference Input Resistance*

2

9

V_DD

V

kW

LOGIC INPUTS

Input Current

±1.0

mA

V

pF

V

VINL, Input Low Voltage

VINH, Input High Voltage

Input Capacitance

0.8

2.4

10

Hysteresis Voltage

0.4

1.3

REFERENCE

Reference –3 dB Bandwidth

Reference Feedthrough

All 1s Loaded

All 0s Loaded,

MHz

V_REF= 1 V p-p at 100 kHz

1

mV p-p

dB

pF

Signal-to-Noise Ratio

Reference Input Capacitance

92

75

120

Code 0000_H

Code 3FFF_H

pF

POWER REQUIREMENTS

V_DD

I_DD

4.5

5.50

1.1

6.05

V

mA

mW

0.3

1.5

Power Dissipation

*Reference input resistance is code-dependent, minimum at 2555_H

.

Specifications subject to change without notice.

–6–

REV. A

AD15700

(V_DD= 5 V, ꢃ5%, V_REF= 2.5 V, AGND = DGND = 0 V. All Specifications

T_A= T_MINto T_MAX, unless otherwise noted).

14-BIT DAC TIMING CHARACTERISTICS^{1, 2}

Parameter

Limit at T_MIN, T_MAXAll Versions

Unit

Description

f_SCLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

25

40

20

15

35

20

15

0

MHz max

ns min

SCLK Cycle Frequency

SCLK Cycle Time

SCLK High Time

SCLK Low Time

CS_DAC Low to SCLK High Setup

CS_DAC High to SCLK High Setup

SCLK High to CS_DAC Low Hold Time

SCLK High to CS_DAC High Hold Time

Data Setup Time

t₉

t₁₀

Data Hold Time

CS_DAC High Time between Active Periods

30

NOTES

¹Guaranteed by design. Not production tested.

²Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90%

of 3 V and timed from a voltage level of 1.6 V).

Specifications subject to change without notice.

t₁

SCLK

t₂

t₆

t₅

t₃

t₄

t₇

CS_DAC

t₁₀

t₈

t₉

DIN

DB13

DB0

Figure 3. Timing Diagram

REV. A

–7–

AD15700

[5 V Supply (T_A= 25ꢁC, V_S= 5 V, R_L= 1 kꢂ to 2.5 V, R_F= 2.5 kꢂ,

unless otherwise noted.)]

AMPLIFIER ELECTRICAL CHARACTERISTICS

Parameter

Condition

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth

Slew Rate

G = +1, V_O< 0.4 V p-p

G = –1, V_O= 2 V Step

G = –1, V_O= 2 V Step, C_L= 10 pF

54

27

80

32

125

MHz

V/ms

ns

Settling Time to 0.1%

DISTORTION/NOISE PERFORMANCE

Total Harmonic Distortion

f_C= 1 MHz, V_O= 2 V p-p, G = +2

f_C= 100 kHz, V_O= 2 V p-p, G = +2

–62

–86

15

2.4

5

dBc

Input Voltage Noise

Input Current Noise

f = 1 kHz

f = 100 kHz

f = 1 kHz

R_L= 1 kW

nV/

÷

Hz

pA

%

/

÷

Differential Gain

Differential Phase

0.17

0.11

Degrees

DC PERFORMANCE

Input Offset Voltage

V_CM= V_CC/2; V_OUT= 2.5 V

±1

±6

5

±6

mV

mV/∞C

mA

T

_MINto T_MAX

±10

Offset Drift

Input Bias Current

V_CM= V_CC/2; V_OUT= 2.5 V

T_MINto T_MAX

0.45

1.2

2.0

350

mA

Input Offset Current

Open-Loop Gain

50

82

nA

dB

V

_CM= V_CC/2; V_OUT= 1.5 V to 3.5 V

76

74

T_MINto T_MAX

INPUT CHARACTERISTICS

Common-Mode Input Resistance

Differential Input Resistance

Input Capacitance

40

280

1.6

–0.5 to +5.5

MW

kW

pF

V

Input Voltage Range

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

–0.2 to +5.2

70

80

V

_CM= 0 V to 5 V

56

66

dB

V

V_CM= 0 V to 3.8 V

Differential/Input Voltage

3.4

OUTPUT CHARACTERISTICS

Output Voltage Swing Low

Output Voltage Swing High

Output Voltage Swing Low

Output Voltage Swing High

Output Current

R_L= 10 kW

R_L= 1 kW

0.05

4.95

0.2

0.02

4.98

0.1

4.9

15

28

–46

15

V

mA

pF

4.8

Short Circuit Current

Sourcing

Sinking

G = +2

Capacitive Load Drive

POWER SUPPLY

Operating Range

Quiescent Current per Amplifier

Power Supply Rejection Ratio

2.7

75

12

1400

V

mA

dB

800

86

V_S– = 0 V to –1 V or

V_S+ = 5 V to 6 V

OPERATING TEMPERATURE RANGE

–40

+85

∞C

Specifications subject to change without notice.

–8–

REV. A

AD15700

ꢃ

5 V Supply (T_A= 25ꢁC, V_S= ꢃ5 V, R_L= 1 kꢂ to 0 V, R_F= 2.5 kꢂ,

AMPLIFIER ELECTRICAL CHARACTERISTICS ^[_{unless otherwise noted.)]}

Parameter

Condition

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth

Slew Rate

G = +1, V_O< 0.4 V p-p

G = –1, V_O= 2 V Step

G = –1, V_O= 2 V Step, C_L= 10 pF

54

30

80

35

125

MHz

V/ms

ns

Settling Time to 0.1%

DISTORTION/NOISE PERFORMANCE

Total Harmonic Distortion

f_C= 1 MHz, V_O= 2 V p-p, G = +2

f_C= 100 kHz, V_O= 2 V p-p, G = +2

–62

–86

15

2.4

5

dBc

Input Voltage Noise

Input Current Noise

f = 1 kHz

f = 100 kHz

f = 1 kHz

R_L= 1 kW

nV

pA

%

/

÷

Hz

Differential Gain

Differential Phase

0.15

Degrees

DC PERFORMANCE

Input Offset Voltage

V_CM= 0 V; V_OUT= 0 V

T_MINto T_MAX

V_CM= 0 V; V_OUT= 0 V

T_MINto T_MAX

±1

±6

5

±6

mV

mV/∞C

mA

±10

Offset Drift

Input Bias Current

0.45

1.2

2.0

350

mA

Input Offset Current

Open-Loop Gain

50

80

nA

dB

V_CM= 0 V; V_OUT= ±2 V

76

74

T

_MINto T_MAX

INPUT CHARACTERISTICS

Common-Mode Input Resistance

Differential Input Resistance

Input Capacitance

40

280

1.6

–5.5 to +5.5

MW

kW

pF

V

Input Voltage Range

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

–5.2 to +5.2

80

90

V

V_CM= –5 V to +5 V

V_CM= –5 V to +3.5 V

60

66

dB

V

Differential/Input Voltage

3.4

OUTPUT CHARACTERISTICS

Output Voltage Swing Low

Output Voltage Swing High

Output Voltage Swing Low

Output Voltage Swing High

Output Current

R_L= 10 kW

R_L= 1 kW

–4.94

+4.94

–4.7

–4.98

+4.98

–4.85

+4.75

15

+35

–50

15

V

mA

pF

+4.7

Short Circuit Current

Sourcing

Sinking

G = +2

Capacitive Load Drive

POWER SUPPLY

Operating Range

Quiescent Current per Amplifier

Power Supply Rejection Ratio

±1.35

±6

1600

V

mA

dB

900

86

V_S– = –5 V to –6 V or

V_S+ = +5 V to +6 V

76

OPERATING TEMPERATURE RANGE

–40

+85

∞C

Specifications subject to change without notice.

REV. A

–9–

AD15700

RESISTOR DIVIDER ELECTRICAL CHARACTERISTICS (@ T_A= 25ꢁC, unless otherwise noted.)

Parameter

Condition

Min

Typ

Max

Unit

Resistance

2.97

3.00

50

1.0

3.03

kW

Temperature Coefficient of Resistance

Resistance Ratio of Two Halves

Resistance Ratio Tracking

Power Dissipation

ppm/∞C

0.99

1.01

2

250*

ppm/∞C

mW

T_A= 70∞C

At higher temperatures, linearly derates to 0 mW at 175∞C.

*

Specifications subject to change without notice.

Amplifier Supply Voltage (VS1, VS2) . . . . . . . . . . . . . . 12.6 V

Amplifier Input Voltage (Common Mode) . . . . . . ±V_S±0.5 V

Amplifier Differential Input Voltage . . . . . . . . . . . . . . . ±3.4 V

Amplifier Output Short Circuit

ABSOLUTE MAXIMUM RATINGS*

Analog Inputs

IND, INC, INB . . . . . . . . . . . . . . . . . . . . . . –11 V to +30 V

INA, REF, INGND, REFGND, AGND . . . –0.3 V to AVDD + 0.3 V

ADC Ground Voltage Differences

AGND_ADC, DGND_ADC, OGND . . . . . . . . . . . . ±0.3 V

ADC Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

ADC Digital Inputs . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

VDD_DAC to AGND_DAC . . . . . . . . . . . . . . . –0.3 V to +6 V

DAC Digital Input Voltage to

Duration . . . . . . . . . . . . . . Observe Power Derating Curves

Resistor Instantaneous Voltage Drop . . . . . . . . . . . . . . . ±50 V

Internal Power Dissipation . . . . . . . . . . . . . (T_JMax – T_A)/␪

JA

Thermal Resistance ␪

JA

10 mm CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 42∞C/W

Maximum Junction Temperature (T_JMax) . . . . . . . . . . 150∞C

Operating Temperature Range . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . 225∞C, 15 sec

DGND_DAC . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

VOUT_DAC to AGND_DAC . . . . –0.3 V to DVDD + 0.3 V

AGND_DAC to DGND_DAC . . . . . . . . . . . –0.3 V to +0.3 V

DAC Input Current to Any DAC Pin Except Supplies . . ±10 mA

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Range

Model

Package Option

AD15700BCA

AD15700/PCB

ADDS-2191-EZLITE

–40∞C to +85∞C

25∞C

144-Lead CSPBGA

Evaluation Board

Evaluation Kit*

™

ADDS-21535-EZLITE

ADDS-21160M-EZLITE

ADDS-21161N-EZLITE

*One of the DSP Evaluation Kits is required for operation of the AD15700/PCB Evaluation Board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–10–

REV. A

AD15700

ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)

Pin No.

Mnemonic

Type

Description

H9, J8,

AGND_ADC

P

Analog Power Ground Pin

J9, M12

M6

L7

AVDD

P

Input Analog Power Pin. Nominally 5 V.

BYTESWAP

DI

Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB

is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is

output on D[7:0].

L8

OB/2C

DI

Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output

is straight binary; when LOW, the MSB is inverted, resulting in a twos complement

output from its internal shift register.

M7

WARP

Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,

the maximum throughput is achievable, and a minimum conversion rate must be applied

in order to guarantee full specified accuracy. When LOW, full accuracy is maintained

independent of the minimum conversion rate.

L9

IMPULSE

DI

Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

M8

SER/PAR

Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH,

the Serial Interface Mode is selected and some bits of the DATA bus are used as a

serial port.

M9, L10 D[0:1]

DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these

outputs are in high impedance.

M10, L11 D[2:3] or

DI/O

When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the

serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial

Port, are used to slow down, if desired, the internal serial clock that clocks the data output.

In the other serial modes, these inputs are not used.

DIVSCLK[0:1]

M11

L12

D[4] or EXT/INT

DI/O

When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital

select input for choosing the internal or an external data clock, called, respectively, Master

and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK

output. With EXT/INT set to a logic HIGH, output data is synchronized to an external

clock signal connected to the SCLK input and the external clock is gated by CS_ADC.

D[5] or INVSYNC

When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the

active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,

SYNC is active LOW.

K11

K12

D[6] or INVSCLK

D[7] or RDC/SDIN

DI/O

When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the

SCLK signal. It is active in both Master and Slave Mode.

When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an

external data input or a read mode selection input, depending on the state of EXT/INT.

When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain

the conversion results from two or more ADCs onto a single SDOUT line. The digital

data level on SDIN is output on DATA with a delay of 16 SCLK periods after the

initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select

the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT

during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT

only when the conversion is complete.

J10

J11

OGND

OVDD

P

Input/Output Interface Digital Power Ground

Input/Output Interface Digital Power. Nominally at the same supply as the supply of

the host interface (5 V or 3.3 V).

J12

DVDD

P

Digital Power. Nominally at 5 V.

REV. A

–11–

AD15700

ADC PIN FUNCTION DESCRIPTIONS (continued)

Pin No.

H10

Mnemonic

Type

P

Description

DGND_ADC

D[8] or SDOUT

Digital Power Ground

H12

DO

When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data

output synchronized to SCLK. Conversion results are stored in an on-chip register.

The ADC provides the conversion result, MSB first, from its internal shift register.

The DATA format is determined by the logic level of OB/2C. In Serial Mode, when

EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when

EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge

and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on

SCLK falling edge and valid on the next rising edge.

H11

G12

D[9] or SCLK

D[10] or SYNC

DI/O

DO

When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a serial

data clock input or output, dependent upon the logic state of the EXT/INT pin. The

active edge where the data SDOUT is updated depends upon the logic state of the

INVSCLK pin.

When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital

output frame synchronization for use with the internal data clock (EXT/INT = Logic

LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH

and remains HIGH while SDOUT output is valid. When a read sequence is initiated

and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output

is valid.

G11

D[11] or RDERROR DO

When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial

Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started

and not complete when the following conversion is complete, the current data is lost

and RDERROR is pulsed high.

F12, F11, D[12:15]

E12, E11

DO

Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH,

these outputs are in high impedance.

G10

BUSY

Busy Output. Transitions HIGH when a conversion is started, and remains HIGH

until the conversion is complete and the data is latched into the on-chip shift register.

The falling edge of BUSY could be used as a data ready clock signal.

G9

DGND_ADC

P

Must be Tied to Digital Ground

E10

RD

DI

Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled.

K10

D12

K9

CS_ADC

RESET

PD

DI

Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled. CS_ADC is also used to gate the external serial clock.

Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.

Power-Down Input. When set to a logic HIGH, power consumption is reduced and

conversions are inhibited after the current one is completed.

E7

CNVST

Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold

state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW),

if CNVST is held low when the acquisition phase (t₈) is complete, the internal

sample/hold is put into the hold state and a conversion is immediately started.

H8

G5

H5

J7

AGND_ADC

REF

P

Must be Tied to Analog Ground

Reference Input Voltage

AI

P

REFGND

INGND

Reference Input Analog Ground

Analog Input Ground

J5, K5,

L5, M5

INA, INB,

INC, IND

AI

Analog Inputs. Refer to Table I for input range configuration.

–12–

REV. A

AD15700

DAC PIN FUNCTION DESCRIPTIONS

Description

Pin No.

Mnemonic

Type

A6

VOUT_DAC

AGND_DAC

VREF

AO

P

AI

Analog Output Voltage from the DAC

Ground Reference Point for Analog Circuitry

This is the voltage reference input for the DAC. Connect to external reference

ranges from 2 V to VDD.

A3, C3, C4

A2

B1

E1

E2

CS_DAC

SCLK

DIN

DI

This is an active low logic input signal. The chip select signal is used to frame

the serial data input.

Clock Input. Data is clocked into the input register on the rising edge of SCLK.

Duty cycle must be between 40% and 60%.

Serial Data Input. This device accepts 14-bit words. Data is clocked into the

input register on the rising edge of SCLK.

E3

C6

DGND_DAC

VDD_DAC

P

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage, 5 V ± 10%

AMPLIFIER PIN FUNCTION DESCRIPTIONS

Pin No.

C9 (J1)

Mnemonic

+IN1(2)

Type

AI

Description

Positive Input Voltage

A9 (G1)

B12 (K4)

A11 (F3)

–IN1(2)

AI

Negative Input Voltage

Amplifier Output Voltage

Analog Positive Supply Voltage

Analog Negative Supply Voltage

VOUT1(2)

+VS1(2)

–VS1(2)

AO

P

B10, B11

(G3, H3)

P

RESISTOR PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Type

Description

B9 (L4)

A8 (M4)

D9 (L1)

A7 (M3)

RA1(2)

RB1(2)

RC1(2)

RPAD1(2)

AI/O

P

Resistor End Terminal

Resistor Center Tap

Resistor End Terminal

Resistor Die Pad. Tie to Analog Ground.

COMMON PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Type

Description

A1, A4, A5, A10, A12, B2–B8, C1,

C2, C5, C7, C8, C10–C12, D1–D8,

D10, D11, E4–E6, E8, E9, F1, F2,

F4–F10, G2, G4, G6–G8, H1, H2,

H4, H6, H7, J2–J4, J6, K1–K3,

K6–K8, L2, L3, L6, M1, M2

COMMON

P

Common Floating Net Connecting 69 Pins. Not electrically

connected within the module. Tie at least one of these pins

to Analog Ground.

NOTES

AI = Analog Input

AI/O = Bidirectional Analog

AO = Analog Output

DI = Digital Input

DI/O = Bidirectional Digital

DO = Digital Output

P = Power

REV. A

–13–

AD15700

ADC DEFINITION OF SPECIFICATIONS

DAC DEFINITION OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Relative Accuracy

Linearity error refers to the deviation of each individual code

from a line drawn from “negative full scale” through “positive

full scale.” The point used as negative full scale occurs 1/2 LSB

before the first code transition. Positive full scale is defined as a

level 1 1/2 LSB beyond the last code transition. The deviation is

measured from the middle of each code to the true straight line.

For the DAC, relative accuracy or integral nonlinearity (INL)

is a measure of the maximum deviation in LSBs from a straight

line passing through the endpoints of the DAC transfer function.

A typical INL versus code plot can be seen in TPC 16.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB maximum

ensures monotonicity. TPC 19 illustrates a typical DNL versus

code plot.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential

nonlinearity is the maximum deviation from this ideal value.

It is often specified in terms of resolution for which no missing

codes are guaranteed.

Gain Error

Full-Scale Error

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range. It is

the deviation in slope of the DAC transfer characteristic from ideal.

The last transition (from 011...10 to 011...11 in twos comple-

ment coding) should occur for an analog voltage 1 1/2 LSB

below the nominal full scale (2.499886 V for the ±2.5 V range).

The full-scale error is the deviation of the actual level of the last

transition from the ideal level.

Gain Error Temperature Coefficient

This is a measure of the change in gain error with changes in

temperature. It is expressed in ppm/∞C.

Bipolar Zero Error

The difference between the ideal midscale input voltage (0 V)

and the actual voltage producing the midscale output code.

Zero Code Error

Zero code error is a measure of the output error when zero code

is loaded to the DAC register.

Unipolar Zero Error

Zero Code Temperature Coefficient

This is a measure of the change in zero code error with a change

in temperature. It is expressed in mV/∞C.

In unipolar mode, the first transition should occur at a level

1/2 LSB above analog ground. The unipolar zero error is the

deviation of the actual transition from that point.

Digital-to-Analog Glitch Impulse

Spurious Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of

the input signal and the peak spurious signal.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV–s

and is measured when the digital input code is changed by 1 LSB

at the major carry transition. A plot of the glitch impulse is shown

in Figure 28.

Effective Number of Bits (ENOB)

A measurement of the resolution with a sine wave input. It is

related to S/(N + D) by the following formula:

Digital Feedthrough

ENOB = S / N + D

– 1.76 / 6.02

[

]

(

)

dB

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital inputs of the DAC, but

is measured when the DAC output is not updated. CS_DAC is

held high, while the CLK and DIN signals are toggled. It is

specified in nV–s and is measured with a full-scale code change

on the data bus, i.e., from all 0s to all 1s and vice versa. A typical

plot of digital feedthrough is shown in Figure 27.

and is expressed in bits.

Total Harmonic Distortion (THD)

The rms sum of the first five harmonic components to the rms

value of a full-scale input signal; expressed in decibels.

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the actual input signal to the rms

sum of all other spectral components below the Nyquist frequency,

excluding harmonics and dc. The value for SNR is expressed in

decibels.

Power Supply Rejection Ratio

This specification indicates how the output of the DAC is affected

by changes in the power supply voltage. Power supply rejection

ratio is quoted in terms of percent change in output per percent

change in V_DDfor full-scale output of the DAC. V_DDis varied

by ±10%.

Signal-to-(Noise + Distortion)

Ratio (S/[N + D])

The ratio of the rms value of the actual input signal to the rms

sum of all other spectral components below the Nyquist frequency,

including harmonics but excluding dc. The value for S/(N + D)

is expressed in decibels.

Reference Feedthrough

This is a measure of the feedthrough from the V_REFinput to the

DAC output when the DAC is loaded with all 0s. A 100 kHz,

1 V p-p is applied to V_REF. Reference feedthrough is expressed

in mV p-p.

Aperture Delay

A measure of the acquisition performance, measured from the

falling edge of the CNVST input to when the input signal is

held for a conversion.

Transient Response

The time required for the ADC to achieve its rated accuracy

after a full-scale step function is applied to its input.

–14–

REV. A

Typical Performance Characteristics–

AD15700

16-BIT D/A CONVERTER

2.5

2.0

60

50

40

30

20

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

10

0

16384

32768

CODE

49152

65536

–3.0 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3 0.0

NEGATIVE INL – LSB

TPC 1. Integral Nonlinearity vs. Code

TPC 4. Typical Negative INL Distribution (314 Units)

1.75

1.50

8000

7029 7039

7000

1.25

6000

5000

4000

3000

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

–0.75

–1.00

2000

1297

986

1000

0

17

25

0

16384

32768

CODE

49152

65536

7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007

CODE IN HEXADECIMAL

TPC 2. Differential Nonlinearity vs. Code

TPC 5. Histogram of 16,384 Conversions of

a DC Input at the Code Transition

60

50

40

30

20

10

10000

9503

9000

8000

7000

6000

5000

4000

3000

2000

3344

3296

1000

0

132

106

0

2

1

0

0.0 0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7 3.0

7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007

POSITIVE INL – LSB

CODE IN HEXADECIMAL

TPC 3. Typical Positive INL Distribution (314 Units)

TPC 6. Histogram of 16,384 Conversions of

a DC Input at the Code Center

REV. A

–15–

AD15700

0

96

93

90

–98

FS = 1 MSPS

= 45.5322kHz

SNR = 89.45dB

THD = –100.05dB

SFDR = 100.49dB

SINAD = 89.1dB

f

IN

–20

–40

–60

–100

–80

–102

–100

–120

–140

–160

87

84

–104

–106

–180

0

100

200

300

400

500

–55 –35

–15

5

25

45

65

85

105 125

FREQUENCY – kHz

TEMPERATURE – ꢁC

TPC 7. FFT Plot

TPC 10. SNR, THD vs. Temperature

100

95

16.0

15.5

15.0

–60

115

110

–65

–70

SFDR

105

100

95

–75

SNR

SINAD

90

–80

90

–85

85

80

14.5

14.0

85

–90

ENOB

SECOND HARMONIC

THD

–95

80

–100

–105

75

70

75

70

13.5

13.0

–110

–115

65

60

THIRD HARMONIC

0

10

100

1000

10

100

1

1000

FREQUENCY – kHz

TPC 8. SNR, S/(N + D), and ENOB vs. Frequency

TPC 11. THD, Harmonics, and SFDR vs. Frequency

100

16.0

15.5

15.0

–60

–70

95

90

–80

SNR

–90

SINAD

–100

85

80

14.5

14.0

SECOND HARMONIC

THD

ENOB

–110

–120

–130

75

70

13.5

13.0

THIRD HARMONIC

–140

–150

10

100

1

1000

–60

–50

–40

–30

–20

–10

0

FREQUENCY – kHz

INPUT LEVEL – dB

TPC 9. SNR vs. Input Frequency

TPC 12. THD, Harmonics vs. Input Level

–16–

REV. A

AD15700

50

40

30

20

1000

900

800

700

600

DVDD

500

400

OVDD

300

200

10

0

AVDD

100

0

45

TEMPERATURE – ꢁC

105

0

50

100

– pF

150

200

–55

–35

–15

5

25

65

85

C

L

TPC 15. Power-Down Operating Currents vs. Temperature

TPC 13. Typical Delay vs. Load Capacitance C_L

100000

AVDD, WARP/NORMAL

10000

DVDD, WARP/NORMAL

1000

100

AVDD, IMPULSE

10

DVDD, IMPULSE

0

0.1

OVDD, ALL MODES

0.01

0.001

0

10

100

1000

10000

100000 1000000

SAMPLING RATE – SPS

TPC 14. Operating Currents vs. Sample Rate

REV. A

–17–

AD15700

14-BIT D/A CONVERTER

0.50

0.25

T

V

= 25ꢁC

T

= 25ꢁC

A

= 5V

V

= 5V

DD

= 2.5V

V

= 2.5V

REF

0.25

0

–0.25

–0.50

–0.25

–0.50

2048

0

4096

6144 8192 10240 12288 14336 16384

CODE – Decimal

0

4096

6144 8192 10240 12288 14336 16384

CODE – Decimal

TPC 16. Integral Nonlinearity vs. Code

TPC 19. Differential Nonlinearity vs. Code

0.50

0.25

0.50

V

= 5V

= 2.5V

V

= 5V

= 2.5V

DD

V

REF

0.25

0

–0.25

–0.50

–0.25

–0.50

–60

–20

20

60

100

140

–60

–20

20

60

100

140

TEMPERATURE – ꢁC

TPC 17. Integral Nonlinearity vs. Temperature

TPC 20. Differential Nonlinearity vs. Temperature

1.00

0.50

V

= 2.5V

= 25ꢁC

V

= 5V

= 25ꢁC

DD

T

0.75

0.50

0.25

0

A

DNL

0.25

0

DNL

–0.25

–0.50

–0.25

–0.50

INL

–0.75

–1.00

2

3

4

5

6

7

0

1

2

3

4

5

6

REFERENCEVOLTAGE –V

SUPPLYVOLTAGE – V

TPC 18. Linearity Error vs. Supply Voltage

TPC 21. Linearity Error vs. Reference Voltage

–18–

REV. A

AD15700

1.00

0.75

0.50

0.25

0

0.75

0.50

V

= 5V

= 2.5V

V

= 5V

DD

V

= 2.5V

REF

–0.25

–0.50

0.25

–0.75

–1.00

0

–50

–25

0

25

50

75

100

125

150

–25

0

25

50

75

100

125

150

TEMPERATURE – ꢁC

TPC 22. Gain Error vs. Temperature

TPC 25. Zero-Code Error vs. Temperature

250

450

400

V

= 5V

= 2.5V

DD

T

= 25ꢁC

A

V

LOGIC

REF

350

300

SUPPLY

VOLTAGE

200

V

= 2.5V

REF

REFERENCE

VOLTAGE

DD

250

V

= 5V

200

150

–40

0

1

2

3

4

5

6

–20

0

20

40

60

80

100

120

VOLTAGE –V

TEMPERATURE – ꢁC

TPC 23. Supply Current vs. Temperature

TPC 26. Supply Current vs. Reference Voltage or

Supply Voltage

400

350

300

250

300

250

200

V

= 5V

= 2.5V

25ꢁC

DD

T

V

= 25ꢁC

A

V

T

REF

= 5V

DD

=

A

= 2.5V

REF

150

100

200

150

50

0

1

2

3

4

5

0

2048

4096

6144

8192 10240 12288 14336 16384

DIGITAL INPUTVOLTAGE –V

CODE – Decimal

TPC 24. Supply Current vs. Digital Input Voltage

TPC 27. Reference Current vs. Code

REV. A

–19–

AD15700

90

80

70

60

50

40

30

20

800

600

400

200

0

N = 250

V

= 10V

S

V

= 5V

S

V

= 2.7V

S

–200

–400

–600

–800

10

0

–5 –4

–3

–2

–1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

10

V

– mV

COMMON-MODEVOLTAGE –V

DS

TPC 28. Typical V_OSDistribution @ V_S= 5 V

TPC 31. Input Bias Current vs. Common-Mode Voltage

2.5

2.3

2.1

0

–0.1

–0.2

V

= 5V

S

V

= 5V

S

–0.3

–0.4

1.9

V

= 65V

S

1.7

1.5

–0.5

–0.6

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE – ꢁC

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5 5.0

COMMON-MODEVOLTAGE –V

TPC 29. Input Offset Voltage vs. Temperature

TPC 32. V_OSvs. Common-Mode Voltage

1.00

0.95

0.90

1000

950

900

850

800

750

700

ꢃI = ꢃ5V

S

V

= 5V

S

0.85

0.80

0.75

0.70

0.65

0.60

ꢄI = ꢄ5V

S

ꢄI = ꢄ2.7V

S

650

600

0.55

0.50

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE – ꢁC

TPC 30. Input Bias Current vs. Temperature

TPC 33. Supply Current vs. Temperature

–20–

REV. A

AD15700

AMPLIFIER

0

1.2

1.0

V

= 2.7V

CC

V

= 10V

CC

V

OUT

–0.5

V

IN

R

LOAD

0.8

0.6

0.4

V

= 5V

CC

EE

–1.0

–1.5

V

2

CC

V

CC

V

= 5V

CC

V

OUT

V

IN

R

LOAD

V

= 10V

CC

–2.0

–2.5

V

EE

0.2

0

V

2

CC

V

= 2.7V

CC

100

1k

10k

100

1k

10k

R

–ꢂ

R

–ꢂ

LOAD

TPC 34. +Output Saturation Voltage vs. R_LOAD@ 85∞C

TPC 37. –Output Saturation Voltage vs. R_LOAD@ 85∞C

0

1.2

V

= 2.7V

CC

V

= 10V

CC

1.0

V

OUT

–0.5

V

IN

R

LOAD

0.8

0.6

0.4

V

= 5V

V

CC

EE

–1.0

–1.5

V

2

CC

V

CC

V

= 5V

CC

V

OUT

V

IN

R

LOAD

V

= 10V

CC

–2.0

–2.5

V

EE

0.2

0

V

2

CC

V

= 2.7V

CC

100

1k

10k

100

1k

10k

R

–ꢂ

R

–ꢂ

LOAD

TPC 35. +Output Saturation Voltage vs. R_LOAD@ 25∞C

TPC 38. –Output Saturation Voltage vs. R_LOAD@ 25∞C

0

1.2

V

= 2.7V

CC

V

= 10V

CC

1.0

V

OUT

–0.5

V

IN

R

LOAD

0.8

0.6

0.4

V

= 5V

V

CC

EE

–1.0

–1.5

V

2

CC

V

CC

V

= 5V

CC

V

OUT

V

IN

R

LOAD

V

= 10V

CC

–2.0

–2.5

V

EE

0.2

0

V

2

CC

V

= 2.7V

CC

100

1k

10k

100

1k

10k

R

–ꢂ

R

–ꢂ

LOAD

TPC. 36 +Output Saturation Voltage vs. R_LOAD@ –40∞C

TPC. 39 –Output Saturation Voltage vs. R_LOAD@ –40∞C

REV. A

–21–

AD15700

110

V

= 5V

S

1V

500mV

105

100

90

100

95

90

85

80

75

70

65

–A

OL

10

0

+A

OL

V

= 5V

S

–10

10

0%

500mV

60

0

–1.5

0.5

2.5

4.5

6.5

2k

4k

6k

–ꢂ

8k

10k

INPUT VOLTAGE –V

R

LOAD

TPC 40. Open-Loop Gain (A_OL) vs. R_LOAD

TPC 43. Differential Input Voltage 1 V Characteristics

86

84

82

80

0.05

0.00

V

= 5V

= 1kꢂ

S

R

L

–0.05

–0.10

–0.15

–A

OL

1ST 2ND 3RD 4TH 5TH

6TH 7TH 8TH 9TH 10TH 11TH

+A

OL

0.10

0.05

0.00

78

76

–0.05

–0.10

1ST 2ND 3RD 4TH 5TH

6TH 7TH 8TH 9TH 10TH 11TH

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE – ꢁC

TPC 41. Open-Loop Gain (A_OL) vs. Temperature

TPC 44. Differential Gain and Phase @ V_S= ±5 V;

R_L= 1 kW

110

100

V

= 5V

S

V

= 5V

S

R

= 10kꢂ

= 1kꢂ

LOAD

100

90

30

100

VOLTAGE NOISE

10

3

10

1

R

LOAD

80

70

CURRENT NOISE

1

0.1

60

50

0.3

1k

100k

1M

100

10k

10M

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5 5.0

10

V

– V

FREQUENCY – Hz

OUT

TPC 42. Open-Loop Gain (A_OL) vs. V_OUT

TPC 45. Input Voltage Noise vs. Frequency

–22–

REV. A

AD15700

5

4

3

2

1

V

= 5V

S

G = +1

= 1kꢂ

40

30

20

10

0

R

L

GAIN

0

–1

–2

–3

–4

–5

–10

–90

–135

–180

–225

PHASE

–20

0.1

1

10

100

0.3

1

10

100

FREQUENCY – MHz

TPC 46. Unity Gain, –3 dB Bandwidth

TPC 49. Open-Loop Frequency Response

3

2

–20

V

= 5V

= –16dBm

S

IN

–30

–40

–50

–60

+85ꢁC

V

CC

1

0

G = +1, R = 2kꢂTO

L

–40ꢁC

2

1.3V p-p

= 2.7V

V

+25ꢁC

S

–1

–2

2.5V p-p

= 2.7V

V

S

V

S

2kꢂ

V

OUT

2V p-p

= 2.7V

–3

–4

–5

V

S

IN

50ꢂ

–70

–80

4.8V p-p

= 5V

V

S

0.1

1

10

100

1k

100k

1M

10k

10M

FREQUENCY – MHz

FUNDAMENTAL FREQUENCY – Hz

TPC 47. Closed-Loop Gain vs. Temperature

TPC 50. Total Harmonic Distortion vs. Frequency; G = +1

2

–20

V

R

= 5V

V

= –2.7V

S

1

0

+ C

R

+ C TO 1.35V

L

G = +2

–30

L

TO 2.5V

V

R

= 5V

= 1kꢂTO

S

V

CC

L

–40

–50

–60

–70

–80

2

V

= 65V

S

–1

–2

4.8V p-p

1V p-p

–3

–4

–5

–6

–7

–8

G = +1

= 5pF

= 1kꢂ

C

R

L

4.6V p-p

4V p-p

1M

–90

–100

10k

1M

10M

FREQUENCY – Hz

100M

1k

100k

10k

10M

FUNDAMENTAL FREQUENCY – Hz

TPC 48. Closed-Loop Gain vs. Supply Voltage

TPC 51. Total Harmonic Distortion vs. Frequency; G = +2

REV. A

–23–

AD15700

10

0

V

= 65V

S

–20

8

6

4

2

V

= 5V

S

–40

–60

–80

V

= 5V

S

V

= 2.7V

S

–100

–120

0

100

1k

100k

1M

10k

10M

100M

1k

100k

1M

10k

10M

FREQUENCY – Hz

FUNDAMENTAL FREQUENCY – Hz

TPC 55. PSRR vs. Frequency

TPC 52. Large Signal Response

V

= 5V

= 10kꢂTO 2.5V

= 6V p-p

S

L

R

V

IN

100

50

G = +1

RB = 50ꢂ

5.5

T

4.5

3.5

2.5

1.5

10

1

0.5

RB–

V

OUT

–0.5

0.1

RB = 0

T

0.1

1

10

100 200

10ꢀs/DIV

FREQUENCY – MHz

TPC 53. R_OUTvs. Frequency

TPC 56. Output Voltage

0

V

= 5V

S

V

= 5V

S

G = +1

INPUT = 650mV

BEYOND RAILS

INPUT

–20

5.5

4.5

–40

–60

–80

3.5

2.5

1.5

0.5

–0.5

–100

100

1k

100k

10k

FREQUENCY – Hz

1M

10M

10ꢀs/DIV

TPC 54. CMRR vs. Frequency

TPC 57. Output Voltage Phase Reversal Behavior

–24–

REV. A

AD15700

V

R

= 27V

= 1kꢂ

S

L

R

TO 2.5V

L

G = –1

2.85

2.35

1.85

1.35

0.85

R

1.35V

TO

L

0.35

V

R

= 5V

= 1kV

S

L

R

TO GND

R

TO GND

L

G = –1

0

10ꢀs/DIV

TPC 58. Output Swing

TPC 60. Output Swing

G = +2

R

C

V

= R = 2.5kꢂ

F

L

G

= 2kꢂ

= 5pF

= 5V

3.1

2.56

S

2.9

2.7

2.5

2.3

2.1

1.9

2.54

2.52

2.50

2.48

2.46

2.44

50ns/DIV

TPC 59. 1 V Step Response

TPC 61. 100 mV Step Response

REV. A

–25–

AD15700

CIRCUIT OPERATION

TYPICAL CONNECTION DIAGRAM

The AD15700 contains precision components for interfacing

analog I/O to a processor. Configuration for particular applications

can be made with short external interconnects under the device.

Figure 4 shows how, using a minimum of external devices, the com-

ponents within the AD15700 can be interconnected to form a

complete analog interface to a processor. The circuit implements signal

conditioning that includes buffering, filtering, and voltage scaling.

AD15700

ANALOG INPUT

+IN2

OP-AMP

VOUT2

+VS2

(0.2VTO 2REF)

STATE MACHINE

+VS

–IN2

–VS2

RESISTOR

RA2

RB2

RPAD2

RFS

TFS

RCLK

TCLK

RC2

C2

NOTE 2

ADC

INA

INB

SCLK

CNVST

DSP/ꢀP

INC

IND

SDOUT

BUSY

INGND

DVDD

OB/2C

ADR421 OR

AD780 2.5V OR

3.0V REF

SER/PAR

WARP

RDC/SIN

INVSCLK

INVSYNC

EXT/INT

DIVSCLK1

DIVSCLK0

IMPULSE

CS_ADC

RD

REF

REFGND

47ꢀF

0.1ꢀF

ANALOG

SUPPLY (5V)

AVDD

AGND_ADC

100ꢂ

DVDD

0.1

DGND_ADC

AGND

ꢀF

10ꢀF

DIGITAL SUPPLY

(3.3V OR 5V)

OVDD

OGND

BYTESWAP

RESET

PD

0.1ꢀF

DAC

VREF

SCLK

DGND

VDD_DAC

DGND_DAC

AGND_DAC

VOUT_DAC

CS_DAC

DIN

RESISTOR

RA1

RB1

RC1

RPAD1

OP AMP

+IN1

–IN1

+VS1

–VS1

VOUT1

+VS

0.1ꢀF

C1

NOTE 1

ANALOG OUTPUT

(0.2VTO 2REF)

NOTES

1. C1 FORMS AN R-C FILTERWITHTHE 6.25kꢂ NOMINAL OUTPUT RESISTANCE OFTHE DAC

2. C2 FORMS PART OFTHE ADC INPUT FILTER. SEE ANALOG INPUT SECTION.

Figure 4. Typical Connection Diagram

–26–

REV. A

AD15700

Analog Input Section

Processor Interface

Made up of a buffer amplifier, an RC filter, and an ADC, the

analog input circuit allows measurement of voltages ranging from

0.2 V to 2 REF V. When placed in the 0 V to REF input range,

the circuit has the configuration shown in Figure 5a.

The circuit in Figure 5a uses serial interfacing to minimize the

number of signals that connect to the digital circuits. External

logic such as a state machine is used to generate clocks and other

timing signals for the interface. Ideally, the clocks supplied to the

converters are discontinuous and operate at the maximum frequency

supported by the converter and the processor. Discontinuous

clocks that are quiet during critical times minimize degradation

caused by voltage transients on the digital interface. It is best to

keep the clocks quiet during ADC conversion and when the DAC

output is sampled by the external system. Often, the processor

cannot tolerate a discontinuous clock and therefore a separate

continuous clock (or clocks) that is synchronous with the converter

clocks must be generated. Separate clocks for the DAC and ADC

are used to maximize the data transfer rate to each converter.

The ADC operates at a maximum rate of 40 MHz while the DAC

can operate up to 25 MHz.

ADC

ANALOG

INPUT

1.5kꢂ

277ꢂ

60pF

C2

Figure 5a. Analog Input Circuit

The filter is made up of one of the AD15700’s internal center-

tapped resistors, an external capacitor C2, plus the ADC’s internal

resistance and capacitance. The transfer function of this filter is

given by:

8.11425¥10⁶

H s =

( )

ADC CIRCUIT INFORMATION

1.62285¥10⁷+ 202.288 s²C2 + s +1.21714 ¥10¹⁰sC2

The ADC is a fast, low power, single-supply precise 16-bit analog-

to-digital converter (ADC). It features different modes to optimize

performances according to the applications.

With C2 set to 100 pF, the bandwidth is 1.2 MHz. Without C2,

the bandwidth of the filter is 2.6 MHz. To utilize the ADC’s

maximum 9.6 MHz bandwidth, the components external to the

ADC are eliminated. In this case, the ADC is configured for its

0 to 2 REF input range and the resulting equivalent input circuit

is shown in Figure 5b.

In warp mode, it is capable of converting 1,000,000 samples per

second (1 MSPS).

The ADC provides the user with an on-chip track/hold, successive

approximation ADC that does not exhibit any pipeline or latency,

making it ideal for multiple multiplexed channel applications.

ADC

100ꢂ

ANALOG

INPUT

375ꢂ

It is specified to operate with both bipolar and unipolar input

ranges by changing the connection of its input resistive scaler.

60pF

The ADC can be operated from a single 5 V supply and be inter-

faced to either 5 V or 3 V digital logic.

Figure 5b. Analog Input Circuit

Analog Output Section

ADC CONVERTER OPERATION

The ADC is a successive approximation analog-to-digital con-

verter based on a charge redistribution DAC. Figure 7 shows the

simplified schematic of the ADC. The input analog signal is first

scaled down and level-shifted by the internal input resistive scaler,

which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V, and

0 to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V). The

output voltage range of the resistive scaler is always 0 V to 2.5 V.

The capacitive DAC consists of an array of 16 binary weighted

capacitors and an additional LSB capacitor. The comparator’s

negative input is connected to a “dummy” capacitor of the same

value as the capacitive DAC array.

The output circuitry consists of a DAC, RC filter, and an amplifier.

The circuit uses the DAC’s output resistance of 6.25 kW ± 20%

to form a single-pole RC filter with an external capacitor C1. One

of the AD15700’s internal center-tapped resistors and one of its

op amps form an amplifier with a gain of two. The gain is used to

bring the DAC’s maximum range of REF volts up to 2 REF V.

DAC

ANALOG

OUTPUT

6.25kꢂ

C1

1.5kꢂ

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND

via SWA. All independent switches are connected to the output

of the resistive scaler. Thus, the capacitor array is used as a

sampling capacitor and acquires the analog signal. Similarly, the

dummy capacitor acquires the analog signal on INGND input.

Figure 6. Analog Output Circuit

Voltage Reference Input

The AD15700 uses an external 2.5 V or 3.0 V voltage reference.

Because of the dynamic input impedance of the A/D and the

code dependent impedance of the D/A, the reference inputs must

be driven by a low impedance source. Decoupling consisting of a

parallel combination of 47 mF and 0.1 mF capacitors is recom-

mended. Suitable references include the ADR421 for 2.5 V output

and the AD780 for selectable 2.5 V or 3.0 V output. Both of these

feature low noise and low temperature drift.

When the acquisition phase is complete, and the CNVST input

goes or is low, a conversion phase is initiated. When the conversion

phase begins, SWA and SWB are opened first. The capacitor

array and the dummy capacitor are then disconnected from the

inputs and connected to the REFGND input. Therefore, the differ-

ential voltage between the output of the resistive scaler and INGND

captured at the end of the acquisition phase is applied to the

comparator inputs, causing the comparator to become unbalanced.

REV. A

–27–

AD15700

4R

IND

REF

4R

REFGND

INC

SWITCHES

CONTROL

MSB

LSB

2R

SW

A

INB

32768C

16384C

4C

2C

C

R

BUSY

INA

CONTROL

LOGIC

COMP

OUTPUT

CODE

INGND

65536C

SW

B

CNVST

Figure 7. ADC Simplified Schematic

in this mode is 666 kSPS. When operating at 100 SPS, for

example, it typically consumes only 15 mW. This feature makes

the ADC ideal for battery-powered applications.

By switching each element of the capacitor array between REFGND

or REF, the comparator input varies by binary weighted voltage

steps (VREF/2, VREF/4. . .VREF/65536). The control logic

toggles these switches, starting with the MSB first, in order to

bring the comparator back into a balanced condition. After the

completion of this process, the control logic generates the ADC

output code and brings BUSY output low.

Transfer Functions

Using the OB/2C digital input, the ADC offers two output

codings: straight binary and twos complement. The ideal transfer

characteristic for the ADC is shown in Figure 8 and Table III.

Modes of Operation

The ADC features three modes of operation: warp, normal,

and impulse. Each of these modes is more suitable for specific

applications.

111...111

111...110

111...101

The warp mode allows the fastest conversion rate up to

1

MSPS. However, in this mode and this mode only, the full

specified accuracy is guaranteed only when the time between

conversion does not exceed 1 ms. If the time between two con-

secutive conversions is longer than 1 ms, for instance, after

power-up, the first conversion result should be ignored. This

mode makes the ADC ideal for applications where both high

accuracy and fast sample rate are required.

000...010

000...001

The normal mode is the fastest mode (800 kSPS) without any

limitation about the time between conversions. This mode makes

the ADC ideal for asynchronous applications such as data

acquisition systems, where both high accuracy and fast sample

rate are required.

000...000

–FS

–FS + 1LSB

+FS – 1LSB

+FS – 1.5LSB

ANALOG INPUT

–FS + 0.5LSB

The impulse mode, the lowest power dissipation mode, allows

power saving between conversions. The maximum throughput

Figure 8. ADC Ideal Transfer Function

Table III. Output Codes and Ideal Input Voltages

Digital Output Code

(Hexadecimal)

Straight Twos

Binary Complement

Description

Analog Input

0 V to 10 V 0 V to 5 V

152.6 mV 76.3 mV

Full-Scale Range

Least Significant Bit 305.2 mV

±10 V

±5 V

±2.5 V

0 V to 2.5 V

38.15 mV

152.6 mV

76.3 mV

FSR –1 LSB

Midscale +1 LSB

Midscale

Midscale –1 LSB

–FSR +1 LSB

–FSR

9.999695 V

305.2 mV

0 V

4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF¹

7FFF¹

0001

0000

152.6 mV

0 V

–152.6 mV

76.3 mV

5.000153 V 2.570076 V 1.257038 V 8001

5 V 2.5 V 1.25 V 8000

4.999847 V 2.499924 V 1.249962 V 7FFF

0 V

–305.2 mV

–76.3 mV

FFFF

8001

–9.999695 V –4.999847 V –2.499924 V 152.6 mV

76.3 mV

0 V

38.15 mV

0 V

0001

–10 V

–5 V

–2.5 V

0 V

0000²

8000²

NOTES

¹This is also the code for an overrange analog input.

²This is also the code for an underrange analog input.

–28–

REV. A

AD15700

Analog Inputs

The capacitor C_Sis typically 60 pF and is mainly the ADC

sampling capacitor. This one-pole filter with a typical –3 dB

cutoff frequency of 9.6 MHz reduces undesirable aliasing effects

and limits the noise coming from the inputs.

The ADC is specified to operate with six full-scale analog input

ranges. Connections required for each of the four analog inputs,

IND, INC, INB, INA, and the resulting full-scale ranges are

shown in Table I. The typical input impedance for each analog

input range is also shown.

75

70

Figure 9 shows a simplified analog input section of the ADC.

AVDD

65

60

55

50

45

4R

IND

4

INC

R1

2R

R

INB

INA

C

S

40

35

R = 1.28kꢂ

1

10

100

1000

10000

FREQUENCY – kHz

AGND

Figure 10. Analog Input CMRR vs. Frequency

Except when using the 0 V to 2.5 V analog input voltage range,

the ADC has to be driven by a very low impedance source to

avoid gain errors. That can be done by using the driver amplifier.

Figure 9. Simplified Analog Input

The four resistors connected to the four analog inputs form a

resistive scaler that scales down and shifts the analog input range

to a common input range of 0 V to 2.5 V at the input of the

switched capacitive ADC.

When using the 0 V to 2.5 V analog input voltage range, the

input impedance of the ADC is very high so the ADC can be

driven directly by a low impedance source without gain error.

That allows putting an external one-pole RC filter between the

output of the amplifier output and the ADC analog inputs to

even further improve the noise filtering done by the ADC analog

input circuit. However, the source impedance has to be kept low

because it affects the ac performances, especially the total harmonic

distortion (THD). The maximum source impedance depends on

the amount of total THD that can be tolerated. The THD degra-

dation is a function of the source impedance and the maximum

input frequency, as shown in Figure 11.

By connecting the four inputs INA, INB, INC, and IND to the

input signal itself, the ground, or a 2.5 V reference, other analog

input ranges can be obtained.

The diodes shown in Figure 9 provide ESD protection for the

four analog inputs. The inputs INB, INC, and IND, have a high

voltage protection (–11 V to +30 V) to allow wide input voltage

range. Care must be taken to ensure that the analog input signal

never exceeds the absolute ratings on these inputs including

INA (0 V to 5 V). This will cause these diodes to become for-

ward-biased and start conducting current. These diodes can

handle a forward-biased current of 120 mA maximum. For

instance, when using the 0 V to 2.5 V input range, these condi-

tions could eventually occur on the input INA when the input

buffer’s (U1) supplies are different from AVDD. In such case,

an input buffer with a short circuit current limitation can be

used to protect the part.

–70

R = 100ꢂ

–80

R = 50ꢂ

This analog input structure allows the sampling of the differential

signal between the output of the resistive scaler and INGND.

Unlike other converters, the INGND input is sampled at the same

time as the inputs. By using this differential input, small signals

common to both inputs are rejected as shown in Figure 10, which

represents the typical CMRR over frequency. For instance, by

using INGND to sense a remote signal ground, differences of

ground potentials between the sensor and the local ADC ground

are eliminated. During the acquisition phase for ac signals, the

ADC behaves like a one-pole RC filter consisting of the equivalent

resistance of the resistive scaler R/2 in series with R1 and C_S. The

resistor R1 is typically 100 W and is a lumped component made

up of some serial resistor and the on resistance of the switches.

–90

R = 11ꢂ

–100

–110

0

100

1000

FREQUENCY – kHz

Figure 11. THD vs. Analog Input Frequency and

Input Resistance (0 V to 2.5 V Only)

REV. A

–29–

AD15700

Driver Amplifier Choice

Although the ADC is easy to drive, the driver amplifier needs to

meet at least the following requirements:

Care should also be taken with the reference temperature coefficient

of the voltage reference, which directly affects the full-scale

accuracy if this parameter matters. For instance, a ±15 ppm/∞C

tempco of the reference changes the full scale by ±1 LSB/∞C.

∑ The driver amplifier and the ADC analog input circuit

must be able, together, to settle for a full-scale step of the

capacitor array at a 16-bit level (0.0015%).

Scaler Reference Input (Bipolar Input Ranges)

When using the ADC with bipolar input ranges, a buffer amplifier

is required to isolate the REFIN pin from the signal dependent

current in the AIN pin. A high speed op amp can be used with a

single 5 V power supply without degrading the performance of

the ADC. The buffer must have good settling characteristics and

provide low total noise within the input bandwidth of the ADC.

∑ The noise generated by the driver amplifier needs to be kept

as low as possible in order to preserve the SNR and transition

noise performance of the ADC. The noise coming from the

driver is first scaled down by the resistive scaler according

to the analog input voltage range used, and is then filtered

by the ADC analog input circuit one-pole, low-pass filter

made by (R/2 + R1) and CS. The SNR degradation due to

the amplifier is:

Power Supply

The ADC uses three sets of power supply pins: an analog 5 V

supply AVDD, a digital 5 V core supply DVDD, and a digital

input/output interface supply OVDD. The OVDD supply allows

direct interface with any logic working between 2.7 V and 5.25 V.

To reduce the number of supplies needed, the digital core (DVDD)

can be supplied through a simple RC filter from the analog

supply. The ADC is independent of power supply sequencing and

thus free from supply voltage induced latchup. Additionally, it is

very insensitive to power supply variations over a wide frequency

range, as shown in Figure 12.

Ê

ˆ

Á

˜

28

Ê 2.5 N e_Nˆ²

SNR_LOSS= log

p

2

784 + f_{–3 dB}

Á

˜

Á

˜

FSR

Ë

¯

Ë

¯

where:

_{–3 dB}is the –3 dB input bandwidth in MHz of the ADC

(9.6 MHz) or the cutoff frequency of the input filter if

any is used (0 V to 2.5 V range).

75

70

65

60

f

N is the noise factor of the amplifier (1 if in buffer

configuration).

e_Nis the equivalent input noise voltage of the op amp

in nV/÷Hz.

55

50

45

FSR is the full-scale span (i.e., 5 V for ±2.5 V range).

For instance, when using the 0 V to 5 V range, a driver like

the AD15700’s internal op amp, with an equivalent input

noise of 15 nV/÷Hz and configured as a buffer, followed by

a 3.2 MHz RC filter, the SNR degrades by about 1.3 dB.

40

35

1

10

100

1000

10000

FREQUENCY – kHz

∑ The driver needs to have a THD performance suitable

to that of the ADC. Figure 11 gives the THD versus

frequency that the driver should preferably exceed.

Figure 12. PSRR vs. Frequency

POWER DISSIPATION

Voltage Reference Input

In impulse mode, the ADC automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low, which

allows a significant power savings when the conversion rate is

reduced, as shown in Figure 13. This feature makes the ADC

ideal for very low power battery applications.

The ADC uses an external 2.5 V voltage reference. The voltage

reference input REF of the ADC has a dynamic input impedance.

Therefore, it should be driven by a low impedance source with

an efficient decoupling between REF and REFGND inputs. This

decoupling depends on the choice of the voltage reference, but

usually consists of a low ESR tantalum capacitor connected to the

REF and REFGND inputs with minimum parasitic inductance.

47 mF is an appropriate value for the tantalum capacitor when

used with one of the recommended reference voltages:

This does not take into account the power, if any, dissipated by

the input resistive scaler, which depends on the input voltage

range used and the analog input voltage even in power-down

mode. There is no power dissipated when the 0 V to 2.5 V is

used or when both the analog input voltage is 0 V and a unipolar

range, 0 V to 5 V or 0 V to 10 V, is used.

∑ The low noise, low temperature drift ADR421 or AD780

voltage references

∑ The low power ADR291 voltage reference

∑ The low cost AD1582 voltage reference

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, the digital inputs need to be driven

close to the power rails (i.e., DVDD and DGND) and OVDD

should not exceed DVDD by more than 0.3 V.

–30–

REV. A

AD15700

100000

10000

1000

100

For applications where the SNR is critical, CNVST signal should

have a very low jitter. One way to achieve that is to use a dedicated

oscillator for CNVST generation, or at least to clock it with a

high frequency low jitter clock.

WARP/NORMAL

t₉

RESET

10

BUSY

DATA

IMPULSE

1

0.1

1

10

100

1000

10000

100000 1000000

SAMPLING RATE – SPS

t₈

Figure 13. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

CNVST

Figure 14 shows the detailed timing diagrams of the conversion

process. The ADC is controlled by the signal CNVST, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The CNVST signal operates independently of

CS_ADC and RD signals.

Figure 15. RESET Timing

DIGITAL INTERFACE

The ADC has a versatile digital interface; it can be interfaced with

the host system by using either a serial or parallel interface. The

serial interface is multiplexed on the parallel data bus. The ADC

digital interface also accommodates both 3 V or 5 V logic by simply

connecting the OVDD supply pin of the ADC to the host system

interface digital supply. Finally, by using the OB/2C input pin,

both straight binary or twos complement coding can be used.

t₂

t₁

CNVST

The two signals, CS_ADC and RD, control the interface. When

at least one of these signals is high, the interface outputs are in

high impedance. Usually, CS_ADC allows the selection of each

ADC in multicircuit applications and is held low in a single

ADC design. RD is generally used to enable the conversion

result on the data bus.

BUSY

t₄

t₃

t₆

t₅

MODE

CONVERT

t₇

ACQUIRE

t₈

CONVERT

ACQUIRE

CS_ADC = RD = 0

t₁

Figure 14. Basic Conversion Timing

CNVST

In impulse mode, conversions can be automatically initiated.

If CNVST is held low when BUSY is low, the ADC controls the

acquisition phase and then automatically initiates a new conversion.

By keeping CNVST low, the ADC keeps the conversion process

running by itself. It should be noted that the analog input has to

be settled when BUSY goes low. Also, at power-up, CNVST

should be brought low once to initiate the conversion process.

In this mode, the ADC could sometimes run slightly faster than

the guaranteed limits in the impulse mode of 666 kSPS. This

feature does not exist in warp or normal modes.

t₁₀

BUSY

t₄

t₃

t₁₁

NEW DATA

DATA BUS

PREVIOUS CONVERSION DATA

Figure 16. Master Parallel Data Timing for Reading

(Continuous Read)

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing. It is a good thing to shield

the CNVST trace with ground and also to add a low value serial

resistor (i.e., 50 W) termination close to the output of the com-

ponent that drives this line.

REV. A

–31–

AD15700

PARALLEL INTERFACE

The ADC is configured to use the parallel interface when the

SER/PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or during

the following conversion as shown, respectively, in Figures 18

and 19. When the data is read during the conversion, however, it

is recommended that it be read only during the first half of the

conversion phase. That avoids any potential feedthrough between

voltage transients on the digital interface and the most critical

analog conversion circuitry.

CS_ADC

RD

BYTE

HI-Z

PINS D[15.8]

PINS D[7.0]

HIGH BYTE

LOW BYTE

t₁₂

t₁₃

HI-Z

LOW BYTE

HIGH BYTE

CSZ_ADC

Figure 19. 8-Bit Parallel Interface

SERIAL INTERFACE

RD

The ADC is configured to use the serial interface when the

SER/PAR is held high. The ADC outputs 16 bits of data, MSB

first, on the SDOUT pin. This data is synchronized with the

16 clock pulses provided on the SCLK pin. The output data is

valid on both the rising and falling edge of the data clock.

BUSY

MASTER SERIAL INTERFACE

Internal Clock

CURRENT

CONVERSION

DATA BUS

The ADC is configured to generate and provide the serial data

clock SCLK when the EXT/INT pin is held low. It also generates

a SYNC signal to indicate to the host when the serial data is valid.

The serial clock SCLK and the SYNC signal can be inverted if

desired. Depending on RDC/SDIN input, the data can be read

after each conversion or during conversion. Figures 20 and 21

show the detailed timing diagrams of these two modes.

t₁₃

t₁₂

Figure 17. Slave Parallel Data Timing for Reading

(Read after Convert)

CS_ADC = 0

t₁

CNVST, RD

Usually, because the ADC is used with a fast throughput, the

mode master read during conversion is the most recommended

serial mode when it can be used.

In read during conversion mode, the serial clock and data toggle at

appropriate instants, which minimizes potential feedthrough

between digital activity and the critical conversion decisions.

BUSY

t₄

t₃

In read after conversion mode, it should be noted that unlike in

other modes, the signal BUSY returns low after the 16 data bits

are pulsed out and not at the end of the conversion phase, which

results in a longer BUSY width.

CONVERSION

t₁₂

t₁₃

Figure 18. Slave Parallel Data Timing for Reading

(Read during Convert)

SLAVE SERIAL INTERFACE

External Clock

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 19, the LSB byte is output on D[7:0] and

the MSB is output on D[15:8] when BYTESWAP is low. When

BYTESWAP is high, the LSB and MSB are swapped and the

LSB is output on D[15:8] and the MSB is output on D[7:0]. By

connecting BYTESWAP to an address line, the 16 data bits can

be read in two bytes on either D[15:8] or D[7:0].

The ADC is configured to accept an externally supplied serial

data clock on the SCLK pin when the EXT/INT pin is held

high. In this mode, several methods can be used to read the data.

The external serial clock is gated by CS_ADC and the data are

output when both CS_ADC and RD are low. Thus, depending on

CS_ADC, the data can be read after each conversion or during

the following conversion. The external clock can be either a

continuous or discontinuous clock. A discontinuous clock can be

either normally high or normally low when inactive. Figure 22 and

Figure 24 show the detailed timing diagrams of these methods.

–32–

REV. A

AD15700

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

EXT/INT = 0

CS_ADC, RD

t₃

CNVST

BUSY

SYNC

t₂₈

t₃₀

t₂₉

t₂₅

t₁₈

t₁₉

t₁₄

t₂₄

t₂₀

t₂₁

t₂₆

14

1

2

3

15

16

SCLK

t₁₅

t₂₇

D2

D1

SDOUT

X

D15

D14

t₂₃

D0

t₁₆

t₂₂

Figure 20. Master Serial Data Timing for Reading (Read after Convert)

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

EXT/INT = 0

CS_ADC, RD

t₁

CNVST

t₃

BUSY

SYNC

t₁₇

t₂₅

t₁₄

t₁₉

t₂₀t₂₁

t₂₄

t₂₆

t₁₅

SCLK

1

2

3

14

15

16

t₁₈

t₂₇

SDOUT

X

D15

D14

t₂₃

D0

D1

D2

t₁₆

t₂₂

Figure 21. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

INVSCLK = 0

EXT/INT = 1

RD = 0

CS_ADC, RD

BUSY

t₃₅

t₃₆

t

37

SCLK

SDOUT

SDIN

1

2

3

14

15

16

17

18

t₃₁

t₃₂

X

D15

t₃₄

D14

D13

X13

D1

X1

D0

X0

X15

Y15

X14

Y14

t₁₆

X15

X14

t₃₃

Figure 22. Slave Serial Data Timing for Reading (Read after Convert)

–33–

REV. A

AD15700

BUSY

OUT

While the ADC is performing a bit decision, it is important that

voltage transients not occur on digital input/output pins or

degradation of the conversion result could occur. This is particu-

larly important during the second half of the conversion phase

because the ADC provides error correction circuitry that can

correct for an improper bit decision made during the first half of

the conversion phase. For this reason, it is recommended that when

an external clock is being provided, it is a discontinuous clock

that is toggling only when BUSY is low or, more importantly,

that it does not transition during the latter half of BUSY high.

BUSY

AD15700

NO. 2

(UPSTREAM)

AD15700

NO. 1

(DOWNSTREAM)

DATA

OUT

RDC/SDIN SDOUT

CNVST

CS_ADC

SCLK

CNVST

CS_ADC

SCLK

External Discontinuous Clock Data Read after Conversion

Though the maximum throughput cannot be achieved using this

mode, it is the most recommended of the serial slave modes.

Figure 22 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning low,

the result of this conversion can be read while both CS_ADC and

RD are low. The data is shifted out, MSB first, with 16 clock

pulses and is valid on both the rising and falling edge of the clock.

Among the advantages of this method is that the conversion perfor-

mance is not degraded because there are no voltage transients on

the digital interface during the conversion process. Another advan-

tage is to be able to read the data at any speed up to 40 MHz,

which accommodates both slow digital host interface and the

fastest serial reading.

SCLK IN

CS_ADC IN

CNVST IN

Figure 23. Two AD15700s in a Daisy-Chain Configuration

External Clock Data Read during Conversion

Figure 24 shows the detailed timing diagrams of this method.

During a conversion, while both CS_ADC and RD are low, the

result of the previous conversion can be read. The data is shifted

out, MSB first, with 16 clock pulses and is valid on both the rising

and falling edge of the clock. The 16 bits have to be read before

the current conversion is complete. If that is not done, RDERROR

is pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain feature

in this mode and RDC/SDIN input should always be tied either

high or low.

Finally, in this mode only, the ADC provides a daisy-chain feature

using the RDC/SDIN input pin for cascading multiple converters

together. This feature is useful for reducing component count

and wiring connections when desired as, for instance, in isolated

multiconverter applications.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 25 MHz when impulse mode is

used, and 32 MHz when normal or 40 MHz when warp mode is

used, is recommended to ensure that all the bits are read during

the first half of the conversion phase. It is also possible to begin

to read the data after conversion and continue to read the last

bits even after a new conversion has been initiated. That allows

the use of a slower clock speed like 18 MHz in impulse mode,

21 MHz in normal mode, and 26 MHz in warp mode.

An example of the concatenation of two devices is shown in

Figure 23. Simultaneous sampling is possible by using a common

CNVST signal. It should be noted that the RDC/SDIN input is

latched on the opposite edge of SCLK of the one used to shift

out the data on SDOUT. Therefore, the MSB of the “upstream”

converter just follows the LSB of the “downstream” converter on

the next SCLK cycle.

INVSCLK = 0

EXT/INT = 1

RD = 0

CS_ADC

CNVST

BUSY

t₃

t₃₅

t₃₆t₃₇

SCLK

1

14

15

16

2

3

t₃₁

t₃₂

SDOUT

X

D15

D14

D13

D1

D0

t₁₆

Figure 24. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

–34–

REV. A

AD15700

DVDD

MICROPROCESSOR INTERFACING

ADSP-21065L*

AD15700*

SHARC^®

The ADC is ideally suited for traditional dc measurement appli-

cations supporting a microprocessor, and ac signal processing

applications interfacing to a digital signal processor. The ADC is

designed to interface either with a parallel 8-bit or 16-bit wide

interface or with a general-purpose serial port or I/O ports on a

microcontroller. A variety of external buffers can be used with the

ADC to prevent digital noise from coupling into the ADC. The

following sections illustrate the use of the ADC with an SPI

equipped microcontroller, the ADSP-21065L and ADSP-218x

signal processors.

SER/PAR

RDC/SDIN

RD

RFS

SYNC

EXT/INT

CS_ADC

INVSYNC

INVSCLK

SDOUT

SCLK

DR

RCLK

FLAG ORTFS

CNVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. Interfacing to the ADSP-21065L Using

the Serial Master Mode

SPI Interface (MC68HC11)

Figure 25 shows an interface diagram between the ADC and an SPI

equipped microcontroller like the MC68HC11. To accommodate

the slower speed of the microcontroller, the ADC acts as a slave

device and data must be read after conversion. This mode also

allows the daisy-chain feature. The convert command could be

initiated in response to an internal timer interrupt. The reading of

output data, one byte at a time, if necessary, could be initiated in

response to the end-of-conversion signal (BUSY going low) using

an interrupt line of the microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for master mode

(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit

(CPHA) = 1, and SPI Interrupt Enable (SPIE) = 1 by writing

to the SPI Control Register (SPCR). The IRQ is configured for

edge-sensitive-only operation (IRQE = 1 in OPTION register).

APPLICATION HINTS

Layout

The AD15700’s ADC has very good immunity to noise on the

power supplies as can be seen in Figure 12. However, care should

still be taken with regard to grounding layout.

The printed circuit board that houses the AD15700 should be

designed so the analog and digital sections are separated and

confined to certain areas of the board. This facilitates the use of

ground planes that can be easily separated. Digital and analog

ground planes should be joined in only one place, preferably

underneath the AD15700, or at least as close as possible to the

AD15700. If the AD15700 is in a system where multiple devices

require analog-to-digital ground connections, the connection should

still be made at one point only, a star ground point, which should

be established as close as possible to the AD15700. It is recom-

mended to avoid running digital lines under the device as these

will couple noise onto the die. The analog ground plane should

be allowed to run under the switching signals like CNVST or

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board, and should never run near

analog signal paths. Crossover of digital and analog signals should

be avoided. Traces on different but close layers of the board

should run at right angles to each other. This will reduce the

effect of feedthrough through the board.

DVDD

MC68HC11*

AD15700*

SER/PAR

EXT/INT

CS_ADC

RD

IRQ

BUSY

SDOUT

SCLK

MSO/SDI

SCK

INVSCLK

I/O PORT

CNVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. Interfacing the AD15700 to SPI Interface

The power supply lines to the AD15700 should use as large a trace

as possible to provide low impedance paths and reduce the effect

of glitches on the power supply lines. Good decoupling is also impor-

tant to lower the supply impedance presented to the AD15700

and reduce the magnitude of the supply spikes. Decoupling

ceramic capacitors, typically 100 nF, should be placed on each

power supply pin, AVDD, DVDD, and OVDD, close to and

ideally right up against these pins and their corresponding ground

pins. Additionally, low ESR 10 nF capacitors should be located

in the vicinity of the ADC to further reduce low frequency ripple.

ADSP-21065L in Master Serial Interface

As shown in Figure 26, AD15700s can be interfaced to the

ADSP-21065L using the serial interface in master mode without

any glue logic required. This mode combines the advantages of

reducing the wire connections and the ability to read the data

during or after conversion at maximum speed transfer

(DIVSCLK[0:1] both low).

The ADC is configured for the internal clock mode (EXT/INT

low) and acts, therefore, as the master device. The convert com-

mand can be generated by either an external low jitter oscillator

or, as shown, by a FLAG output of the ADSP-21065L or by a

frame output TFS of one serial port of the ADSP-21065L,

which can be used like a timer. The serial port on the ADSP-21065L

is configured for external clock (IRFS = 0), rising edge active

(CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1,

RFSR = 1), and active high (LRFS = 0). The serial port of the

ADSP-21065L is configured by writing to its receive control

register (SRCTL)—see the ADSP-2106x SHARC User’s Manual.

Because the serial port within the ADSP-21065L will be seeing

a discontinuous clock, an initial word reading has to be done

after the ADSP-21065L has been reset to ensure that the serial

port is properly synchronized to this clock during each following

data read operation.

The DVDD supply of the AD15700 can be either a separate supply

or come from the analog supply, AVDD, or from the digital

interface supply, OVDD. When the system digital supply is noisy,

or fast switching digital signals are present, it is recommended if

no separate supply is available to connect the DVDD digital supply

to the analog supply AVDD through an RC filter, and connect

the system supply to the interface digital supply OVDD and the

remaining digital circuitry. When DVDD is powered from the

system supply, it is useful to insert a bead to further reduce high

frequency spikes.

REV. A

–35–

AD15700

The AD15700’s ADC has five different ground pins: INGND,

REFGND, AGND, DGND, and OGND. INGND is used to

sense the analog input signal. REFGND senses the reference

voltage and should be a low impedance return to the reference

because it carries pulsed currents. AGND is the ground to which

most internal ADC analog signals are referenced. This ground

must be connected with the least resistance to the analog ground

plane. DGND must be tied to the analog or digital ground plane

depending on the configuration. OGND is connected to the

digital system ground.

V

= 2.5V

= 5V

= 25ꢁC

REF

V

T

DD

V

(1V/DIV)

OUT

100

90

A

V

(50mV/DIV)

OUT

GAIN = –216

10

0%

The layout of the decoupling of the reference voltage is important.

The decoupling capacitor should be close to the ADC and connected

with short and large traces to minimize parasitic inductances.

0.5ꢀs/DIV

Figure 30. Small Signal Settling Time

V

= 2.5V

= 5V

REF

DAC Circuit Information

V

DD

The DAC is a single 14-bit, serial input voltage output. It

operates from a single supply ranging from 2.7 V to 5 V and

consumes typically 300 mA with a supply of 5 V. Data is written

to the devices in a 14-bit word format, via a 3- or 4-wire serial

interface. To ensure a known power-up state, the parts were

designed with a power-on reset function. In unipolar mode, the

output is reset to 0 V.

T = 25ꢁC

100

90

CLOCK (5V/DIV)

A

V

= (50mV/DIV)

OUT

10

Digital-to-Analog Section

0%

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 31. The four

MSBs of the 14-bit data-word are decoded to drive 15 switches,

E1 to E15. Each of these switches connects one of 15 matched

resistors to either AGND or VREF. The remaining 10 bits of

the data-word drive switches S0 to S9 of a 10-bit voltage mode

R-2R ladder network.

2ꢀs/DIV

Figure 27. Digital Feedthrough

V

= 2.5V

= 5V

REF

V

DD

T

= 25ꢁC

R

100

90

A

V

OUT

CS (5V/DIV)

2R

S1

2R

S9

2R

E1

2R

E2

2R

S0

E15

V

(0.1V/DIV)

OUT

10

0%

10-BIT R-2R LADDER

FOUR MSBS DECODED INTO

15 EQUAL SEGMENTS

2ꢀs/DIV

Figure 31. DAC Architecture

Figure 28. Digital-to-Analog Glitch Impulse

With this type of DAC configuration, the output impedance is

independent of code, while the input impedance seen by the

reference is heavily code dependent. The output voltage is

dependent on the reference voltage as shown in the following

equation.

2ꢀs/DIV

100

90

CS

(5V/DIV)

10pF

V_REF¥ D

V_OUT

=

50pF

2^N

200pF

100pF

where D is the decimal data-word loaded to the DAC register

and N is the resolution of the DAC. For a reference of 2.5 V,

the equation simplifies to the following.

V

= 2.5V

= 5V

= 25ꢁC

REF

10

V

T

DD

0%

A

2.5 ¥ D

V_OUT

=

V

OUT

16,384

(0.5V/DIV)

giving a V_OUTof 1.25 V with midscale loaded, and 2.5 V with

full scale loaded to the DAC.

Figure 29. Large Signal Settling Time

The LSB size is V_REF/16,384.

–36–

REV. A

AD15700

Serial Interface

Output Amplifier Selection

The DAC is controlled by a versatile 3-wire serial interface that

operates at clock rates up to 25 MHz and is compatible with

SPI, QSPI, MICROWIRE, and DSP interface standards. The

timing diagram can be seen in Figure 3. Input data is framed by

the chip select input, CS_DAC. After a high to low transition on

CS_DAC, data is shifted synchronously and latched into the

input register on the rising edge of the serial clock, SCLK. Data

is loaded MSB first in 14-bit words. After 14 data bits have been

loaded into the serial input register, a low to high transition on

CS_DAC transfers the contents of the shift register to the DAC.

Data can only be loaded to the part while CS_DAC is low.

In a single-supply application, selection of a suitable op amp

may be more difficult as the output swing of the amplifier does

not usually include the negative rail, in this case AGND. This

can result in some degradation of the specified performance

unless the application does not use codes near zero.

The selected op amp needs to have very low offset voltage (the

DAC LSB is 152 mV with a 2.5 V reference) to eliminate the

need for output offset trims. Input bias current should also be

very low as the bias current multiplied by the DAC output

impedance (approximately 6 kW) will add to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code independent, but in order to minimize gain

errors, the input impedance of the output amplifier should be as

high as possible. The amplifier should also have a 3 dB band-

width of 1 MHz or greater. The amplifier adds another time

constant to the system, thus increasing the settling time of the

output. A higher 3 dB amplifier bandwidth results in a faster

effective settling time of the combined DAC and amplifier.

Unipolar Output Operation

The DAC is capable of driving unbuffered loads of 60 kW.

Unbuffered operation results in low supply current, typically

300 mA, and a low offset error. The DAC provides a unipolar

output swing ranging from 0 V to VREF. Figure 32 shows a

typical unipolar output voltage circuit. The code table for this

mode of operation is shown in Table IV.

5V

2.5V

10ꢀF

Force Sense Buffer Amplifier Selection

0.1ꢀF

These amplifiers can be single-supply or dual-supply, low noise

amplifiers. A low output impedance at high frequencies is pre-

ferred to be able to handle dynamic currents of up to ±20 mA.

SERIAL

INTERFACE

V

REF

DD

CS

DAC

Reference and Ground

DIN

SCLK

UNIPOLAR

OUTPUT

OUT

As the input impedance is code dependent, the reference pin

should be driven from a low impedance source. The DAC oper-

ates with a voltage reference ranging from 2 V to V_DD. Although

DAC’s full-scale output voltage is determined by the reference,

references below 2 V will result in reduced accuracy. Table IV

outlines the analog output voltage for particular digital codes.

OP AMP

AGND

DGND

Figure 32. Unipolar Output

Table IV. Unipolar Code Table

Power-On Reset

The DAC has a power-on reset function to ensure the output is

at a known state upon power-up. On power-up, the DAC register

contains all zeros, until data is loaded from the serial register.

However, the serial register is not cleared on power-up, so its

contents are undefined. When loading data initially to the DAC,

14 bits or more should be loaded to prevent erroneous data

appearing on the output. If more than 14 bits are loaded, only the

last 14 are kept, and if fewer than 14 are loaded, bits will remain

from the previous word. If the DAC needs to be interfaced with

data shorter than 14 bits, the data should be padded with zeros

at the LSBs.

DAC Latch Contents

MSB LSB

11 1111 1111 1111

10 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0000

Analog Output

VREF X (16383/16384)

VREF X (8192/16384) = 1/2 VREF

VREF X (1/16384)

0 V

Assuming a perfect reference, the worst-case output voltage may

be calculated from the following equation.

D

2¹⁴

V_OUT–UNI

=

¥ V

(

+V_GE+V

+ INL

ZSE

Power Supply and Reference Bypassing

)

REF

For accurate high resolution performance, it is recommended

that the reference and supply pins be bypassed with a 10 nF

tantalum capacitor in parallel with a 0.1 nF ceramic capacitor.

where:

_{OUT –UNI}= Unipolar Mode Worst-Case Output

D = Decimal Code Loaded to DAC

V

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the DAC is via a serial bus that

uses standard protocol compatible with DSP processors and

microcontrollers. The communications channel requires a

3-wire interface consisting of a clock signal, a data signal, and a

synchronization signal. The DAC requires a 14-bit data-word

with data valid on the rising edge of SCLK. The DAC update

may be done automatically when all the data is clocked in.

V

_REF= Reference Voltage Applied to Part

_GE= Gain Error in Volts

_ZSE= Zero Scale Error in Volts

INL = Integral Nonlinearity in Volts

REV. A

–37–

AD15700

ADSP-2101/ADSP-2103 to DAC Interface

P3.3

RxD

TxD

CS_DAC

DIN

Figure 33 shows a serial interface between the DAC and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set to operate in the SPORT (Serial Port) Transmit Alternate

Framing Mode. The ADSP-2101/ADSP-2103 is programmed

through the SPORT Control Register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. The first two bits are DON’T CARE as the DAC

will keep the last 14 bits. Transmission is initiated by writing a

word to the Tx Register after the SPORT has been enabled.

Because of the edge-triggered difference, an inverter is required at

the SCLKs between the DSP and the DAC.

80C51/

80L51*

DAC

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. 80C51/80L51 to DAC Interface

The 80C51/80L51 provides the LSB first, while the DAC

expects the MSB of the 14-bit word first. Care should be taken

to ensure the transmit routine takes this into account. Usually it

can be done through software by shifting out and accumulating

the bits in the correct order before inputting to the DAC. Also,

80C51 outputs 2-byte word/16-bit data. Thus the first two bits,

after rearrangement, should be DON’T CARE as they will be

dropped from the DAC’s 14-bit word.

TFS

DT

CS_DAC

DIN

ADSP-2101/

ADSP-2103*

DAC

SCLK

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmits its data in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. As the DAC requires a

14-bit word, P3.3 (or any one of the other programmable bits)

is the CS_DAC input signal to the DAC, so P3.3 should be

brought low at the beginning of the 16-bit write cycle 2 ϫ 8-bit

words and held low until the 16-bit 2 ϫ 8 cycle is completed.

After that, P3.3 is brought high again and the new data loads to

the DAC. Again, the first two bits, after rearranging, should be

DON’T CARE.

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 33. ADSP-2101/ADSP-2103 to DAC Interface

68HC11/68L11 to DAC Interface

Figure 34 shows a serial interface between the DAC and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the DAC, while the MOSI output drives the

serial data lines SDIN. CS signal is driven from one of the port lines.

The 68HC11/68L11 is configured for master mode; MSTR = 1,

CPOL = 0, and CPHA = 0. Data appearing on the MOSI

output is valid on the rising edge of SCK.

PC6

APPLICATIONS

Optocoupler Interface

PC7

MOSI

SCK

CS_DAC

DIN

68HC11/

68L11*

DAC

The digital inputs of the DAC are Schmitt-triggered, so they

can accept slow transitions on the digital input lines. This makes

these parts ideal for industrial applications where it may be

necessary for the DAC to be isolated from the controller via

optocouplers. Figure 37 illustrates such an interface.

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 34. 68HC11/68L11 to DAC Interface

MICROWIRE to DAC Interface

Figure 35 shows an interface between the DAC and any

MICROWIRE compatible device. Serial data is shifted out on

the falling edge of the serial clock and into the DAC on the

rising edge of the serial clock. No glue logic is required as the

DAC clocks data into the input shift register on the rising edge.

5V

REGULATOR

10nF

0.1nF

POWER

V

DD

10kꢂ

V

DD

CS_DAC

SCLK

MICROWIRE*

DAC

SO

SCLK

DIN

SCLK

DAC

V

DD

*ADDITIONAL PINS OMITTED FOR CLARITY

10kꢂ

Figure 35. MICROWIRE to DAC Interface

80C51/80L51 to DAC Interface

V

CS_DAC

CS

OUT

A serial interface between the DAC and the 80C51/80L51

microcontroller is shown in Figure 36. TxD of the microcontroller

drives the SCLK of the DAC, while RxD drives the serial data line

of the DAC. P3.3 is a bit programmable pin on the serial port

that is used to drive CS_DAC.

V

DD

10kꢂ

DIN

GND

Figure 37. DAC in an Optocoupler Interface

–38–

REV. A

AD15700

Decoding Multiple DACs

AMPLIFIER THEORY OF OPERATION

The CS_DAC pin of the DAC can be used to select one of a

number of DACs. All devices receive the same serial clock and

serial data, but only one device will receive the CS_DAC signal

at any one time. The DAC addressed will be determined by the

decoder. There will be some digital feedthrough from the digital

input lines. Using a burst clock will minimize the effects of digital

feedthrough on the analog signal channels. Figure 38 shows a

typical circuit.

The amplifiers are single and dual versions of high speed, low

power voltage feedback amplifiers featuring an innovative archi-

tecture that maximizes the dynamic range capability on the inputs

and outputs. Linear input common-mode range exceeds either

supply voltage by 200 mV, and the amplifiers show no phase

reversal up to 500 mV beyond supply. The output swings to

within 20 mV of either supply when driving a light load; 300 mV

when driving up to 5 mA.

The amplifier provides an impressive 80 MHz bandwidth when

used as a follower and 30 V/ms slew rate at only 800 mA supply

current. Careful design allows the amplifier to operate with a

supply voltage as low as 2.7 V.

DAC

SCLK

CS_DAC

V

OUT

DIN

V

DD

SCLK

Input Stage Operation

A simplified schematic of the input stage appears in Figure 39.

For common-mode voltages up to 1.1 V within the positive supply,

(0 V to 3.9 V on a single 5 V supply) tail current I2 flows through

the PNP differential pair, Q13 and Q17. Q5 is cut off; no bias

current is routed to the parallel NPN differential pair Q2 and Q3.

As the common-mode voltage is driven within 1.1 V of the positive

supply, Q5 turns on and routes the tail current away from the PNP

pair and to the NPN pair. During this transition region, the

amplifier’s input current will change magnitude and direction.

Reusing the same tail current ensures that the input stage has

the same transconductance (which determines the amplifier’s

gain and bandwidth) in both regions of operation.

DAC

ENABLE

EN

CS_DAC

CODED

ADDRESS

V

DECODER

DGND

OUT

DIN

SCLK

DAC

CS_DAC

V

OUT

DIN

SCLK

DAC

Switching to the NPN pair as the common-mode voltage is

driven beyond 1 V within the positive supply allows the amplifier

to provide useful operation for signals at either end of the supply

voltage range and eliminates the possibility of phase reversal for

input signals up to 500 mV beyond either power supply. Offset

voltage will also change to reflect the offset of the input pair in

control. The transition region is small, on the order of 180 mV.

These sudden changes in the dc parameters of the input stage

can produce glitches that will adversely affect distortion.

CS_DAC

V

OUT

DIN

SCLK

Figure 38. Addressing Multiple DACs

V

CC

R1

2kꢂ

R2

2kꢂ

I2

90mA

I3

25mA

Q9

?

1.1V

R5

50kꢂ

V

Q3

R8

Q2

R9

Q6

Q10

IN

1

R6

R7

Q7

850ꢂ 850ꢂ

Q8

Q5

4

850ꢂ 850ꢂ

V

Q13

Q17

I4

IP

OUTPUT STAGE,

COMMON-MODE

FEEDBACK

?

25mA

Q11

Q14

1

Q15

Q16

R3

2kꢂ

R4

2kꢂ

I1

5mA

?

Q18

Q4

V

EE

Figure 39. Simplified Schematic of Input Stage

REV. A

–39–

AD15700

Overdriving the Input Stage

Used as a unity gain follower, the amplifier output will exhibit

more distortion in the peak output voltage region around

V_CC–0.7 V. This unusual distortion characteristic is caused by

the input stage architecture and is discussed in detail in the

section covering Input Stage Operation.

Sustained input differential voltages greater than 3.4 V should be

avoided as the input transistors may be damaged. Input clamp

diodes are recommended if the possibility of this condition exists.

The voltages at the collectors of the input pairs are set to 200 mV

from the power supply rails. This allows the amplifier to remain

in linear operation for input voltages up to 500 mV beyond the

supply voltages. Driving the input common-mode voltage beyond

that point will forward bias the collector junction of the input

transistor, resulting in phase reversal. Sustaining this condition

for any length of time should be avoided as it is easy to exceed

the maximum allowed input differential voltage when the amplifier

is in phase reversal.

Output Overdrive Recovery

Output overdrive of an amplifier occurs when the amplifier

attempts to drive the output voltage to a level outside its normal

range. After the overdrive condition is removed, the amplifier must

recover to normal operation in a reasonable amount of time. As

shown in Figure 41, the amplifier recovers within 100 ns from

negative overdrive and within 80 ns from positive overdrive.

R

F

G

R

= R = 2kꢂ

G

F

Output Stage, Open-Loop Gain, and Distortion Versus

Clearance from Power Supply

The amplifier features a rail-to-rail output stage. The output

transistors operate as common emitter amplifiers, providing the

output drive current as well as a large portion of the amplifier’s

open-loop gain.

V

OUT

IN

R

T

L

50V

I1

25mA

I2

25mA

Q42

Q51

Q47

V

R

= ꢃ2.5V

= 1kꢂ TO GND

S

IN

L

DIFFERENTIAL

DRIVE

Q37 Q38

FROM

1V

100ns

C9

1.5pF

Q68

INPUT STAGE

R29

300ꢂ

Q20

Figure 41. Overdrive Recovery

Q27

Q21

V

OUT

C5

1.5pF

Driving Capacitive Loads

Q43

Q48

Capacitive loads interact with an amplifier’s output impedance

to create an extra delay in the feedback path. This reduces circuit

stability and can cause unwanted ringing and oscillation. A given

value of capacitance causes much less ringing when the amplifier

is used with a higher noise gain.

Q49

I4

25mA

I5

25mA

Q44

Q50

The capacitive load drive of the amplifier can be increased by

adding a low valued resistor in series with the capacitive load.

Introducing a series resistor tends to isolate the capacitive load

from the feedback loop, thereby diminishing its influence.

Figure 42 shows the effect of a series resistor on capacitive drive

for varying voltage gains. As the closed-loop gain is increased, the

larger phase margin allows for larger capacitive loads with less

overshoot. Adding a series resistor at lower closed-loop gains

accomplishes the same effect. For large capacitive loads, the

frequency response of the amplifier will be dominated by the

roll-off of the series resistor and capacitive load.

Figure 40. Output Stage Simplified Schematic

The output voltage limit depends on how much current the

output transistors are required to source or sink. For applica-

tions with very low drive requirements (a unity gain follower

driving another amplifier input, for instance), the amplifier

typically swings within 20 mV of either voltage supply. As the

required current load increases, the saturation output voltage

will increase linearly as I_LOADϫ R_C, where I_LOADis the required

load current and R_Cis the output transistor collector resistance.

For the amplifier, the collector resistances for both output tran-

sistors are typically 25 W. As the current load exceeds the rated

output current of 15 mA, the amount of base drive current

required to drive the output transistor into saturation will reach

its limit, and the amplifier’s output swing will rapidly decrease.

u

1000

R

= 5ꢂ

V

= 5

S

200mV STEP

WITH 30% OVERSHOOT

R

= 0ꢂ

S

The open-loop gain of the amplifier decreases approximately

linearly with load resistance and also depends on the output

voltage. Open-loop gain stays constant to within 250 mV of the

positive power supply, 150 mV of the negative power supply

and then decreases as the output transistors are driven further

into saturation.

100

R

= 20V

S

R

= 20ꢂ

S

R

F

G

10

R

S

V

OUT

The distortion performance of the amplifiers differs from

conventional amplifiers. Typically an amplifier’s distortion

performance degrades as the output voltage amplitude increases.

R

S

= 0ꢂ, 5ꢂ

C

L

1

0

1

2

3

4

5

CLOSED-LOOP GAIN –V/V

Figure 42. Capacitive Load Drive vs. Closed-Loop Gain

REV. A

–40–

AD15700

High Performance Single-Supply Line Driver

Figure 43 shows the amplifier configured as a single-supply

gain-of-two line driver. With the output driving a back terminated

50 W line, the overall gain from V_INto V_OUTis unity. In addition

to minimizing reflections, the 50 W back termination resistor pro-

tects the transistor from damage if the cable is short circuited.

The emitter follower, which is inside the feedback loop, ensures

that the output voltage from the amplifier stays about 700 mV

above ground. Using this circuit, very low distortion is attain-

able even when the output signal swings to within 50 mV of

ground. The circuit was tested at 500 kHz and 2 MHz. Figures 44

and 45 show the output signal swing and frequency spectrum at

500 kHz. At this frequency, the output signal (at V_OUT), which

has a peak-to-peak swing of 1.95 V (50 mV to 2 V), has a THD

of –68 dB (SFDR = –77 dB).

Even though the amplifier swings close to both rails, the amplifier

has optimum distortion performance when the signal has a common-

mode level halfway between the supplies and when there is about

500 mV of headroom to each rail. If low distortion is required in

single-supply applications for signals that swing close to ground,

an emitter follower circuit can be used at the amplifier output.

5V

10ꢀF

0.1ꢀF

V

IN

Figures 46 and 47 show the output signal swing and frequency

spectrum at 2 MHz. As expected, there is some degradation in

signal quality at the higher frequency. When the output signal has

a peak-to-peak swing of 1.45 V (swinging from 50 mV to 1.5 V),

the THD is –55 dB (SFDR = –60 dB). This circuit could also be

used to drive the analog input of a single-supply high speed ADC

whose input voltage range is referenced to ground (e.g., 0 V to 2 V

or 0 V to 4 V). In this case, a back termination resistor is not

necessary (assuming a short physical distance from transistor to

ADC), so the emitter of the external transistor would be connected

directly to the ADC input. The available output voltage swing

of the circuit would, therefore, be doubled.

49.9ꢂ

2N3904

V

2.49ꢂ

49.9ꢂ

200ꢂ

OUT

49.9ꢂ

Figure 43. Low Distortion Line Driver for Single-

Supply Ground Referenced Signals

1.5V

100

90

100

90

2V

10

0%

50mV

0.5V

1µs

0.2V

200ns

50mV

Figure 44. Output Signal Swing of Low Distortion

Line Driver at 500 kHz

Figure 46. Output Signal Swing of Low Distortion

Line Driver at 2 MHz

+9dBm

+7dBm

START 0Hz

STOP 5MHz

START 0Hz

STOP 20MHz

Figure 45. THD of Low Distortion Line Driver at 500 kHz

Figure 47. THD of Low Distortion Line Driver at 2 MHz

REV. A

–41–

AD15700

AD15700 PINOUT

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

AGND

DAC

A

B

COMMON

VREF

COMMON

VOUT

RPAD1

RB1

–IN1

COMMON

+VS1

COMMON

A

B

COMMON

RA1

–VS1

VOUT1

CS_DAC

AGND

DAC

AGND

DAC

VDD

DAC

C

D

COMMON

+IN1

RC1

COMMON

RESET

C

D

COMMON

DGND

DAC

SCLK

E

DIN

COMMON

CNVST

COMMON

RD

D15

D13

D14

D12

E

F

G

H

COMMON

–IN2

COMMON

+VS2

–VS2

COMMON

REF

COMMON

TEST1

COMMON

BUSY

F

D11

RDERROR

D10

SYNC

G

AGND

ADC

DGND

ADC

D9

SCLK

D8

SDOUT

COMMON

+IN2

COMMON

–VS2

COMMON

VOUT2

REFGND

INA

COMMON

INGND

TEST0

H

J

AGND

ADC

AGND

ADC

COMMON

OGND

OVDD

DVDD

J

D6

INVSCLK

D7

RDC/SDN

COMMON

INB

COMMON

PD

CS_ADC

K

L

K

L

BYTE

SWAP

D3

DIVSCLK1

D5

INVSYNC

RC2

COMMON

RA2

INC

COMMON

OB/2C

IMPULSE

D1

D2

D4

EXT/INT

AGND

ADC

M

COMMON

1

COMMON

2

RPAD2

3

RB2

4

IND

5

AVDD

6

WARP

7

SER/PAR

D0

9

DIVSCLK0

8

10

11

12

–42–

REV. A

AD15700

OUTLINE DIMENSIONS

144-Lead Chip Scale Ball Grid Array [CSPBGA]

(BC-144)

Dimensions shown in millimeters

A1 CORNER

INDEX AREA

10.00 BSC SQ

12 11 10

9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

A1

TOP VIEW

G

H

J

K

L

M

0.80 BSC

8.80 BSC

DETAIL A

1.70 MAX

DETAIL A

0.85 MIN

0.12 MAX

0.25 MIN

0.55

0.50

0.45

SEATING

PLANE

COPLANARITY

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-205AC

NOTES

1. THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.15

OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES

2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL

POSITION RELATIVE TO THE BALL POPULATION

REV. A

–43–

AD15700

Revision History

Location

Page

2/03—Data Sheet changed from REV. 0 to REV. A.

Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to AMPLIFIER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Edit to ADC PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Edit to Figure 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

–44–

REV. A


型号：	AD15700/PCB
厂家：	ADI
描述：	1 MSPS 16-/14-Bit Analog I/O Port 1 MSPS 16位/ 14位模拟I / O端口
文件：	总44页 (文件大小：1007K)
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AD15700/PCB [ADI]

相关型号：

AD15700BCA

AD1580

AD1580A

AD1580ART

AD1580ART-R2

AD1580ART-R2

AD1580ART-REEL

AD1580ART-REEL1

AD1580ART-REEL7

AD1580ART-REEL7

AD1580ARTZ-REEL

AD1580ARTZ-REEL7