5962-9961003HXA [ADI]
Dual Channel, 12-Bit, 105 MSPS IF Sampling A/D Converter With Analog Input Signal Conditioning;
| 型号： | 5962-9961003HXA |
| 厂家： | 
ADI |
| 描述： | Dual Channel, 12-Bit, 105 MSPS IF Sampling A/D Converter With Analog Input Signal Conditioning 转换器 |
| 文件： | 总20页 (文件大小：1493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Channel, 12-Bit 105 MSPS IF Sampling
A/D Converter with Analog Input
Signal Conditioning
a
AD10200
FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
0.850 W per Channel
an innovative architecture to achieve 12-bit, 105 MSPS perfor-
mance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.
The AD10200 operates with 5.0 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–50°C to +125°C).
Industrial and Military Grade
APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 105 MSPS.
2. Input signal conditioning with full power bandwidth to
250 MHz.
PRODUCT DESCRIPTION
The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
3. Fully tested/characterized performance at 121 MHz AIN.
4. Optimized for IF sampling.
FUNCTIONAL BLOCK DIAGRAM
A
A2
A
B2
IN
7
IN
63
34
50
D00A
(LSB)
D00B
(LSB)
D01A 33
49 D01B
T1A
T1B
32
48
D02A
D02B
D03A 31
47 D03B
46 D04B
45 D05B
50⍀
50⍀
D04A
30
T/H
T/H
AD10200
D05A 29
28
42
D06A
D06B
D07A 25
41 D07B
40 D08B
ADC
ADC
24
D08A
12
12
12
12
D09A 23
D10A 22
D09B
D10B
39
38
OUTPUT RESISTORS
OUTPUT RESISTORS
21
D11A
(MSB)
37 D11B
(MSB)
TIMING
REF
REF
56
TIMING
18
17
3
53
54
ENCODEA ENCODEA
REF_A_OUT
REF_B_OUT
ENCODEB ENCODEB
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
©Analog Devices, Inc., 2001–2016
AD10200* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
SOFTWARE AND SYSTEMS REQUIREMENTS
• Military Part Cross-Reference Guide
• Military Products by Function
EVALUATION KITS
• AD10200 Evaluation Board
• Military Products by GENERIC Part Number
• SMD to Generic Cross Reference
DOCUMENTATION
Application Notes
TOOLS AND SIMULATIONS
• Visual Analog
• AN-280: Mixed Signal Circuit Technologies
• AN-282: Fundamentals of Sampled Data Systems
REFERENCE MATERIALS
Technical Articles
• AN-297: Test Video A/D Converters Under Dynamic
Conditions
• Class T Satellite Products
• AN-302: Exploit Digital Advantages in an SSB Receiver
• Correlating High-Speed ADC Performance to Multicarrier
• AN-342: Analog Signal-Handling for High Speed and
3G Requirements
Accuracy
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System
Performance
• Multi-Channel Analog-to-Digital Converter Module
Integration
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
DESIGN RESOURCES
• AD10200 Material Declaration
• PCN-PDN Information
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• Quality And Reliability
• Symbols and Footprints
• AN-835: Understanding High Speed ADC Testing and
Evaluation
DISCUSSIONS
View all AD10200 EngineerZone Discussions.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
SAMPLE AND BUY
Visit the product page to see pricing options.
Data Sheet
• AD10200: Dual Channel, 12-Bit 105 MSPS IF Sampling A/D
Converter with Analog Input Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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AD10200–SPECIFICATIONS1
(VDD = 3.3 V, VCC = 5.0 V; ENCODE = 105 MSPS, unless otherwise noted)
Test
MIL
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error2
Full
Full
Full
Full
Full
IV
IV
I
I
I
12
12
1, 2, 3
1, 2, 3
1, 2, 3
–0.99
–3
0.5
0.75
Guaranteed
1
+0.99
+3
LSB
LSB
–9
–12
+9
+12
% FS
LSB
Output Offset
ANALOG INPUT
Input Voltage Range
Input Impedance
25°C
25°C
Full
Full
Full
V
V
IV
IV
IV
2.048
50
1.1:1
250
V p-p
Ω
Ratio
MHz
MHz
Input VSWR3
12
12
12
1.25:1
2.6
Analog Input Bandwidth, High
Analog Input Bandwidth, Low
200
1
ANALOG REFERENCE
Output Voltage
Load Current
Full
25°C
Full
I
V
V
1, 2, 3
2.4
2.5
5
50
V
mA
ppm/°C
Tempco
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Duty Cycle
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
I
4, 5, 6
12
12
105
45
MSPS
MSPS
%
ns
ps rms
ns
ns
ns
ns
IV
IV
V
10
55
50
Aperture Delay (tA)
1.0
0.25
5.3
5.5
3.5
3.3
Aperture Uncertainty (Jitter)
V
Output Valid Time (tV)4
Output Propagation Delay (PD
IV
IV
V
12
12
12
12
3.0
4.5
4
)
8.0
Output Rise Time (tR)
Output Fall Time (tF)
V
DIGITAL INPUTS
Encode Input Common Mode
Differential Input (Enc, Enc)
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
V
12
12
12
12
12
1.2
0.4
2.0
1.6
2.0
5.0
V
V
V
V
kΩ
pF
0.8
8
3
5
4.5
Input Capacitance
DIGITAL OUTPUTS
Logic “1” Voltage4
Logic “0” Voltage4
Output Coding
Full
Full
VI
VI
1, 2, 3
1, 2, 3
3.1
3.3
0
V
V
0.2
Two’s Complement
POWER SUPPLY5
Power Dissipation6
Power Supply Rejection Ratio
I (DVDD) Current
Full
Full
Full
Full
I
IV
I
I
1, 2, 3
12
1, 2, 3
1, 2, 3
1800
0.5
25
2200
5
40
mW
mV/V
mA
I (AVCC) Current
340
410
mA
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)7
(Without Harmonics)
f
f
f
f
IN = 10 MHz
IN = 41 MHz
IN = 71 MHz
IN = 121 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
67
66
66.5
65
66.4
64
65
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
4
5, 6
4
5, 6
4
64
62
62.5
61.5
61
5, 6
61
64
–2–
REV. B
AD10200
Test
MIL
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
(Continued)
Signal-to-Noise Ratio (SINAD)8
(With Harmonics)
f
f
f
f
IN = 10 MHz
IN = 41 MHz
IN = 71 MHz
IN = 121 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
66
63
65.5
63
63.5
60
58.5
55
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
4
5, 6
4
5, 6
4
5, 6
63
60.5
61
57
56
53
Spurious Free Dynamic Range9
fIN = 10 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
81
70
81
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
f
f
f
IN = 41 MHz
IN = 71 MHz
IN = 121 MHz
4
5, 6
4
5, 6
4
5, 6
73
67.5
67
60
61
74
65
58
55.5
Two-Tone Intermodulation
Distortion10 (IMD)
f
f
f
IN = 10 MHz; fIN = 12 MHz
IN = 71 MHz; fIN = 72 MHz
IN = 121 MHz; fIN = 122 MHz
25°C
Full
25°C
Full
25°C
Full
V
V
V
V
I
86
81
70
65
62
57
dBc
dBc
dBc
dBc
dBc
dBc
4
5, 6
55.5
53
II
Channel-to-Channel Isolation11
fIN = 121 MHz
Full
IV
12
80
85
dB
NOTES
1All ac specifications tested by driving ENCODE and ENCODE differentially.
2Gain Error measured at 2.5 MHz.
3Input VSWR guaranteed 10 MHz to 200 MHz.
4tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of 40 mA.
5Supply voltages should remain stable within 5% for normal operation.
6Power dissipation measured with encode at rated speed and 0 dBm analog input.
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR
is reported in dBFS, related back to converter full scale.
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD
is reported in dBFS, related back to converter full scale.
9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz
100 kHz, f2 = x MHz 100 kHz.
11Channel-to-Channel isolation tested with A Channel/50 Ω terminated (AINA2) grounded and a full-scale signal applied to B Channel (AINB2).
Specifications subject to change without notice.
REV. B
–3–
AD10200
ABSOLUTE MAXIMUM RATINGS1, 2
Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 Vp-p(18 dBm)
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –50°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
Code
AIN (V)
Digital Output
+2047
•
•
0
–1
•
•
+1.024
•
•
0
–0.00049
•
•
0111 1111 1111
•
•
0000 0000 0000
1111 1111 1111
•
•
–2048
–1.024
1000 0000 0000
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2Typical thermal impedances for “Z” package:
θJC = 2.22°C/W; θJA = 24.3°C/W.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specific temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Revision History
Location
Page
8/2016 Data Sheet changed from REV. A to REV. B.
Change Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 4
Moved Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Updated Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Sheet changed from REV. 0 to REV. A.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Edit to ENCODE Inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edit to Figure 9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. B
–4–
AD10200
PIN CONFIGURATION
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIN 1
AGNDA
AGNDA
DNC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AGNDB
AGNDB
DNC
IDENTIFIER
AGNDA
DNC
AV
CC
DNC
REF_B_OUT
AGNDB
AGNDA
ENCODEB
ENCODEB
AGNDB
ENCODEA
ENCODEA
AGNDA
AD10200
TOP VIEW
(Not to Scale)
DV
CC
D0B (LSB)
D1B
DV
CC
(MSB) D11A
D10A
D2B
D9A
D3B
D8A
D4B
D7A
D5B
DGNDA
DGNDB
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Function
Pin No.
Mnemonic
1
SHIELD
AGNDA
Internal Ground Shield between Channels
A Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
2, 5, 9–11, 13, 16, 19, 35
3
VREF_A_OUT
NC
A Channel Internal Voltage Reference
No Connection
6, 62
7
AINA2
Analog Input for A Side ADC
4, 8, 12, 15, 57, 58, 64, 67
DNC
Do Not Connect
14, 66
17
18
20
AVCC
Analog Positive Supply Voltage (Nominally 5.0 V)
Complement of Encode
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (Nominally 3.3 V)
Digital Outputs for ADC A. D0 (LSB)
ENCODEA
ENCODEA
DVCC
D11A–D7A,
D6A–D0A
DGNDA
AGNDB
21–25, 28–34
26, 27
36, 52, 55, 59–61, 65, 68
A Channel Digital Ground
B Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
37–42, 45–50
D11B–D6B,
D5B–D0B
DGNDB
Digital Outputs for ADC B. D0 (LSB)
43, 44
51
53
54
56
B Channel Digital Ground
DVCC
Digital Positive Supply Voltage (Nominally 3.3 V)
Data conversion initiated on rising edge of ENCODE input.
Complement of Encode
B Channel Internal Voltage Reference
Analog Input for B Side ADC
ENCODEB
ENCODEB
VREF_B_OUT
AINB2
63
REV. B
–5–
AD10200
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
Aperture Delay
The ratio of a change in output offset voltage to a change in
power supply voltage.
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set a 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. [May be reported in
dBc (i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale)].
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Signal-to-Noise Ratio (without Harmonics)
Encode Pulsewidth/Duty Cycle
The ratio of the rms signal amplitude (set a I dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc. [May be
reported in dBc (i.e., degrades as signal levels is lowered) or in
dBFS (always related back to converter full scale).]
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
Spurious-Free Dynamic Range
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. [May be reported in dBc
(i.e., degrades as signal levels is lowered) or in dBFS (always
related back to converter full scale).]
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Transient Response
The time required for the converter to achieve 0.02% accu-
racy when a one-half full-scale step function is applied to the
analog input.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more that 3 dB below the guaranteed limit.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
Voltage Standing-Wave Ratio (VSWR)
The ratio of the amplitude of the elective field at a voltage maxi-
mum to that at an adjacent voltage minimum.
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
–6–
REV. B
Typical Performance Characteristics–AD10200
0
؊10
0
ENCODE = 105 MSPS
= 41MHz (–1dBFS)
SNR = 66.06dBFS
SFDR = 80.59dBc
ENCODE = 105 MSPS
= 10MHz (–1dBFS)
SNR = 66.84dBFS
SFDR = 82.28dBc
؊10
؊20
A
A
IN
IN
؊20
؊30
؊30
؊40
؊40
؊50
؊50
؊60
؊60
؊70
؊70
؊80
؊80
؊90
؊90
؊100
؊110
؊120
؊130
؊100
؊110
؊120
؊130
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
FREQUENCY – MHz
TPC 1. Single Tone @ 10 MHz
TPC 4. Single Tone @ 41 MHz
0
؊10
0
؊10
ENCODE = 105 MSPS
= 121MHz (–1dBFS)
SNR = 64.92dBFS
SFDR = 64.73dBc
ENCODE = 105 MSPS
IN
SNR = 66.04dBFS
SFDR = 79.71dBc
A
A
= 71MHz (–1dBFS)
IN
؊20
؊20
؊30
؊30
؊40
؊40
؊50
؊50
؊60
؊60
؊70
؊70
؊80
؊80
؊90
؊90
؊100
؊110
؊120
؊130
؊100
؊110
؊120
؊130
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Single Tone @ 71 MHz
TPC 5. Single Tone @ 121 MHz
0
؊10
0
؊10
ENCODE = 105 MSPS
= 121MHz (–6dBFS)
ENCODE = 105 MSPS
A = 201MHz (–10dBFS)
IN
A
IN
SNR = 66.9dBFS
SFDR = 65.57dBc
SNR = 66.84dBFS
SFDR = 64.57dBc
؊20
؊20
؊30
؊30
؊40
؊40
؊50
؊50
؊60
؊60
؊70
؊70
؊80
؊80
؊90
؊90
؊100
؊110
؊120
؊130
؊100
؊110
؊120
؊130
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
FREQUENCY – MHz
TPC 6. Single Tone @ 201 MHz
TPC 3. Single Tone @ 121 MHz
–7–
REV. B
AD10200
0
0
؊10
ENCODE = 105 MSPS
= 71MHz & 72MHz (–7dBFS)
SFDR = 74.8dBc
ENCODE = 105 MSPS
= 37MHz & 38MHz (–10dBFS)
SFDR = 79.84dBc
؊10
A
A
IN
IN
؊20
؊30
؊20
؊30
؊40
؊40
؊50
؊50
؊60
؊60
؊70
؊70
؊80
؊80
؊90
؊90
؊100
؊110
؊120
؊130
؊100
؊110
؊120
؊130
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
FREQUENCY – MHz
TPC 7. Two-Tone @ 37 MHz/38 MHz
TPC 10. Two-Tone @ 71 MHz/72 MHz
3.0
2.5
0
؊10
ENCODE = 105 MSPS
DNL MAX = 0.486 Codes
DNL MIN = 0.431 Codes
ENCODE = 105 MSPS
IN
SFDR = 63.8dBc
A
= 120MHz & 121MHz (–7dBFS)
؊20
؊30
2.0
؊40
1.5
؊50
؊60
1.0
؊70
؊80
0.5
؊90
0.0
؊100
؊110
؊120
؊130
؊0.5
؊1.0
0
512
1024
1536
2048
2560 3072
3584
4096
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
TPC 11. Differential Nonlinearity
TPC 8. Two-Tone @ 120 MHz/121 MHz
3
2
0
ENCODE = 105 MSPS
3dB = 261MHz
ENCODE = 105 MSPS
INL MAX = 0.874 Codes
INL MIN = 0.895 Codes
؊
؊
؊
1
2
3
1
؊
؊
4
5
0
؊6
؊7
؊1
؊2
؊3
؊8
؊9
؊10
3.0 32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0
MHz
0
512
1024
1536
2048
2560 3072
3584
4096
TPC 12. Gain Flatness
TPC 9. Integral Nonlinearity
–8–
REV. B
AD10200
11
10MHz = 1.0149
50MHz = 1.085
100MHz = 1.130
150MHz = 1.092
10
9
8
7
6
5
4
3
2
1
10MHz = 50.22 + j.173
50MHz = 48.79 – j4.2
100MHz = 46.95 – j5.9
150MHz = 48.55 – j4.66
3.0 32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0
MHz
TPC 13. Input Impedance S11
TPC 14. Voltage Standing Wave Ratio (VSWR)
SAMPLE N
SAMPLE N+10
SAMPLE N+11
SAMPLE N–1
AIN
SAMPLE N+1
SAMPLE N+9
1/fS
ENCODE
ENCODE
tPD
tV
DATA NϷ11
DATA NϷ10
NϷ9
NϷ2
DATA NϷ1
DATA N
DATA N+1
D11ϷD0
Figure 1. Timing Diagram
V
CC
V
V
CC
CC
17k⍀
8k⍀
17k⍀
Q1
NPN
ENCODE
ENCODE
100⍀
100⍀
8k⍀
V
OUTPUT
REF
Figure 2. Equivalent Encode Input Circuit
Figure 4. Equivalent Voltage Reference Output Circuit
V
CC
V
CC
5k⍀
7k⍀
5k⍀
A
IN
50⍀
100⍀
DIGITAL
OUTPUT
7k⍀
Figure 3. Equivalent Digital Output Circuit
Figure 5. Equivalent Analog Input Circuit
–9–
REV. B
AD10200
APPLICATION NOTES
Theory of Operation
Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.
The AD10200 is a high-dynamic range dual 12-bit, 105 MHz
subrange pipeline converter that uses switched capacitor
architecture. The analog input section uses AINA2/AINB2 at
2.048 V p-p with an input impedance of 50 Ω. The analog input
includes an ac-coupled wide-band 1:1 transformer, which provides
high-dynamic range and SNR while maintaining VSWR and
gain flatness. The ADC includes a high-bandwidth linear track/
hold that gives excellent spurious performance up to and beyond
the Nyquist rate. The high-bandwidth track/hold has a low jitter
of 0.25 ps rms, leading to excellent SNR and SFDR performance.
AC-coupled differential PECL/ECL encode inputs are recom-
mended for optimum performance.
Digital Outputs
The digital outputs are TTL/CMOS-compatible and a separate
output power supply pin supports interfacing with 3.3 V logic.
Analog Input
The analog input is a single ended ac-coupled high performance
1:1 transformer with an input impedance of 50 Ω to 105 MHz.
The nominal full scale input is 2.048 V p-p.
Special care was taken in the design of the analog input section
of the AD10200 to prevent damage and corruption of data when
the input is overdriven.
USING THE AD10200
ENCODE Input
Voltage Reference
Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD10200, and the user is
advised to give commensurate thought to the clock source. The
ENCODE input are fully TTL/CMOS compatible. For opti-
mum performance, the AD10200 must be clocked differentially.
A stable and accurate 2.5 V voltage reference is designed into
the AD10200 (VREFOUT). An external voltage reference is
not required.
Timing
The AD10200 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (tPD
)
after the rising edge of the encode command (see Figure 1). The
length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD10200; these
transients can detract from the converter's dynamic performance.
Note that the ENCODE inputs cannot be driven directly from
PECL level signals (VIHD is 3.5 V max). PECL level signals can
easily be accommodated by ac coupling as shown in Figure 6.
Good performance is obtained using an MC10EL16 in the
circuit to drive the encode inputs.
The minimum guaranteed conversion rate of the AD10200 is
10 MSPS. At internal clock rates below 10 MSPS, dynamic
performance may degrade. Therefore, input clock rates below
10 MHz should be avoided.
0.1F
AD10200
ENCODE
GROUNDING AND DECOUPLING
Analog and Digital Grounding
PECL
GATE
ENCODE
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
0.1F
510⍀
510⍀
GND
Figure 6. AC Coupling to ENCODE Inputs
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and ENCODE
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
in differential mode are shown in Figure 7.
ENCODE Inputs
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
Differential Signal Amplitude (VID)
500 mV min,
750 mV nom
5.0 V max
These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.
High Differential Input Voltage (VIHD
)
Low Differential Input Voltage (VILD
)
0 V min
Common-Mode Input (VICN
)
1.25 V min, 1.6 V nom
It is important to design a layout that prevents noise from cou-
pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The PCB should have a ground plane covering
all unused portions of the component side of the board to pro-
vide a low impedance path and manage the power and ground
currents. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.
ENCODE
V
V
IHD
V
ID
ICM
ENCODE
V
ILD
V
IHS
ENCODE
0.1F
V
ILS
Figure 7. Differential Input Levels
–10–
REV. B
AD10200
LAYOUT INFORMATION
EVALUATION BOARD
The schematic of the evaluation board (Figure 8) represents
a typical implementation of the AD10200. The pinout of the
AD10200 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
The AD10200 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD10200
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10200. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high-slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD10200. The digital outputs of the
AD10200 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Figure 8. Evaluation Board Mechanical Layout
–11–
REV. B
AD10200
A G N D B
D G N D B
4 3
D G N D B
D 6 B
A G N D B
6 1
I N
B 1 A
D 6 B
6 2
6 3
4 2
I N
D 7 B
4 1
D 7 B
D 8 B
D 9 B
B 2 A
S D I N _ B
A G N D B
D 8 B
4 0
( N C )
6 4
A G N D A
6 5
D 9 B
3 9
5 V ؉ A B
5 V ؉ A B _
D 1 0 B
3 8
D 1 0 B
6 6
6 7
S C L K _ B
D 1 1 B ( M S B B D ) 1 1 B
( N C )
3 7
A G N D B
A G N D B
A G N D B
A G N D A
D 0 A
A G N D B
S H I E L D
6 8
3 6
L I D
1
A G N D A
3 5
A G N D A
A G N D A
D 0 A ( L S B A )
3 4
2
R E F _ A
S D I N _ A
A G N D A
D 1 A
D 2 A
D 1 A
3
3 3
D 2 A
3 2
D 3 A
( N C )
4
A G N D A
5
D 3 A
D 4 A
D 5 A
D 6 A
3 1
D 4 A
3 0
D 5 A
2 9
D 6 A
2 8
D G N D A
2 7
I N
A 1 A
6
7
5
I N
A 2 A
V F U _ A
A G N D A
A G N D A
D G N D A
9
Figure 9a. Evaluation Board
–12–
REV. B
AD10200
U14
5
NR
OUT
ADP3330
1
3
2
ERR
+5VAA_
IN
R42
SD
SD
AGNDA
+3.3VA
AGNDA
U2
100⍀
C13
6
4
0.47F
C1
C7
0.1F
1
8
0.1F
NC
D
VCC
Q
J5
ENCODE
SMA
2
3
4
7
6
5
ENCAB
ENCAB
DB
VBB
QB
VEE
J12
C8
0.1F
R1
50⍀
SMA
AGNDA
C2
0.1F
MC10EL16
R43
100⍀
AGNDA
R41
50⍀
R56
33k⍀
C6
0.1F
AGNDA
AGNDA
DGNDA
R3
100⍀
DGNDA
DGNDA
+3.3VA
C5
0.1F
U3
R58
33k⍀
AGNDA
1
2
3
4
8
7
6
5
NC
D
DB
VCC
Q
QB
U4
LATCHA
E23
1
2
3
4
8
+3.3VA
D0
VCC
Q0
Q1
7
6
5
D0B
D1B
D1
R4
100⍀
VBB
VEE
E19
BUFLATA
VEE
MC10EL16
DGNDA
MC100EPT23
DGNDA
DGNDA
U15
5
NR
OUT
NC = NO CONNECT
1
3
ERR
ADP3330
IN
2
+5VAB_
R63
SD
SD
AGNDB
+3.3VB
AGNDB
100⍀
C27
6
4
0.47F
U11
VCC
C22
C24
0.1F
1
8
0.1F
NC
D
DB
J10
ENCODE
SMA
2
3
4
7
6
5
ENCBB
ENCB
Q
QB
J11
C28
0.1F
VBB
VEE
R60
50⍀
SMA
AGNDB
C23
0.1F
MC10EL16
R64
100⍀
AGNDB
R61
50⍀
R38
33k⍀
C25
0.1F
AGNDB
AGNDB
DGNDB
R3
100⍀
DGNDB
DGNDA
+3.3VDB
C26
U9
R39
33k⍀
AGNDB
1
8
7
6
5
0.1F
U10
NC
D
DB
VBB
VCC
Q
QB
LATCHB
E24
2
3
4
1
2
3
4
8
+3.3VB
D0
VCC
Q0
Q1
7
6
5
D0B
D1B
D1
VEE
R66
100⍀
E22
VEE
MC10EL16
BUFLATB
DGNDB
MC100EPT23
DGNDB
DGNDB
NC = NO CONNECT
E42
E44
E48
E41
E43
E47
BANANA JACKS FOR GNDS AND PWRS
E3
E4
AGNDB
AGNDA
E66
E65
E67
E70
E72
E73
E76
E81
E68
E69
E71
E74
E75
E82
E33
DGNDB
DGNDB
DGNDB
DGNDA
DGNDA
AGNDA
E34
DGNDA
E29
E36
E38
E40
E30
E35
E37
E39
DGNDA
E45
E46
E79
E84
E80
E83
DGNDB
AGNDB
STAND OFFS ON THE BOARD
SO4
SO1
SO2 SO5
SO3 SO6
Figure 9b. Evaluation Board
–13–
REV. B
AD10200
BILL OF MATERIALS LIST FOR AD10200 EVAL BOARD
Qty. Component Name
Ref Des
Value
Description
M/S P/Ns
2
1
2
4
4
74LCX16373MTD
AD10200BZ
ADP3330
BRES0805
BRES0805
U16, U17
U1
U14, U15
R38, R39, R56, R58
R1, R41, R60,
R61
74LCX16374MTD (Fairchild)
AD10200BZ
ADP3330ART-3.3-RL7 (Analog)
ERJ6GEYJ333V (Panasonic)
ERJ6GEYJ510V (Panasonic)
SM 3.3 V Regulator
SM 0805 Resistor
SM 0805 Resistor
33 kΩ
50 Ω
8
BRES0805
CAP2
R3, R4, R42, R43,
R63, R64, R65, R66
C1, C2, C5, C6,
C7, C8, C9, C10,
C12, C16, C17, C18,
C20, C21, C22, C23,
C24, C25, C26, C28,
C33, C34, C35
C13, C27, C38, C39
100 Ω
0.1 µF
SM 0805 Resistor
ERJ6GEYJ101V (Panasonic)
23
SM 0805 Capacitor
GRM40X7R104K025BL
(MENA)
4
CAP2
0.47 µF
47 Ω
SM 1206 Capacitor
VJ1206U474MFXMB
(VITRAMON)
2
4
4
10
2
N49DM
IND2
MC10EL16
BJACK
MC100ELT23
POLCAP2
J1, J2
2×20×100 Male Connector
Inductor
TSW-120-08G-D (Samtec)
2743019447 (Fair Ride)
MC1016EP16D (Motorola)
108-0740-001 (Johnson Comp.)
SY100ELT23L (Micrel-Synergy)
T491C106M016A57280
(KEMET)
L1, L2, L3, L4
U2, U3 U9, U11
BJ1 – BJ10
U4, U10
C3, C4, C14, C15,
C29, C30
R47, R48, R49,
R50, R51, R52,
R53, R54
POWER JACK
6
10 µF
0 Ω
SM 1812 Polar Capacitor
SM 0805 Resistor
8
RES2
ERJ-6GEY0R00V (Panasonic)
4
24
RES4
RES2
R7, R8, R71, R72
R9, R10, R11, R12,
R13, R14, R15, R16,
R17, R18, R23, R24,
R25, R26, R27, R28,
R29, R30, R35, R36,
R40, R44, R45, R46
J4
J7
J11, J12
J5, J10
S01–S04
50 Ω
SM 0805 Resistor
ERJ-6GEYJ510V (Panasonic)
1
1
2
2
4
4
SMA
SMA
SMA
SMA
Stand-Off
Screws
AINA2
AINB2
ENCODE
ENCODE
Stand-Off
Screws (Stand-Off)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
142-0701-201 (Johnson Comp.)
313-2477-016 (Johnson Comp.)
MPMS 0040005PH (Building
Fasteners)
1
PCB
AD10200 Eval Board
GS03363 Rev. A
–14–
REV. B
AD10200
Figure 10a. Bottom View
C 1 4
C 4
C 3 0
R 7 2
R 6 1
U 1 0
C 2 3
R 3 9
R 6 6
R 6 0
C 2 2
R 5 0
R 4 9
R 4
R 8
U 1 1
C 1 7
C 2 7
R 3 8
U 9
R 6 4
U 1 7
R 6 3
R 5 3
R 6 5
C 2 5
U 1 5
C 3 5
C 2 8
C 2 4
C 2 1
C 3 6
E 4 0
C 1 8
G N D T I E
G N D T I E
G N D T I E
G N D T I E
U 1 6
C 3 3
C 3 7
G N D T I E
E 4 8
C 1 0
C 2 0
C 1 5
C 7
C 3 4
C 8
R 4 2
R 4 3
U 3
U 1 4
C 9
R 4
R 3
R 7
U 4
U 2
R 5 6
C 1 3
C 1
R 1
C 6
C 2
R 5 8
R 4 1
R 7 1
C 2 9
C 3
Figure 10b. Bottom Assembly
–15–
REV. B
AD10200
Figure 10c. Ground 1
AGNDB
DGNDB
AGNDA
DGNDA
Figure 10d. Ground 2
–16–
REV. B
AD10200
C 1 4
C 4
C 3 0
R 7 2
R 6 1
C 2 3
U 1 0
R 3 9
U 9
R 6 6
R 6 0
C 2 2
R 5 0
R 8
R 4 9
R 5 4
R 5 3
U 1 1
C 1 7
C 2 7
R 3 8
U 1 7
R 6 3
R 6 5
C 2 5
R 6 4
C 2 8
U 1 5
C 3 5
C 2 4
C 2 1
C 3 6
E 4 0
C 1 8
G N D T I E
G N D T I E
G N D T I E
G N D T I E
U 1 6
C 3 3
C 3 7
G N D T I E
E 4 8
C 1 0
C 2 0
C 1 5
C 7
C 3 4
C 8
R 4 2
R 4 3
U 3
U 1 4
C 9
R 4
R 3
R 7
U 4
U 2
R 5 6
C 1 3
C 1
R 1
C 6
C 2
R 5 8
R 4 1
R 7 1
C 2 9
C 3
Figure 10e. Bottom Silk
Figure 10f. Top View
–17–
REV. B
AD10200
E5
E3
E33
E26
J2
C16
E37
E30
E2
E38
E29
E1
+5VAB
3.3VDB
AGNDB
DGNDB
L2
BJ1
EXTRA
L4
E35
E80
E46
E83
E36
E79
E45
E84
E27
E63
U6
C39
ENCB
ENCBBAR
E58
E62
E59
J10
J11
E60
E61
E55
R11
R10
R30
R29
R28
R27
R26
R12
BUFLATB
LATCHB
E22
E24
C26
R9
R25
R36
R35
R34
R33
R32
R31
E50
REF_B
AINB1
AINB2
U1
J6
ANALOG
DEVICES
COPYRIGHT
J7
E11
E39
E77
E12
2/10 0
GND TIE
E47
GND TIE
GND TIE
E78
E49
REF_A
AD10200 EVALUATION BOARD
E7
PIN
1
GS03363 (A)
BEL
J3
E8
J4
AINA1
R18
R17
R16
R40
R44
R45
R46
R15
R14
R13
R24
R23
R22
R21
R20
R19
J1
AINA2
BUFLATA
E19
LATCHA
E57
E23
ENCA
ENCABAR
C5
E82 E81
E65 E66
E52 E53
E51
J5
J12
E56
E54
E9
E10
C38
E64
E41 E42
E43 E44
E68 E67
E74 E73
E71 E72
E69 E70
E75 E76
U5
L3
BJ2
EXTRA
L1
E28
3.3VDA
+5VAA
AGNDA
DGNDA
C12
E6
E34
E25
E4
Figure 10g. Top Assembly
E5
E3
E33
E26
J2
C16
E37
E30
E2
E38
E29
E1
+5VAB
3.3VDB
AGNDB
DGNDB
L2
BJ1
EXTRA
L4
E35
E80
E46
E83
E36
E79
E45
E84
E27
U6
E63
C39
ENCB
ENCBBAR
E58
E62
E59
J10
J11
E60
E61
E55
R11
R10
R30
R29
R28
R27
R26
R12
BUFLATB
LATCHB
E22
E24
C26
R9
R25
R36
R35
R34
R33
R32
R31
E50
REF_B
AINB1
AINB2
U1
J6
ANALOG
DEVICES
COPYRIGHT
J7
E11
E39
E77
E12
2/10 0
GND TIE
E47
GND TIE
GND TIE
E78
E49
REF_A
AD10200 EVALUATION BOARD
E7
PIN
1
GS03363 (A)
BEL
J3
E8
J4
AINA1
R18
R17
R16
R40
R44
R45
R46
R15
R14
R13
R24
R23
R22
R21
R20
R19
J1
AINA2
BUFLATA
E19
LATCHA
E57
E23
ENCA
ENCABAR
C5
E82 E81
E65 E66
E52 E53
E51
J5
J12
E56
E54
E9
E10
C38
E64
E41 E42
E43 E44
E68 E67
E74 E73
E71 E72
E69 E70
E75 E76
U5
L3
BJ2
EXTRA
L1
E28
3.3VDA
+5VAA
AGNDA
DGNDA
C12
E6
E34
E25
E4
Figure 10h. Top Silk
–18–
REV. B
AD10200
Data Sheet
OUTLINE DIMENSIONS
0.290 (7.37)
MAX
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
9
61
10
60
PIN 1
TOP VIEW
(PINS DOWN)
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
1.070
(27.18)
MIN
0.800
(20.32)
BSC
TOE DOWN
ANGLE
0–8 DEGREES
0.010 (0.254)
26
44
30°
27
43
0.050 (1.27)
0.020 (0.508)
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
DETAIL A
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
DETAIL A
0.230 (5.84)
MAX
ROTATED 90° CCW
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 8. 68-Lead Ceramic Leaded Chip Carrier [CLCC]
(ES-68-3)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD10200BZ
5962-9961002HXA
5962-9961003HXA
−40°C to +85°C
−40°C to +85°C
−50°C to +125°C
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier [CLCC]
ES-68-3
ES-68-3
ES-68-3
©2001–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01634-0-8/16(B)
Rev. B | Page 19 of 19
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