5962-9320901MPA [ADI]
IC DUAL OP-AMP, 2000 uV OFFSET-MAX, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier;
| 型号： | 5962-9320901MPA |
| 厂家： | 
ADI |
| 描述： | IC DUAL OP-AMP, 2000 uV OFFSET-MAX, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier 放大器 CD |
| 文件： | 总24页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply, Rail-to-Rail
Low Power FET-Input Op Amp
AD822
FEATURES
CONNECTION DIAGRAM
True single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 5 V to 30 V
Dual-supply capability from 2.5 V to 15 V
High load drive
Capacitive load drive of 350 pF, G = +1
Minimum output current of 15 mA
Excellent ac performance for low power
800 μA maximum quiescent current per amplifier
Unity-gain bandwidth: 1.8 MHz
Slew rate of 3 V/ꢀs
8
7
6
5
OUT1
–IN1
+IN1
1
2
3
4
V+
OUT2
–IN2
V–
+IN2
AD822
Figure 1. 8-Lead PDIP (N Suffix);
8-Lead MSOP (RM Suffix);
and 8-Lead SOIC_N (R Suffix)
GENERAL DESCRIPTION
The AD822 is a dual precision, low power FET input op amp
that can operate from a single supply of 5 V to 30 V or dual
supplies of ±2ꢀ5 V to ±±5 Vꢀ It has true single-supply capability
with an input voltage range extending below the negative rail,
allowing the AD822 to accommodate input signals below
ground in the single-supply modeꢀ Output voltage swing
extends to within ±0 mV of each rail, providing the maximum
output dynamic rangeꢀ
Good dc performance
800 μV maximum input offset voltage
2 μV/°C typical offset voltage drift
25 pA maximum input bias current
Low noise
13 nV/√Hz @ 10 kHz
No phase inversion
100
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems
Medical instrumentation
10
Low power references and regulators
1
10
100
FREQUENCY (Hz)
10k
1k
Figure 2. Input Voltage Noise vs. Frequency
Offset voltage of 800 μV maximum, offset voltage drift of 2 μV/°C,
input bias currents below 25 pA, and low input voltage noise
provide dc precision with source impedances up to a gigaohmꢀ
The ±ꢀ8 MHz unity-gain bandwidth, –93 dB THD at ±0 kHz,
and 3 V/μs slew rate are provided with a low supply current of
800 μA per amplifierꢀ
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1993–2010 Analog Devices, Inc. All rights reserved.
AD822
TABLE OF CONTENTS
Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±
Typical Performance Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±±
Applications Informationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±8
Input Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±8
Output Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±8
Single-Supply Voltage-to-Frequency Converter ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±9
Applicationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±
Connection Diagram ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±
General Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±
Revision History ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2
Specificationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Absolute Maximum Ratingsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
Thermal Resistance ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
Maximum Power Dissipation ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
ESD Cautionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
Single-Supply Programmable Gain Instrumentation
Amplifier ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 20
Low Dropout Bipolar Bridge Driverꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 20
Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2±
Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
6/06—Rev. F to Rev. G
REVISION HISTORY
Changes to Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±
Changes to Table 4ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
Changes to Table 5ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±2
Changes to Table 6ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
1/10—Rev. H to Rev. I
Changes to Features Section and General Description Sectionꢀ ±
Changes to Endnote ±, Table ±ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 5
Changes to Endnote ±, Table 2ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 7
Changes to Endnote ±, Table 3ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 9
Deleted Table 4; Renumbered Sequentially ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±0
Changes to Table 5ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±2
Updated Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2±
Changes to Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
Deleted 3 V, Single-Supply Stereo Headphone Driver Sectionꢀ 22
Deleted Figure 50; Renumbered Sequentially ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
10/05—Rev. E to Rev. F
Updated FormatꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀUniversal
Changes to Outline Dimensions ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
Updated Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
1/03—Data sheet changed from Rev. D to Rev. E
Edits to Specificationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ2
Edits to Figure ±0ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±6
Updated Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±7
8/08—Rev. G to Rev H.
Changes to Features Section and General Description Sectionꢀ ±
Changed VO to VOUT Throughoutꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Changes to Table ±ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
Changes to Table 2ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 6
Changes to Table 3ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 8
Changes to Table 5ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±2
Added Table 6; Renumbered Sequentially ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±2
Changes to Figure ±3 Captionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±4
Changes to Figure 29, Figure 3±, and Figure 35 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±7
Changes to Figure 36ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±8
Changed Application Notes Section to Applications
10/02—Data sheet changed from Rev. C to Rev. D
Edits to Featuresꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±
Edits to Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ6
Updated SOIC Package Outline ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±7
8/02—Data sheet changed from Rev. B to Rev. C
All Figures Updated ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀGlobal
Edits to Featuresꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±
Updated All Package Outlinesꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±7
7/01—Data sheet changed from Rev. A to Rev. B
All Figures Updated ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀGlobal
CERDIP References Removedꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±, 6, and ±8
Additions to Product Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±
8-Lead SOIC and 8-Lead MSOP Diagrams Added ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ±
Deletion of AD822S Columnꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ2
Edits to Absolute Maximum Ratings and Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀ6
Removed Metallization Photograph ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ6
Information Section ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 20
Changes to Figure 46 and Figure 47ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2±
Changes to Figure 49ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
Changes to Figure 5±ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23
Rev. I | Page 2 of 24
AD822
The AD822 drives up to 350 pF of direct capacitive load as a
follower and provides a minimum output current of ±5 mAꢀ
This allows the amplifier to handle a wide range of load conditionsꢀ
Its combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile amplifier
for the single-supply userꢀ
1V
. . . . . . . .
20µs
. . . . . . . . . . . .
1V
. . . .
. . . . . . . . . . . . . . . .
100
90
5V
.
V
OUT
The AD822 is available in two performance gradesꢀ The A grade
and B grade are rated over the industrial temperature range of
−40°C to +85°Cꢀ
10
. . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . .
0%
0V
(GND)
The AD822 is offered in three varieties of 8-lead packages:
PDIP, MSOP, and SOIC_Nꢀ
1V
Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V,
VIN = 2.5 V Sine Centered at 1.25 V, RL = 100 Ω
Rev. I | Page 3 of 24
AD822
SPECIFICATIONS
VS = 0 V, 5 V @ TA = 25°C, VCM = 0 V, VOUT = 0ꢀ2 V, unless otherwise notedꢀ
Table 1.
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
0.1
0.5
2
2
0.5
2
0.8
1.2
0.1
0.5
2
2
0.5
2
0.4
0.9
mV
mV
μV/°C
pA
nA
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
VCM = 0 V to 4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VOUT = 0.2 V to 4 V
RL = 100 kΩ
500
400
80
80
15
1000
150
30
500
400
80
80
15
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ to 2.5 V
VOUT = 0.25 V to 4.75 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency
Full Power Response
Slew Rate
1.8
210
3
1.8
210
3
MHz
kHz
V/μs
VOUT p-p = 4.5 V
Settling Time
To 0.1%
To 0.01%
VOUT = 0.2 V to 4.5 V
VOUT = 0.2 V to 4.5 V
1.4
1.8
1.4
1.8
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
1.0
1.6
0.5
1.3
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
3
3
Input Bias Current
Crosstalk @ f = 1 kHz
Crosstalk @ f = 100 kHz
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
20
10
RL = 5 kΩ
RL = 5 kΩ
−130
−93
–130
–93
−0.2
66
66
+4
−0.2
69
66
+4
V
dB
dB
VCM = 0 V to 2 V
VCM = 0 V to 2 V
80
80
Rev. I | Page 4 of 24
AD822
A Grade
Typ
B Grade
Typ
Parameter
Input Impedance
Conditions
Min
Max
Min
Max
Unit
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL – VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
15
12
15
12
Capacitive Load Drive
POWER SUPPLY
Quiescent Current, TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.24
80
1.6
1.24
80
1.6
mA
dB
dB
V+ = 5 V to 15 V
66
66
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. I | Page 5 of 24
AD822
VS = ±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise notedꢀ
Table 2.
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
0.1
0.5
2
2
0.5
2
0.8
1.5
0.1
0.5
2
2
0.5
2
0.4
1
mV
mV
μV/°C
pA
nA
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
VCM = −5 V to +4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VOUT = −4 V to +4 V
RL = 100 kΩ
400
400
80
80
20
1000
150
30
400
400
80
80
20
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VOUT = 4.5 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency
Full Power Response
Slew Rate
1.9
105
3
1.9
105
3
MHz
kHz
V/μs
VOUT p-p = 9 V
Settling Time
to 0.1%
to 0.01%
VOUT = 0 V to 4.5 V
VOUT = 0 V to 4.5 V
1.4
1.8
1.4
1.8
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
1.0
3
0.5
2
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
3
3
Input Bias Current
Crosstalk @ f = 1 kHz
Crosstalk @ f = 100 kHz
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
25
10
RL = 5 kΩ
RL = 5 kΩ
−130
−93
−130
−93
−5.2
66
66
+4
−5.2
69
66
+4
V
dB
dB
VCM = −5 V to +2 V
VCM = −5 V to +2 V
80
80
Input Impedance
Differential
Common Mode
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Rev. I | Page 6 of 24
AD822
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
15
12
15
12
Capacitive Load Drive
POWER SUPPLY
Quiescent Current, TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.3
80
1.6
1.3
80
1.6
mA
dB
dB
VSY = 5 V to 15 V
66
66
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. I | Page 7 of 24
AD822
VS = ±±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise notedꢀ
Table 3.
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
0.4
0.5
2
2
3
0.3
0.5
2
1.5
2.5
mV
mV
μV/°C
pA
Maximum Offset Over Temperature
Offset Drift
Input Bias Current
VCM = 0 V
2
25
2
12
VCM = −10 V
VCM = 0 V
40
0.5
2
40
0.5
2
pA
nA
pA
nA
At TMAX
Input Offset Current
At TMAX
5
20
2.5
12
0.5
0.5
Open-Loop Gain
VOUT = −10 V to +10 V
RL = 100 kΩ
500
500
100
100
30
2000
500
45
500
500
100
100
30
2000
500
45
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
20
20
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VOUT = 10 V
−85
−85
dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency
Full Power Response
Slew Rate
1.9
45
3
1.9
45
3
MHz
kHz
V/μs
VOUT p-p = 20 V
Settling Time
to 0.1%
to 0.01%
VOUT = 0 V to 10 V
VOUT = 0 V to 10 V
4.1
4.5
4.1
4.5
μs
μs
MATCHING CHARACTERISTICS
Initial Offset
3
4
2
2.5
mV
mV
μV/°C
pA
dB
dB
Maximum Offset Over Temperature
Offset Drift
3
3
Input Bias Current
Crosstalk @ f = 1 kHz
Crosstalk @ f = 100 kHz
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX
Common-Mode Rejection Ratio (CMRR)
TMIN to TMAX
25
12
RL = 5 kΩ
RL = 5 kΩ
−130
−93
−130
−93
−15.2
70
70
+14
−15.2
74
74
+14
V
dB
dB
VCM = −15 V to +12 V
VCM = −15 V to +12 V
80
90
Input Impedance
Differential
Common Mode
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Rev. I | Page 8 of 24
AD822
A Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
ISOURCE = 20 μA
ISINK = 2 mA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
20
15
20
15
Capacitive Load Drive
POWER SUPPLY
Quiescent Current, TMIN to TMAX
Power Supply Rejection
TMIN to TMAX
350
350
1.4
80
1.8
1.4
80
1.8
mA
dB
dB
VSY = 5 V to 15 V
70
70
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. I | Page 9 of 24
AD822
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packagesꢀ
Parameter
Rating
Supply Voltage
18 V
Internal Power Dissipation
8-Lead PDIP (N)
8-Lead SOIC_N (R)
8-Lead MSOP (RM)
Input Voltage1
Table 5. Thermal Resistance
Package Type
Observe derating curves
Observe derating curves
Observe derating curves
((V+) + 0.2 V) to
((V−) − 20 V)
θJA
90
160
190
Unit
°C/W
°C/W
°C/W
8-lead PDIP (N)
8-lead SOIC_N (R)
8-lead MSOP (RM)
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range (N)
Storage Temperature Range (R, RM)
Operating Temperature Range
A Grade and B Grade
Indefinite
30 V
–65°C to +125°C
–65°C to +150°C
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD822 is limited by the associated rise in junction temperatureꢀ
For plastic packages, the maximum safe junction temperature is
±45°Cꢀ If these maximums are exceeded momentarily, proper
circuit operation is restored as soon as the die temperature is
reducedꢀ Leaving the device in the overheated condition for an
extended period can result in device burnoutꢀ To ensure proper
operation, it is important to observe the derating curves shown
in Figure 27ꢀ
–40°C to +85°C
260°C
Lead Temperature
(Soldering, 60 sec)
1 See the Input Characteristics section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the deviceꢀ This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not impliedꢀ Exposure to absolute
maximum rating conditions for extended periods may affect
device reliabilityꢀ
While the AD822 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditionsꢀ With power
supplies ±±2 V (or less) at an ambient temperature of 25°C or
less, if the output node is shorted to a supply rail, then the
amplifier is not destroyed, even if this condition persists for an
extended periodꢀ
ESD CAUTION
Rev. I | Page 10 of 24
AD822
TYPICAL PERFORMANCE CHARACTERISTICS
70
5
V
= 0V, 5V
S
60
50
40
30
20
10
0
V
= 0V, +5V AND ±5V
S
V
= ±5V
S
0
–5
–5
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
OFFSET VOLTAGE (mV)
Figure 4. Typical Distribution of Offset Voltage (390 Units)
Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and
VS = 5 V
16
14
12
10
8
1k
100
10
V
V
= ±5V
= ±15V
S
S
6
4
1
2
0
0.1
–16
–12 –10 –8
–6
–4
–2
0
2
4
6
8
10
–12
–8
–4
0
4
8
12
16
OFFSET VOLTAGE DRIFT (µV/°C)
COMMON-MODE VOLTAGE (V)
Figure 5. Typical Distribution of Offset Voltage Drift (100 Units)
Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = 15 V
50
45
40
35
30
25
20
15
10
5
100k
10k
1k
100
10
1
0
0.1
20
0
1
2
3
4
5
6
7
8
9
10
40
60
80
100
120
140
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
Figure 6. Typical Distribution of Input Bias Current (213 Units)
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V
Rev. I | Page 11 of 24
AD822
10M
40
20
POS RAIL
NEG RAIL
R = 2kΩ
L
R
= 20kΩ
L
V
= ±15V
S
1M
V
= 0V, +5V
S
POS RAIL
0
POS
RAIL
V
= 0V, +3V
100k
S
–20
–40
NEG RAIL
NEG RAIL
R
= 100kΩ
L
10k
100
1k
10k
100k
0
60
120
180
240
300
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE FROM SUPPLY RAILS (mV)
Figure 13. Input Error Voltage with Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = 5 V
Figure 10. Open-Loop Gain vs. Load Resistance
1k
100
10
10M
1M
R
= 100kΩ
L
V
= ±15V
S
V
= 0V, +5V
S
V
= ±15V
R
= 10kΩ
S
L
V
= 0V, +5V
S
100k
10k
V
= ±15V
S
R
= 600Ω
L
V
= 0V, +5V
S
1
1
10
100
1k
10k
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 11. Open-Loop Gain vs. Temperature
Figure 14. Input Voltage Noise vs. Frequency
300
200
100
–40
–50
R
A
= 10kΩ
L
= –1
CL
–60
R
= 10kΩ
L
R
= 100kΩ
V
= 0V, +3V; V = 2.5V p-p
OUT
L
S
–70
0
–100
–200
–80
V
= ±15V; V = 20V p-p
OUT
S
–90
V
= ±5V; V = 9V p-p
OUT
S
R
= 600Ω
L
–100
–110
V
= 0V, +5V; V = 4.5V p-p
OUT
S
–300
–16
–12
–8
–4
0
4
8
12
16
100
1k
10k
FREQUENCY (Hz)
100k
OUTPUT VOLTAGE (V)
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads
Figure 15. Total Harmonic Distortion (THD) vs. Frequency
Rev. I | Page 12 of 24
AD822
100
80
60
40
20
0
100
80
90
80
70
60
50
40
30
20
10
0
V
= ±15V
S
PHASE
60
V
= 0V, +5V
S
GAIN
V
= 0V, +3V
S
40
20
0
R
C
= 2kΩ
= 100pF
L
L
–20
10M
–20
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
Figure 19. Common-Mode Rejection vs. Frequency
1k
5
A
= +1
CL
= ±15V
V
S
NEGATIVE
RAIL
POSITIVE
RAIL
100
10
4
3
2
1
0
+25°C
–55°C
1
+125°C
0.1
0.01
–55°C
+125°C
100
1k
10k
100k
1M
10M
–1
0
1
2
3
FREQUENCY (Hz)
COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V)
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from
Figure 17. Output Impedance vs. Frequency
Supply Rails (VS − VCM
)
1000
100
10
16
12
8
1%
4
V
– V
OH
S
0.01%
ERROR
0.1%
0
0.01%
–4
–8
V
– V
OL S
1%
–12
–16
0
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
LOAD CURRENT (mA)
SETTLING TIME (µs)
Figure 18. Output Swing and Error vs. Settling Time
Figure 21. Output Saturation Voltage vs. Load Current
Rev. I | Page 13 of 24
AD822
1000
100
90
80
70
60
50
40
30
20
10
0
I
I
= 10mA
SOURCE
= 10mA
SINK
+PSRR
100
10
1
I
= 1mA
= 10µA
SOURCE
I
I
I
= 1mA
SINK
–PSRR
SOURCE
= 10µA
SINK
10
100
1k
10k
100k
1M
10M
10M
80
60
TEMPERATURE (°C)
–60 –40 –20
0
20
40
80
100 120 140
FREQUENCY (Hz)
Figure 22. Output Saturation Voltage vs. Temperature
Figure 25. Power Supply Rejection vs. Frequency
80
70
60
50
40
30
20
10
0
30
25
20
15
10
5
V
= ±15V
R
= 2kΩ
S
L
V
= ±15V
S
–OUT
+
V
= ±15V
S
V
= 0V, +5V
S
V
= 0V, +3V
S
–
–
V
= 0V, +5V
= 0V, +3V
+
+
S
V
= 0V, +5V
S
0
V
= 0V, +3V
S
V
S
0
10k
100k
FREQUENCY (Hz)
1M
–60 –40 –20
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 23. Short-Circuit Current Limit vs. Temperature
Figure 26. Large Signal Frequency Response
2.4
2.2
1600
1400
1200
1000
800
600
400
200
0
T = +125°C
T = +25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
8-LEAD PDIP
8-LEAD SOIC
T = –55°C
8-LEAD MSOP
0
4
8
12
16
20
24
28
32
36
–60
–40
–20
0
20
40
60
TOTAL SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature
Figure 27. Maximum Power Dissipation vs. Temperature for Packages
Rev. I | Page 14 of 24
AD822
–70
–80
5V
5µs
100
90
–90
–100
–110
–120
10
0%
–130
–140
300
1k
3k
10k
30k
100k
300k
1M
Figure 32. Large Signal Response Unity-Gain Follower; VS = 15 V, RL = 10 kΩ
FREQUENCY (Hz)
Figure 28. Crosstalk vs. Frequency
10mV
500ns
V+
0.01µF
100
90
8
+
1/2
V
IN
AD822
–
V
OUT
100pF
R
L
0.01µF
4
10
Figure 29. Unity-Gain Follower
0%
5V
10µs
Figure 33. Small Signal Response Unity-Gain Follower; VS = 15 V, RL = 10 kΩ
100
90
1V
2µs
100
90
10
0%
10
0%
GND
Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity-Gain Follower; VS = 15 V,
RL = 600 Ω
V
OUT
Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step
V+
20kΩ
2.2kΩ
V+
0.1µF
1
1µF
0.01µF
8
2
3
–
–
6
5
8
1/2
AD822
1/2
AD822
7
5kΩ
V
IN
+
1/2
AD822
20V p-p
+
+
5kΩ
V
OUT
100pF
R
L
–
4
V
IN
0.1µF
1µF
V
OUT
CROSSTALK = 20 log
Figure 35. Unity-Gain Follower
10V
IN
V–
Figure 31. Crosstalk Test Circuit
Rev. I | Page 15 of 24
AD822
10kΩ
20kΩ
V
IN
10mV
2µs
V
V+
OUT
0.01µF
100
90
8
–
1/2
AD822
+
100pF
R
L
4
10
Figure 36. Gain-of-Two Inverter
0%
GND
1V
2µs
Figure 39. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step,
Centered 20 mV Below Ground, RL = 10 kΩ
100
90
1V
2µs
100
90
10
0%
GND
10
Figure 37. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step
0%
GND
Figure 40. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V Below Ground, RL = 10 kΩ
10mV
2µs
100
90
500mV
10µs
100
90
10
0%
GND
10
0%
Figure 38. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step,
Centered 40 mV above Ground, RL = 10 kΩ
GND
Figure 41. VS = 3 V, 0 V; Gain-of-2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave
Centered at −0.75 V, RL = 600 Ω
Rev. I | Page 16 of 24
AD822
1V
10µs
. . . .
. . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
100
90
10
. . . . . . . .
. . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
0%
GND
1V
(a)
10µs
1V
1V
. . . . . . . . . . .
. . .
. . . . . . . . . . . .
. . . .
100 . . . .
. . . .
+V
s
90
10
. . . .
0% . . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
. . . .
GND
1V
(b)
5V
R
P
V
IN
V
OUT
Figure 42. (a) Response with RP = 0; VIN from 0 V to +VS
(b) VIN = 0 V to +VS + 200 mV
V
OUT = 0 V to +VS
RP = 49.9 kΩ
Rev. I | Page 17 of 24
AD822
APPLICATIONS INFORMATION
100k
10k
1k
INPUT CHARACTERISTICS
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
In the AD822, N-channel JFETs are used to provide a low offset,
low noise, high impedance input stageꢀ Minimum input common-
mode voltage extends from 0ꢀ2 V below −VS to ± V less than +VSꢀ
Driving the input voltage closer to the positive rail causes a loss
of amplifier bandwidth (as can be seen by comparing the large
signal responses shown in Figure 34 and Figure 37) and increased
common-mode voltage error as illustrated in Figure 20ꢀ
1kHz
RESISTOR JOHNSON
NOISE
100
10
10Hz
The AD822 does not exhibit phase reversal for input voltages
up to and including +VSꢀ Figure 42 shows the response of an
AD822 voltage follower to a 0 V to 5 V (+VS) square wave inputꢀ
The input and output are superimposedꢀ The output tracks the
input up to +VS without phase reversalꢀ The reduced bandwidth
above a 4 V input causes the rounding of the output waveformꢀ
For input voltages greater than +VS, a resistor in series with the
AD822 noninverting input prevents phase reversal, at the expense
of greater input voltage noiseꢀ This is illustrated in Figure 42ꢀ
1
AMPLIFIER-GENERATED
NOISE
0.1
10k
100k
10M
100M
10G
1M
1G
SOURCE IMPEDANCE (Ω)
Figure 43. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD822 unique bipolar rail-to-rail output stage swings within
5 mV of the negative supply and ±0 mV of the positive supply with
no external resistive loadꢀ The approximate output saturation
resistance of the AD822 is 40 Ω sourcing and 20 Ω sinking, which
can be used to estimate output saturation voltage when driving
heavier current loadsꢀ For instance, when sourcing 5 mA, the
saturation voltage to the positive supply rail is 200 mV; when
sinking 5 mA, the saturation voltage to the negative rail is ±00 mVꢀ
Because the input stage uses N-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminalsꢀ If the input voltage is driven more positive
than +VS − 0ꢀ4 V, then the input current reverses direction as
internal device junctions become forward biasedꢀ This is illu-
strated in Figure 7ꢀ
A current limiting resistor should be used in series with the input
of the AD822 if there is a possibility of the input voltage exceed-
ing the positive supply by more than 300 mV, or if an input voltage
is applied to the AD822 when +VS or −VS = 0 Vꢀ The amplifier is
damaged if left in that condition for more than ±0 secondsꢀ A ± kΩ
resistor allows the amplifier to withstand up to ±0 V of conti-
nuous overvoltage and increases the input voltage noise by a
negligible amountꢀ
The open-loop gain characteristic of the amplifier changes as a
function of resistive load, as shown in Figure ±0 to Figure ±3ꢀ
For load resistances over 20 kΩ, the AD822 input error voltage
is virtually unchanged until the output voltage is driven to ±80 mV
of either supplyꢀ
If the AD822 output is overdriven so that either of the output
devices are saturated, the amplifier recovers within 2 ꢁs of its
input returning to the linear operating region of the amplifierꢀ
Input voltages less than −VS are a completely different storyꢀ The
amplifier can safely withstand input voltages 20 V below the
negative supply voltage if the total voltage from the positive
supply to the input terminal is less than 36 Vꢀ In addition, the
input stage typically maintains picoampere (pA) level input
currents across that input voltage rangeꢀ
Direct capacitive loads interact with the effective output imped-
ance of the amplifier to form an additional pole in the amplifier
feedback loop, which can cause excessive peaking on the pulse
response or loss of stabilityꢀ The worst case occurs when the
amplifier is used as a unity-gain followerꢀ Figure 44 shows the
AD822 pulse response as a unity-gain follower driving 350 pFꢀ
This amount of overshoot indicates approximately 20° of phase
margin—the system is stable, but nearing the edgeꢀ Configurations
with less loop gain, and as a result less loop bandwidth, are
much less sensitive to capacitance load effectsꢀ
The AD822 is designed for ±3 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure ±4)ꢀ This noise performance, along with the
AD822 low input current and current noise, means that the
AD822 contributes negligible noise for applications with source
resistances greater than ±0 kΩ and signal bandwidths greater
than ± kHzꢀ This is illustrated in Figure 43ꢀ
Rev. I | Page 18 of 24
AD822
Figure 46 shows a method for extending capacitance load drive
capability for a unity-gain followerꢀ With these component
values, the circuit drives 5000 pF with a ±0% overshootꢀ
20mV
. . . . . . . .
2µs
. . . .
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
100
90
V+
0.01µF
8
+
1/2
100Ω
V
IN
AD822
V
OUT
–
0.01µF
20pF
C
4
L
10
. . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . .
0%
V–
20kΩ
Figure 46. Extending Unity-Gain Follower Capacitive Load Capability
Beyond 350 pF
Figure 44. Small Signal Response of AD822 as
Unity-Gain Follower Driving 350 pF
Figure 45 is a plot of noise gain vsꢀ capacitive load that results in
a 20° phase margin for the AD822ꢀ Noise gain is the inverse of
the feedback attenuation factor provided by the feedback
network in useꢀ
SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY
CONVERTER
The circuit shown in Figure 47 uses the AD822 to drive a low
power timer that produces a stable pulse of width t±ꢀ The positive
going output pulse is integrated by R± and C± and used as one
input to the AD822 that is connected as a differential integratorꢀ
The other input (nonloading) is the unknown voltage, VINꢀ The
AD822 output drives the timer trigger input, closing the overall
feedback loopꢀ
5
4
3
10V
U4
REF02
= 5V
C5
0.1µF
V
REF
2
4
6
5
CMOS
74HCO4
OUT2
OUT1
R
C3
0.1µF
3
SCALE
10kΩ
2
1
U3A
2
U3B
3
1
4
U2
CMOS 555
R2
499kΩ
1%
0.01µF, 2%
C1
300
1k
3k
10k
30k
8
4
R3
116kΩ
CAPACITIVE LOAD FOR 20° PHASE MARGIN (pF)
U1
R
V+
6
3
5
THR
+
OUT
CV
R1
1/2
2
7
499kΩ
1%
TR
AD822B
V
–
DIS
IN
GND
C2
0.01µF
2%
C
L
1
R
F
C4
0.01µF
0V TO 2.5V
FULL SCALE
R1
NOTES
1. f
= V
/
(V
× t ), t = 1.1 × R3 × C6.
1 1
Figure 45. Noise Gain vs. Capacitive Load Tolerance
OUT
IN
= 25kHzRfESFAS SHOWN.
2. R3 = 1% METAL FILM <50ppm/°C TC.
3. R = 10% 20T FILM <100ppm/°C TC.
SCALE
4. t = 33µF FOR f
= 20kHz @ V = 2.0V.
OUT IN
1
Figure 47. Single-Supply Voltage-to-Frequency Converter
Typical AD822 bias currents of 2 pA allow Mꢂ range source
impedances with negligible dc errorsꢀ Linearity errors on the
order of 0ꢀ0±% full scale can be achieved with this circuitꢀ This
performance is obtained with a 5 V single supply that delivers
less than ± mA to the entire circuitꢀ
Rev. I | Page 19 of 24
AD822
SINGLE-SUPPLY PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
OHMTEK
PART # 1043
R1
90kΩ
R2
9kΩ
R3
1kΩ
R4
1kΩ
R5
9kΩ
R6
90kΩ
+
–
V
REF
The AD822 can be configured as a single-supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to ±±5 Vꢀ Using only one AD822 rather
than three separate op amps, this circuit is cost and power efficientꢀ
The 2 pA bias currents of the AD822 FET inputs minimize
offset errors caused by high unbalanced source impedancesꢀ
G = 10
G = 100
G = 100
G = 10
V+
0.1µF
2
3
6
5
–
–
1/2
AD822
1/2
7
+
–
1
R
P
An array of precision thin film resistors sets the in-amp gain to
be either ±0 or ±00ꢀ These resistors are laser trimmed to ratio
match to 0ꢀ0±% and have a maximum differential TC of 5 ppm/°Cꢀ
AD822
1kΩ
+
+
V
OUT
V
V
IN1
4
R
P
1kΩ
IN2
R6
R4 + R5
Table 6. In-Amp Performance
Parameters
(G = 10) V
OUT
= (V
IN1
– V
IN2
)
+V
1+
REF
(
)
VS = 3 V, 0 V
VS = 5 V
R5 + R6
R4
(G = 100) V
OUT
= (V
IN1
– V
IN2
)
+V
REF
1+
(
)
CMRR
74 dB
80 dB
Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V
3 dB BW
G = 10
G = 100
tSETTLING
2 V Step
5 V Step
Noise @ f = 1 kHz
G = 10
G = 100
ISUPPLY (Total)
Figure 49. A Single-Supply Programmable Instrumentation Amplifier
LOW DROPOUT BIPOLAR BRIDGE DRIVER
180 kHz
18 kHz
180 kHz
18 kHz
The AD822 can be used for driving a 350 Ω Wheatstone bridgeꢀ
Figure 50 shows one-half of the AD822 being used to buffer the
AD589, a ±ꢀ235 V low power referenceꢀ The output of 4ꢀ5 V can
be used to drive an analog-to-digital converter (ADC) front endꢀ
The other half of the AD822 is configured as a unity-gain inverter
and generates the other bridge input of −4ꢀ5 Vꢀ Resistor R± and
Resistor R2 provide a constant current for bridge excitationꢀ The
AD620 low power instrumentation amplifier is used to condition
the differential output voltage of the bridgeꢀ The gain of the AD620
is programmed using an external resistor RG and determined by
2 μs
5 μs
270 nV/√Hz
2.2 μV/√Hz
1.10 mA
270 nV/√Hz
2.2 μV/√Hz
1.15 mA
5µs
49ꢀ9 k
100 . . . . . . . .
. . . .
. . . . . . . . . . . .
. . . . . . . . . . .
. . .
G
±
RG
90
V+
49.9kꢀ
+1.235V
+
8
R1
20ꢀ
3
+
1/2
AD822
1
TO A/D CONVERTER
REFERENCE INPUT
AD589
2
–
–
10
. . . . . . . . . . . . . . . .
. . . . . . . . . . . .
. . . .
. . . . . . . .
+V
S
0%
25.4kꢀ 1%
10kꢀ 1%
350ꢀ
1V
7
350ꢀ
350ꢀ
2
3
–
6
R
AD620
350ꢀ
G
Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal;
VS = 5 V, 0 V; Gain = 0
+
5
4
10kꢀ 1%
V
REF
–V
S
6
5
–
1/2
7
10kꢀ 1%
V+
0.1μF
GND
0.1μF
V–
+5V
–5V
–4.5V
+
+
+
AD822
1μF
1μF
+
4
R2
20ꢀ
+
V–
Figure 50. Low Dropout Bipolar Bridge Driver
Rev. I | Page 20 of 24
AD822
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 51. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
5.15
4.90
4.65
3.20
3.00
2.80
4
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
PIN 1
IDENTIFIER
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.65 BSC
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.95
0.85
0.75
15° MAX
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
1.10 MAX
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COPLANARITY
0.10
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. I | Page 21 of 24
AD822
ORDERING GUIDE
Model1
AD822AN
AD822ANZ
AD822AR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
Package Option
Branding
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
AD822AR-REEL
AD822AR-REEL7
AD822ARZ
AD822ARZ-REEL
AD822ARZ-REEL7
AD822ARMZ
AD822ARMZ-REEL
AD822BR
AD822BR-REEL
AD822BR-REEL7
AD822BRZ
AD822BRZ-REEL
AD822BRZ-REEL7
#B4A
#B4A
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
1 Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked.
SPICE model is available at wwwꢀanalogꢀcomꢀ
Rev. I | Page 22 of 24
AD822
NOTES
Rev. I | Page 23 of 24
AD822
NOTES
©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00874-0-1/10(I)
Rev. I | Page 24 of 24
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