5962-8964701PA [ADI]
High Speed, Low Power Monolithic Op Amp; 高速，低功耗单片运算放大器
| 型号： | 5962-8964701PA |
| 厂家： | 
ADI |
| 描述： | High Speed, Low Power Monolithic Op Amp |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Low Power
Monolithic Op Amp
a
AD847
CO NNECTIO N D IAGRAM
FEATURES
Superior Perform ance
High Unity Gain BW: 50 MHz
Low Supply Current: 5.3 m A
P lastic D IP (N),
Sm all O utline (R) and
Cerdip (Q) P ackages
High Slew Rate: 300 V/ s
Excellent Video Specifications
0.04% Differential Gain (NTSC and PAL)
0.19؇ Differential Phase (NTSC and PAL)
Drives Any Capacitive Load
Fast Settling Tim e to 0.1% (10 V Step): 65 ns
Excellent DC Perform ance
High Open-Loop Gain 5.5 V/ m V (RLOAD = 1 k⍀)
Low Input Offset Voltage: 0.5 m V
Specified for ؎5 V and ؎15 V Operation
Available in a Wide Variety of Options
Plastic DIP and SOIC Packages
Cerdip Package
Die Form
MIL-STD-883B Processing
Tape & Reel (EIA-481A Standard)
Dual Version Available: AD827 (8 Lead)
Enhanced Replacem ent for LM6361
Replacem ent for HA2544, HA2520/ 2/ 5 and EL2020
specifications which include an open-loop gain of 3500 V/V
(500 Ω load) and low input offset voltage of 0.5 mV. Common-
mode rejection is a minimum of 78 dB. Output voltage swing is
±3 V into loads as low as 150 Ω. Analog Devices also offers
over 30 other high speed amplifiers from the low noise AD829
(1.7 nV/√Hz) to the ultimate video amplifier, the AD811, which
features 0.01% differential gain and 0.01° differential phase.
APPLICATIONS
Video Instrum entation
Im aging Equipm ent
AP P LICATIO N H IGH LIGH TS
Copiers, Fax, Scanners, Cam eras
High Speed Cable Driver
High Speed DAC and Flash ADC Buffers
1. As a buffer the AD847 offers a full-power bandwidth of
12.7 MHz (5 V p-p with ±5 V supplies) making it outstand-
ing as an input buffer for flash A/D converters.
2. T he low power and small outline package of the AD847
make it very well suited for high density applications such as
multiple pole active filters.
P RO D UCT D ESCRIP TIO N
T he AD847 represents a breakthrough in high speed amplifiers
offering superior ac & dc performance and low power, all at low
cost. T he excellent dc performance is demonstrated by its ±5 V
3. T he AD847 is internally compensated for unity gain opera-
tion and remains stable when driving any capacitive load.
6
5.5
5
4.5
4
0
5
10
15
20
SUPPLY VOLTAGE – ± Volts
Quiescent Current vs. Supply Voltage
AD847 Driving Capacitive Loads
REV. F
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(@ T = +25؇C, unless otherwise noted)
AD847–SPECIFICATIONS
A
Model
AD 847J
AD 847AR
Typ
Conditions
VS
Min
Typ
Max
Min
Max
Units
INPUT OFFSET VOLT AGE1
T MIN to T MAX
±5 V
0.5
1
3.5
0.5
1
4
mV
mV
Offset Drift
15
15
µV/°C
INPUT BIAS CURRENT
T MIN to T MAX
±5 V, ±15 V
±5 V, ±15 V
3.3
6.6
7.2
3.3
6.6
10
µA
µA
INPUT OFFSET CURRENT
T MIN to T MAX
50
300
400
50
300
500
nA
nA
Offset Current Drift
0.3
0.3
nA/°C
OPEN-LOOP GAIN
VOUT = ±2.5 V
RLOAD = 500 Ω
T MIN to T MAX
RLOAD = 150 Ω
VOUT = ±10 V
RLOAD = 1 kΩ
T MIN to T MAX
±5 V
2
1
3.5
1.6
5.5
2
1
3.5
1.6
5.5
V/mV
V/mV
V/mV
±15 V
3
1.5
3
1.5
V/mV
V/mV
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
±5 V
±15 V
35
50
35
50
MHz
MHz
Full Power Bandwidth2
VOUT = 5 V p-p
RLOAD = 500 Ω,
VOUT = 20 V p-p,
RLOAD = 1 kΩ
±5 V
12.7
12.7
MHz
±15 V
±5 V
±15 V
4.7
200
300
4.7
200
300
MHz
V/µs
V/µs
Slew Rate3
RLOAD = 1 kΩ
225
225
Settling T ime
to 0.1%, RLOAD = 250 Ω
–2.5 V to +2.5 V
10 V Step, AV = –1
–2.5 V to +2.5 V
10 V Step, AV = –1
CLOAD = 10 pF
±5 V
±15 V
±5 V
±15 V
±15 V
65
65
140
120
65
65
140
120
ns
ns
ns
ns
to 0.01%, RLOAD = 250 Ω
Phase Margin
RLOAD= 1 kΩ
f ≈ 4.4 MHz, RLOAD = 1 kΩ
f ≈ 4.4 MHz, RLOAD = 1 kΩ
50
0.04
0.19
50
0.04
0.19
Degree
%
Degree
Differential Gain
Differential Phase
±15 V
±15 V
COMMON-MODE REJECT ION
VCM = ±2.5 V
VCM = ±12 V
T MIN to T MAX
±5 V
±15 V
78
78
75
95
95
78
78
75
95
95
dB
dB
dB
POWER SUPPLY REJECT ION
VS = ±5 V to ±15 V
T MIN to T MAX
75
72
86
75
72
86
dB
dB
INPUT VOLT AGE NOISE
INPUT CURRENT NOISE
f = 10 kHz
f = 10 kHz
±15 V
±15 V
15
15
nV/√Hz
pA/√Hz
1.5
1.5
INPUT COMMON-MODE
VOLT AGE RANGE
±5 V
+4.3
–3.4
+14.3
–13.4
+4.3
–3.4
+14.3
–13.4
V
V
V
V
±15 V
OUT PUT VOLT AGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
±5 V
±5 V
±15 V
±15 V
±15 V
3.0
2.5
12
3.6
3
3.0
2.5
12
3.6
3
±V
±V
±V
±V
mA
10
10
Short-Circuit Current
INPUT RESIST ANCE
INPUT CAPACIT ANCE
OUT PUT RESIST ANCE
32
32
300
1.5
15
300
1.5
15
kΩ
pF
Ω
Open Loop
POWER SUPPLY
Operating Range
Quiescent Current
؎4.5
؎18
6.0
7.3
6.3
7.6
؎4.5
؎18
6.0
7.3
6.3
7.6
V
±5 V
4.8
5.3
4.8
5.3
mA
mA
mA
T MIN to T MAX
T MIN to T MAX
±15 V
mA
N
OT ES
lInput Offset Voltage Specifications are guaranteed after 5 minutes at T A = +25°C.
2Full Power Bandwidth = Slew Rate/2 π VPEAK
.
3Slew Rate is measured on rising edge.
All min and max specifications are guaranteed. Specifications in boldface are 100% tested at final electrical test.
Specifications subject to change without notice.
–2–
REV. F
AD847
Model
AD 847AQ
Typ
AD 847S
Typ
Conditions
VS
Min
Max
Min
Max
Units
INPUT OFFSET VOLT AGE1
±5 V
0.5
1
4
0.5
1
4
mV
mV
T MIN to T MAX
Offset Drift
15
15
µV/°C
INPUT BIAS CURRENT
±5 V, ±15 V
±5 V, ±15 V
3.3
5
7.5
3.3
5
7.5
µA
µA
T MIN to T MAX
T MIN to T MAX
INPUT OFFSET CURRENT
50
300
400
50
300
400
nA
nA
Offset Current Drift
OPEN-LOOP GAIN
0.3
0.3
nA/°C
VOUT = ±2.5 V
RLOAD = 500 Ω
T MIN to T MAX
RLOAD = 150 Ω
VOUT = = ±10 V
RLOAD = 1 kΩ
T MIN to T MAX
±5 V
2
1
3.5
1.6
5.5
2
1
3.5
1.6
5.5
V/mV
V/mV
V/mV
±15 V
3
1.5
3
1.5
V/mV
V/mV
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
±5 V
±15 V
35
50
35
50
MHz
MHz
Full Power Bandwidth2
VOUT = 5 V p-p
RLOAD = 500 Ω,
VOUT = 20 V p-p,
RLOAD = 1 kΩ
±5 V
12.7
12.7
MHz
±15 V
±5 V
±15 V
4.7
200
300
4.7
200
300
MHz
V/µs
V/µs
Slew Rate3
RLOAD = 1 kΩ
225
225
Settling T ime
to 0.1%, RLOAD = 250 Ω
–2.5 V to +2.5 V
10 V Step, AV = –1
–2.5 V to +2.5 V
10 V Step, AV = –1
CLOAD = 10 pF
±5 V
±15 V
±5 V
±15 V
±15 V
65
65
140
120
65
65
140
120
ns
ns
ns
ns
to 0.01%, RLOAD = 250 Ω
Phase Margin
R
LOAD = 1 kΩ
50
0.04
0.19
50
0.04
0.19
Degree
%
Degree
Differential Gain
Differential Phase
f ≈ 4.4 MHz, RLOAD = 1 kΩ
f ≈ 4.4 MHz, RLOAD = 1 kΩ
±15 V
±15 V
COMMON-MODE REJECT ION
VCM = ±2.5 V
VCM = ±12 V
T MIN to T MAX
±5 V
±15 V
80
80
75
95
95
80
80
75
95
95
dB
dB
dB
POWER SUPPLY REJECT ION
VS = ±5 V to ±15 V
T MIN to T MAX
75
72
86
75
72
86
dB
dB
INPUT VOLT AGE NOISE
INPUT CURRENT NOISE
f = 10 kHz
f = 10 kHz
±15 V
±15 V
15
15
nV/√Hz
pA/√Hz
1.5
1.5
INPUT COMMON-MODE
VOLT AGE RANGE
±5 V
+4.3
–3.4
+14.3
–13.4
+4.3
–3.4
+14.3
–13.4
V
V
V
V
±15 V
OUT PUT VOLT AGE SWING
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 1 kΩ
±5 V
±5 V
±15 V
±15 V
±15 V
3.0
2.5
12
3.6
3
3.0
2.5
12
3.6
3
±V
±V
±V
±V
mA
RLOAD
=
500 Ω
10
10
Short-Circuit Current
INPUT RESIST ANCE
INPUT CAPACIT ANCE
OUT PUT RESIST ANCE
32
32
300
1.5
15
300
1.5
15
kΩ
pF
Ω
Open Loop
POWER SUPPLY
Operating Range
Quiescent Current
؎4.5
؎18
5.7
7.0
6.3
7.6
؎4.5
؎18
5.7
7.8
6.3
8.4
V
±5 V
4.8
5.3
4.8
5.3
mA
mA
mA
mA
T MIN to T MAX
T MIN to T MAX
±15 V
REV. F
–3–
AD847
ABSO LUTE MAXIMUM RATINGS 1
ESD SUSCEP TIBILITY
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD847 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. T herefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C
(N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Mini-DIP Package: θJA = 100°C/Watt; θJC = 33°C/Watt
Cerdip Package: θJA = 110°C/Watt; θJC = 30°C/Watt
Small Outline Package: θJA = 155°C/Watt; θJC = 33°C/Watt
METALIZATIO N P H O TO GRAP H
Contact factory for latest dimensions.
D imensions shown in inches and (mm).
O RD ERING GUID E
Tem perature
Range – ؇C
P ackage
D escription
P ackage
O ption
Models*
AD847JN
AD847JR
AD847AQ
AD847AR
AD847SQ
AD847SQ/883B
5962-8964701PA
0 to +70
0 to +70
Plastic
SOIC
Cerdip
SOIC
Cerdip
Cerdip
Cerdip
N-8
R-8
Q-8
R-8
Q-8
Q-8
Q-8
–40 to +85
–40 to +85
–55 to +125
–55 to +125
–55 to +125
*AD847 also available in J and S grade chips, and AD847JR and AD847AR are available
*in tape and reel.
–4–
REV. F
AD847
(@ +25؇C and V = ؎15 V, unless otherwise noted)
Typical Characteristics
S
20
20
15
15
+V
IN
+V
OUT
10
10
–V
IN
–V
OUT
5
0
5
0
R
= 500Ω
LOAD
10
0
5
10
SUPPLY VOLTAGE – ± Volts
15
20
0
5
15
20
SUPPLY VOLTAGE – ± Volts
Figure 1. Input Com m on-Mode Range vs. Supply Voltage
Figure 2. Output Voltage Swing vs. Supply Voltage
30
6
25
20
5.5
5
±15 V SUPPLIES
15
10
4.5
4
±5V SUPPLIES
5
0
10
100
1k
10k
0
5
10
15
20
LOAD RESISTANCE – Ω
SUPPLY VOLTAGE – ± Volts
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 4. Quiescent Current vs. Supply Voltage
5
100
10
1
4
V
= ± 5V
S
3
2
0.1
0.01
–60 –40 –20
20
40
60
80
100 120 140
0
10k
100k
1M
10M
100M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 5. Input Bias Current vs. Tem perature
Figure 6. Output Im pedance vs. Frequency
REV. F
–5–
(@ +25؇C and V = ؎15 V, unless otherwise noted)
AD847–Typical Characteristics
S
7
35
6
5
30
25
20
15
4
V
= ± 5V
S
3
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
AMBIENT TEMPERATURE – °C
TEMPERATURE – °C
Figure 8. Short-Circuit Current Lim it vs. Tem perature
Figure 7. Quiescent Current vs. Tem perature
100
80
52
+100°
+80°
+60°
+40°
+20°
0
±15V SUPPLIES
1kΩ LOAD
51
50
60
±5V SUPPLIES
500Ω LOAD
40
20
49
48
0
–20
100
1k
10k
100k
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY – Hz
TEMPERATURE – °C
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
Figure 9. Gain Bandwidth Product vs. Tem perature
80
100
V
= ±15V
= ± 5V
+SUPPLY
80
S
75
70
65
60
55
50
60
V
S
–SUPPLY
40
20
0
10
100
1k
10k
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
LOAD RESISTANCE – Ω
Figure 11. Open-Loop Gain vs. Load Resistance
Figure 12. Power Supply Rejection vs. Frequency
–6–
REV. F
AD847
100
80
60
40
20
0
30
25
20
15
10
5
V
= ±1V p-p
CM
R = 1kΩ
L
0
1M
10M
INPUT FREQUENCY – Hz
100M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 14. Large Signal Frequency Response
Figure 13. Com m on-Mode Rejection vs. Frequency
–70
10
8
–80
6
3V RMS
R =1kΩ
L
4
–90
2ND HARMONIC
2
0.1%
0.1%
1%
1%
–100
0
–2
–110
–4
3RD HARMONIC
–6
–120
–8
–130
–10
0
100
1k
10k
FREQUENCY – Hz
100k
20
40
60
80
100
120
140
160
SETTLING TIME – ns
Figure 15. Output Swing and Error vs. Settling Tim e
Figure 16. Harm onic Distortion vs. Frequency
50
40
30
20
10
0
450
400
350
300
250
200
150
0
–60 –40 –20
20
40
60
80
100 120 140
10
100
1k
10k
100k
1M
10M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 18. Slew Rate vs. Tem perature
Figure 17. Input Voltage Noise Spectral Density
REV. F
–7–
AD847
Figure 19. Inverting Am plifier Configuration
Figure 19a. Inverter Large
Signal Pulse Response
Figure 19b. Inverter Sm all
Signal Pulse Response
Figure 20. Noninverting Am plifier Configuration
Figure 20a. Noninverting
Figure 20b. Noninverting
Large Signal Pulse Response
Sm all Signal Pulse Response
–8–
REV. F
AD847
+V
O FFSET NULLING
S
T he input offset voltage of the AD847 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
C
F
OUTPUT
–IN
+IN
–V
S
Figure 21. Offset Nulling
NULL 1
NULL 8
INP UT CO NSID ERATIO NS
An input resistor (RIN in Figure 20) is required in circuits where
the input to the AD847 will be subjected to transient or con-
tinuous overload voltages exceeding the ±6 V maximum differ-
ential limit. T his resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into their bases.
Figure 22. AD847 Sim plified Schem atic
GRO UND ING AND BYP ASSING
In designing practical circuits with the AD847, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. A large ground plane should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. T he offset voltage er-
ror will be reduced by more than an order of magnitude.
TH EO RY O F O P ERATIO N
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitance at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 kΩ are recommended. If a larger
resistor must be used, a small (<10 pF) feedback capacitor in
parallel with the feedback resistor, RF, may be used to compen-
sate for the input capacitances and optimize the dynamic perfor-
mance of the amplifier.
T he AD847 is fabricated on Analog Devices’ proprietary
complementary bipolar (CB) process which enables the con-
struction of pnp and npn transistors with similar fT s in the
600 MHz to 800 MHz region. T he AD847 circuit (Figure 22)
includes an npn input stage followed by fast pnps in the folded
cascode intermediate gain stage. T he CB pnps are also used in
the current amplifying output stage. T he internal compensation
capacitance that makes the AD847 unity gain stable is provided
by the junction capacitances of transistors in the gain stage.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of
0.1 µF are recommended.
T he capacitor, CF, in the output stage mitigates the effect of ca-
pacitive loads. At low frequencies and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case CF is bootstrapped and does not
contribute to the compensation capacitance of the part. As the
capacitive load is increased, a pole is formed with the output
impedance of the output stage. T his reduces the gain, and
therefore, CF is incompletely bootstrapped. Some fraction of CF
contributes to the compensation capacitance, and the unity gain
bandwidth falls. As the load capacitance is increased, the band-
width continues to fall, and the amplifier remains stable.
REV. F
–9–
AD847
VID EO LINE D RIVER
Figure 24 shows the AD847 driving 100 pF and 1000 pF loads.
T he AD847 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD847 driving a doubly terminated cable in a fol-
lower configuration.
T he termination resistor, RT , (when equal to the cable’s charac-
teristic impedance) minimizes reflections from the far end of the
cable. While operating from ±5 V supplies, the AD847 main-
tains a typical slew rate of 200 V/µs, which means it can drive a
±1 V, 30 MHz signal into a terminated cable.
+V
S
75Ω
COAX
R
IN
100Ω
0.1 µF
Figure 24. AD847 Driving Capacitive Loads
75Ω
COAX
V
IN
V
AD847
OUT
FLASH AD C INP UT BUFFER
75Ω
R
BT
75Ω
R
75Ω
T
T he 35 MHz unity gain bandwidth of the AD847 makes it an
excellent choice for buffering the input of high speed flash A/D
converters, such as the AD9048.
0.1 µF
500Ω
–V
S
Figure 25 shows the AD847 as a unity inverter for the input to
the AD9048.
500Ω
C
C
0.1
SEE TABLE I
–5.2V
AD589
2k
10kΩ
Figure 23. Video Line Driver
Table I. Video Line D river P erform ance Chart
27
100
2N3906
5
0.1
AD741
1k
O ver-
–3 dB BW shoot
1k
VIN*
VSUP P LY CC
1.5kΩ
0.1µF
0 dB or ±500 mV Step ±15
0 dB or ±500 mV Step ±15
0 dB or ±500 mV Step ±15
0 dB or ±500 mV Step ±5
0 dB or ±500 mV Step ±5
0 dB or ±500 mV Step ±5
20 pF 23 MHz
15 pF 21 MHz
0 pF 13 MHz
20 pF 18 MHz
15 pF 16 MHz
4%
0%
0%
2%
0%
0%
ANALOG
INPUT
(0V TO +2V)
R
B
R
1.5kΩ
50Ω
T
43Ω
D1
(MSB)
V
AD847
IN
AD9048
CONVERT
TTL
CONVERT
SIGNAL
0 pF
11 MHz
D8
(LSB)
V
V
*–3 dB bandwidth numbers are for the 0 dBm signal input. Overshoot numbers
are the percent overshoot of the 1 volt step input.
EE
CC
0.1µF
0.1µF
A back-termination resistor (RBT, also equal to the characteristic
impedance of the cable) may be placed between the AD847 out-
put and the cable input, in order to damp any reflected signals
caused by a mismatch between RT and the cable’s characteristic
impedance. T his will result in a flatter frequency response, al-
though this requires that the op amp supply ±2 V to the output
in order to achieve a ±1 V swing at resistor RT .
+5.0V
–5.2V
Figure 25. Flash ADC Input Buffer
–10–
REV. F
AD847
A H igh Speed, Thr ee O p-Am p In-Am p
T he input amplifier (A1 and A2) is an AD827, which is a dual
version of the AD847. T his circuit has the optional flexibility of
both dc and ac trims for common-mode rejection, plus the abil-
ity to adjust for minimum settling time.
T he circuit of Figure 26 lends itself well to CCD imaging and
other video speed applications. It uses two high speed CB pro-
cess op-amps: Amplifier A3, the output amplifier, is an AD847.
EACH
AMPLIFIER
PIN 7 AD847,
+15V
COMM
–15V
+V
S
PIN 8 AD827
10µF
10µF
0.1µF
0.1µF
1µF
1µF
0.1µF
0.1µF
PIN 4
AD847 & AD827
–V
S
1/2
2–8pF
SETTLING TIME
AC CMR ADJUST
AD827
3
2
–V
IN
INPUT
1
A1
CMRR
FREQUENCY
2kΩ
100Hz
1kHz
10kHz
100kHz
1MHz
88.3dB
87.4dB
86.2dB
67.4dB
47.1dB
1kΩ
1kΩ
2kΩ
2
V
OUT
6
A3
R
G
2kΩ
3
R
L
2kΩ
AD847
1.87kΩ
5pF
6
5
7
A2
DC CMR
ADJUST
200Ω
+V
IN
1/2
AD827
2000Ω
CIRCUIT GAIN =
+ 1
R
G
BANDWIDTH, SETTLING TIME AND TOTAL HARMONIC DISTORTION VS. GAIN
THD + NOISE
SMALL
SIGNAL
SETTLING
TIME
BELOW INPUT
LEVEL
C
ADJ
GAIN
R
G
(pF) BANDWIDTH TO 0.1%
@ 10kHz
1
2
10
100
OPEN 2–8
16.1MHz
14.7MHz
4.5MHz
660kHz
200ns
200ns
370ns
2.5µs
82dB
82dB
81dB
71dB
2kΩ
226Ω
20Ω
2–8
2–8
2–8
Figure 26. A High Speed In-Am p Circuit for Data Acquisition
REV. F
–11–
AD847
H IGH SP EED D AC BUFFER
(10.24 V for a 1 kΩ resistor). Note that since the DAC gener-
ates a positive current to ground, the voltage at the amplifier
output will be negative. A 100 Ω series resistor between the
noninverting amplifier input and ground minimizes the offset
effects of op amp input bias currents.
T he wide bandwidth and fast settling time of the AD847 makes
it a very good output buffer for high speed current-output D/A
converters like the AD668. As shown in Figure 27, the op amp
establishes a summing node at ground for the DAC output. T he
output voltage is determined by the amplifier’s feedback resistor
+15V
10µF
TO ANALOG
GROUND PLANE
0.1µF
1
2
3
MSB
V
24
CC
–
REFCOM 23
1V NOMINAL
REFERENCE INPUT
22
21
20
19
+
REFIN1
REFIN2
10k
4
5
1k
I
OUT
100Ω
DIGITAL
INPUTS
AD668
ANALOG
OUTPUT
6
R
LOAD
AD847
ANALOG GROUND PLANE
7
ACOM 18
ANALOG
SUPPLY
GROUND
8
17
16
LCOM
IBPO
9
10µF
0.1µF
–15V
+5V
10
11
15
14
V
EE
THCOM
VTH
100pF
12 LSB
13
1kΩ
Figure 27. High Speed DAC Buffer
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Sm all O utline (R-8) P ackage
Mini-D IP (N-8) P ackage
Cerdip (Q-8) P ackage
0.150 (3.81)
0.005 (0.13) MIN
0.055 (1.40) MAX
5
8
5
0.25
(6.35)
0.31
(7.87)
8
PIN 1
8
5
0.244 (6.20)
0.228 (5.79)
0.157 (3.99)
0.150 (3.81)
0.310 (7.87)
1
4
PIN 1
0.220 (5.59)
PIN 1
1
1
4
4
0.39 (9.91) MAX
0.035±0.01
(0.89±0.25)
0.405 (10.29) MAX
0.165±0.01
(4.19±0.25)
0.060 (1.52)
0.015 (0.38)
0.197 (5.01)
0.189 (4.80)
0.200
(5.08)
MAX
0.18±0.03
(4.57±0.76)
0.125
(3.18)
MIN
0.102 (2.59)
0.094 (2.39)
0.010 (0.25)
0.004 (0.10)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.019 (0.48)
0.014 (0.36)
0.050
(1.27)
BSC
0.018±0.003
(0.46±0.08) (2.54)
0.10
0.033
(0.84)
NOM
SEATING
PLANE
BSC
0.023 (0.58) 0.100
0.070 (1.78)
0.030 (0.76)
0.020 (0.051) x 45
CHAMF
°
SEATING
PLANE
(2.54)
BSC
0.30 (7.62)
REF
0.014 (0.36)
0.190 (4.82)
0.170 (4.32)
0.320 (8.13)
0.290 (7.37)
8
°
0.090
(2.29)
0°
10
0°
°
0.011±0.003
(0.28±0.08)
0.030 (0.76)
0.018 (0.46)
0.098 (0.2482)
0.075 (0.1905)
0.015 (0.38)
0.008 (0.20)
15°
0°
15°
0°
All brand or product nam es m entioned are tradem arks or registered tradem arks of their respective holders.
–12–
REV. F
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