5962-8876403XA [ADI]
8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, CERAMIC, DIP-24;
| 型号： | 5962-8876403XA |
| 厂家： | 
ADI |
| 描述： | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, CERAMIC, DIP-24 CD 转换器 |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS High Speed
4- and 8-Channel 8-Bit ADCs
a
AD7824/AD7828
FUNCTIONAL BLOCK DIAGRAM
FEATURES
4 or 8 Analog Input Channels
Built-In Track-and-Hold Function
10 kHz Signal Handling on Each Channel
Fast Microprocessor Interface
Single 5 V Supply
Low Power: 50 mW
Fast Conversion Rate: 2.5 s/Channel
Tight Error Specification: 1/2 LSB
V
(+)
(–)
DB7
DB6
DB5
DB4
4-BIT
FLASH
ADC
REF
V
REF
(4MSB)
AIN1
THREE-
STATE
DRIVERS
4-BIT
DAC
AIN4
MUX*
V
(+)
REF
16
DB3
DB2
DB1
DB0
4-BIT
FLASH
ADC
AIN8
(4LSB)
ADDRESS
LATCH
DECODE
TIMING AND CONTROL
CIRCUITRY
INT
RD
RDY
CS
A0 A1 A2**
*AD7824 – 4-CHANNEL MUX
**AD7828 – 8-CHANNEL MUX
A2 – AD7828 ONLY
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7824 and AD7828 are high speed, multichannel, 8-bit
ADCs with a choice of four (AD7824) or eight (AD7828) multi-
plexed analog inputs. A half-flash conversion technique gives a fast
conversion rate of 2.5 µs per channel, and the parts have a built-in
track-and-hold function capable of digitizing full-scale signals of
10 kHz (157 mV/µs slew rate) on all channels. The AD7824 and
AD7828 operate from a single 5 V supply and have an analog input
range of 0 V to 5 V, using an external 5 V reference.
1. 4- or 8-channel input multiplexer gives cost effective,
space-saving multichannel ADC system.
2. Fast conversion rate of 2.5 µs/channel features a per-channel
sampling frequency of 100 kHz for the AD7824 or 50 kHz
for the AD7828.
3. Built-in track-and-hold function allows handling of four or
eight channels up to 10 kHz bandwidth (157 mV/µs slew rate).
4. Tight total unadjusted error spec and channel-to-channel
matching eliminate the need for user trims.
Microprocessor interfacing of the parts is simple, using standard
Chip Select (CS) and Read (RD) signals to initiate the conversion
and read the data from the three-state data outputs. The half-flash
conversion technique means that there is no need to generate a
clock signal for the ADC. The AD7824 and AD7828 can be
interfaced easily to most popular microprocessors.
5. Single 5 V supply simplifies system power requirements.
6. Fast, easy-to-use digital interface allows connection to most
popular microprocessors with minimal external components.
No clock signal is required for the ADC.
The AD7824 and AD7828 are fabricated in an advanced, all
ion-implanted, linear compatible CMOS process (LC2MOS) and
have low power dissipation of 40 mW (typ). The AD7824 is
available in a 0.3" wide, 24-lead “skinny” DIP, while the AD7828
is available in a 0.6" wide, 28-lead DIP and in 28-terminal surface-
mount packages.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(V = 5 V, VREF (+) = 5 V, VREF (–) = GND = O V, unless otherwise
noted. All specifications TMIN to TMAX, unless otherwise noted. Specifications apply to Mode 0.)
AD7824/AD7828–SPECIFICATIONS
DD
Parameter
K Version1 L Version B, T Versions
C, U Versions Unit
Conditions/Comments
ACCURACY
Resolution
8
8
8
8
8
8
8
8
Bits
LSB max
Total Unadjusted Error2
Minimum Resolution for which
No Missing Codes Are Guaranteed
Channel-to-Channel Mismatch
1
1/2
1/4
1
1/2
1/4
Bits
LSB max
1/4
1/4
REFERENCE INPUT
Input Resistance
1.0/4.0
VREF (–)/
VDD
1.0/4.0
VREF (–)/
VDD
1.0/4.0
VREF (–)/
VDD
1.0/4.0
VREF (–)/
VDD
kΩ min/kΩ max
V min/V max
V
REF (+) Input Voltage Range
VREF (–) Input Voltage Range
GND/
VREF (+)
GND/
VREF (+)
GND/
VREF (+)
GND/
VREF (+)
V min/V max
V min/V max
ANALOG INPUT
Input Voltage Range
VREF (–)/
VREF (–)/
VREF (+)
3
VREF (–)/
VREF (+)
3
VREF (–)/
VREF (+)
3
V
REF (+)
Input Leakage Current
Input Capacitance3
3
45
µA max
pF typ
Analog Input Any Channel
0 V to 5 V
45
45
45
LOGIC INPUTS
RD, CS, A0, A1, and A2
VINH
VINL
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
V min
V max
µA max
µA max
pF max
IINH
IINL
Input Capacitance3
Typically 5 pF
LOGIC OUTPUTS
DB0–DB7 and INT
VOH
4.0
0.4
3
4.0
0.4
3
4.0
0.4
3
4.0
0.4
3
V min
ISOURCE = 360 µA
ISINK = 1.6 mA
Floating State Leakage
Typically 5 pF
VOL
V max
µA max
pF max
IOUT (DB0–DB7)
Output Capacitance3
RDY
8
8
8
8
4
VOL
0.4
3
8
0.4
3
8
0.4
3
8
0.4
3
8
V max
µA max
pF max
ISINK = 2.6 mA
Floating State Leakage
Typically 5 pF
IOUT
Output Capacitance
SLEW RATE, TRACKING3
0.7
0.157
0.7
0.157
0.7
0.157
0.7
0.157
V/µs typ
V/µs max
POWER SUPPLY
VDD
5
5
5
5
V
5% for Specified
Performance
CS = RD = 2.4 V
5
IDD
16
50
80
1/4
16
50
80
1/4
20
50
100
1/4
20
50
100
1/4
mA max
mW typ
mW max
LSB max
Power Dissipation
Power Supply Sensitivity
1/16 LSB typ
VDD = 5 V 5%
NOTES
1Temperature ranges are as follows: K, L Versions: 0°C to 70°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C
2Total Unadjusted Error includes offset, full-scale and linearity errors.
3Sample tested at 25°C by Product Assurance to ensure compliance.
4RDY is an open-drain output.
5See Typical Performance Characteristics.
Specifications subject to change without notice.
–2–
REV. F
AD7824/AD7828
TIMING CHARACTERISTICS1
(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)
Limit at 25؇C
Limit at TMIN, TMAX
Limit at TMIN, TMAX
Parameter
(All Grades)
(K, L, B, C Grades)
(T, U Grades)
Unit
Conditions/Comments
tCSS
tCSH
tAS
tAH
tRDY
0
0
0
30
40
0
0
0
35
60
0
0
0
40
60
ns min
ns min
ns min
ns min
ns max
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 kΩ.
Conversion Time, Mode 0
Data Access Time after RD
Data Access Time after INT, Mode 0
RD to INT Delay
2
tCRD
tACC1
tACC2
tlNTH
2.0
85
50
2.4
110
60
2.8
120
70
µs max
ns max
ns max
ns typ
3
3
2
40
65
70
75
60
500
60
600
100
70
500
80
100
70
600
80
ns max
ns max
ns min
ns min
ns max
4
tDH
tP
tRD
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
500
400
NOTES
1Sample tested at 25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
DBN
3k⍀
10pF
3k⍀
100pF
DGND
DGND
a. VOH to High-Z
a. High-Z to VOH
5V
5V
3k⍀
3k⍀
DBN
DBN
10pF
DGND
100pF
DGND
b. VOL to High-Z
b. High-Z to VOL
Figure 2. Load Circuits for Data Hold Time Test
Figure 1. Load Circuits for Data Access Time Test
REV. F
–3–
AD7824/AD7828
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
Operating Temperature Range
Commercial (K, L Versions) . . . . . . . . . . . . . . 0°C to 70°C
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V
Digital Input Voltage to GND
(RD, CS, A0, A1, and A2) . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to GND
(DB0, DB7, RDY, and INT) . . . . . . . –0.3 V, VDD + 0.3 V
VREF (+) to GND . . . . . . . . . . . . . . . . . VREF (–), VDD + 0.3 V
VREF (–) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VREF (+)
Analog Input (Any Channel) . . . . . . . . . . –0.3 V, VDD + 0.3 V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although AD7824/AD7828 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP/SOIC/SSOP
ORDERING GUIDE
Total
Temperature
Range
Unadjusted
Error (LSBs) Option
Package
Model
1
2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
NC
28 AIN7
27 AIN8
AIN4
AIN3
AIN2
AIN1
NC
V
DD
NC
AD7824KN
AD7824LN
AD7824KR
AD7824BQ
AD7824CQ
0°C to 70°C
1
1/2
1
1
1/2
1
N-24
N-24
R-24
Q-24
Q-24
Q-24
Q-24
3
3
26
V
DD
A0
0°C to 70°C
4
4
25 A0
A1
0°C to 70°C
5
5
24 A1
DB7
DB6
DB5
DB4
–40°C to +85°C
–40°C to +85°C
AD7824
TOP VIEW
(Not to Scale)
6
6
23 A2
DB0
DB1
DB2
DB3
AD7828
TOP VIEW
(Not to Scale)
7
7
22 DB7
21 DB6
20 DB5
19 DB4
AD7824TQ* –55°C to +125°C
8
8
DB0
DB1
DB2
DB3
RD
AD7824UQ* –55°C to +125°C
1/2
9
9
CS
AD7828KN
AD7828LN
AD7828KP
AD7828LP
AD7828BQ
AD7828CQ
AD7828BR
0°C to 70°C
1
1/2
1
1/2
1
1/2
+1
1/2
1
1/2
1
1/2
N-28
N-28
P-28A
P-28A
Q-28
Q-28
R-28
RS-28
Q-28
Q-28
E-28A
E-28A
10
11
12
13
14
10
11
12
RDY
RD
INT
0°C to 70°C
18
V
REF
(+)
(–)
CS
0°C to 70°C
17 RDY
GND
V
REF
0°C to 70°C
16
15
V
(+)
(–)
INT
REF
NC = NO CONNECT
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
GND
V
REF
NC = NO CONNECT
PLCC
AD7828LRS 0°C to 70°C
AD7828TQ* –55°C to +125°C
AD7828UQ* –55°C to +125°C
AD7828TE* –55°C to +125°C
AD7828UE* –55°C to +125°C
4
3
2
1
28 27 26
PIN 1
5
6
25
AIN2
AIN1
NC
A0
IDENTIFIER
24 A1
23
*Available to /883B processing only. Contact our local sales office for military
data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing
#5692-88764.
7
A2
22 DB7
AD7828
DB0
DB1
DB2
8
TOP VIEW
(Not to Scale)
9
21
20
19
DB6
DB5
DB4
LCCC
10
DB3 11
4
3
2
1
28 27 26
12 13 14 15 16 17 18
25
24
23
22
21
20
19
5
6
A0
AIN2
AIN1
NC
A1
7
A2
AD7828
TOP VIEW
(Not to Scale)
NC = NO CONNECT
8
DB0
DB1
DB2
DB3
DB7
DB6
DB5
DB4
9
10
11
12 13 14 15 16 17 18
NC = NO CONNECT
–4–
REV. F
Typical Performance Characteristics–AD7824/AD7828
3
14
13
12
V
= 5V
DD
V
= 5.25V
DD
2
11
10
9
V
= 5V
DD
V
= 4.75V
50
DD
8
1
–100
–50
T
0
50
100
150
–100
–50
T
0
100
150
900
150
– AMBIENTTEMPERATURE – ؇C
– AMBIENTTEMPERATURE – ؇C
A
A
TPC 1. Conversion Time vs. Temperature
TPC 4. Power Supply Current vs. Temperature
(Not Including Reference Ladder)
2.0
1.5
2.0
V
= 5V
= 5V
= 25؇C
DD
V
= 5V
DD
V
REF
T
= 25؇C
A
T
A
1.5
1.0
0.5
1.0
0.5
0
0
0
1
2
3
4
5
300
400
500
600
700
800
V
–V
tP – ns
REF
V
REF
256
*1LSB =
TPC 2. Accuracy vs. VREF [VREF = VREF (+) – VREF (–)]
TPC 5. Accuracy vs. tP
–36
10
8
ENCODE RATE = 400kHz
INPUT SIGNAL = 5V p-p
V
= 5V
DD
–38
MEASUREMENT BANDWIDTH = 80kHz
–40
I
, V = 2.4V
SOURCE OUT
–42
6
–44
–46
–48
–50
4
I
, V = 0.4V
SINK OUT
2
0
–100
–52
1
2
3
4
5
7
10
20 30 40 50 70 100
–50
0
50
100
INPUT FREQUENCY – kHz
T
– AMBIENTTEMPERATURE – ؇C
A
TPC 3. Signal Noise Ratio vs. Input Frequency
TPC 6. Output Current vs. Temperature
REV. F
–5–
AD7824/AD7828
OPERATIONAL DIAGRAM
APPLYING THE AD7824/AD7828
The AD7824 is a 4-channel 8-bit ADC and the AD7828 is an
8-channel 8-bit ADC. Operational diagrams for both of these
devices are shown in Figures 3 and 4. The addition of just a 5 V
reference allows the devices to perform the analog-to-digital function.
REFERENCE AND INPUT
The two reference inputs on the AD7824/AD7828 are fully differ-
ential and define the zero to full-scale input range of the ADC.
As a result, the span of the analog input voltage for all channels
can easily be varied. By reducing the reference span, VREF (+) to
VREF (–), to less than 5 V, the sensitivity of the converter can be
increased (e.g., if VREF = 2 V then 1 LSB = 7.8 mV). The input/
reference arrangement also facilitates ratiometric operation.
AIN4
AIN3
AIN2
AIN1
NC
1
2
24
23
22
21
20
19
18
17
16
15
14
13
5V
V
DD
NC
A0
ANALOG INPUTS
0V TO 5V
3
P ADDRESS
BUS
This reference flexibility also allows the input channel voltage
span to be offset from zero. The voltage at VREF (–) sets the
input level for all channels, which produces a digital output of
all zeroes. Therefore, although the analog inputs are not them-
selves differential, they have nearly differential input capability
in most measurement applications because of the reference
design. Figures 5 to 7 show some of the configurations that are
possible.
4
A1
AD7824
5
DB7
DB6
DB5
DB4
DB0
DB1
DB2
DB3
6
P 4MSB
DATA BUS
7
P 4LSB
DATA BUS
8
P CONTROL INPUT
9
CS
10
11
12
RD
RDY
P CONTROL INPUT
STATUS OUTPUT
5V
V
(+)
(–)
STATUS OUTPUT
INT
GND
REF
V
REF
V
(+)
(–)
AIN1
GND
NC = NO CONNECT
IN
AD7824*
AD7828*
V
IN
Figure 3. AD7824 Operational Diagram
5V
V
DD
0.1F
47F
V
(+)
REF
1
2
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
NC
AIN7 28
AIN8 27
ANALOG INPUTS
0V TO 5V
V
(–)
REF
5V
3
V
DD
26
ANALOG INPUTS
0V TO 5V
4
A0 25
A1 24
*ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
P ADDRESS
BUS
5
6
A2 23
Figure 5. Power Supply as Reference
AD7828
7
DB7 22
DB6 21
DB5 20
DB4 19
8
DB0
DB1
DB2
DB3
RD
P 4MSB
DATA BUS
V
(+)
(–)
AIN1
GND
IN
9
P 4LSB
DATA BUS
AD7824*
AD7828*
10
11
12
13
14
V
IN
P CONTROL INPUT
STATUS OUTPUT
5V
18
CS
5V
V
DD
P CONTROL INPUT
RDY 17
(+) 16
0.1F
47F
AD580
V
(+)
REF
STATUS OUTPUT
V
V
INT
REF
0.1F
10F
V
(–)
REF
GND
(–) 15
REF
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
Figure 4. AD7828 Operational Diagram
CIRCUIT INFORMATION
Figure 6. External Reference Using the AD580, Full-Scale
Input is 2.5 V
BASIC DESCRIPTION
The AD7824/AD7828 uses a half-flash conversion technique
whereby two 4-bit flash ADCs are used to achieve an 8-bit result.
Each 4-bit flash ADC contains 15 comparators that compare
the unknown input to a reference ladder to get a 4-bit result.
For a full 8-bit reading to be realized, the upper 4-bit flash, the
most significant (MS) flash, performs a conversion to provide
the four most significant data bits. An internal DAC, driven by
the four MSBs, then recreates an analog approximation of the
input voltage. This analog result is subtracted from the input,
and the difference is converted by the lower flash ADC, the least
significant (LS) flash, to provide the four least significant bits of
the output data. The most significant flash ADC also has one
additional comparator to detect overrange on the analog input.
V
(+)
AIN1
GND
IN
AD7824*
AD7828*
5V
V
DD
DB7
0.1F
47F
V1
V2
V
(+)
(–)
REF
DATA
DB0
V
REF
*ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
V
(+)
IN
V1 –V2
DATA =
؋
256 (FOR ALL CHANNELS) Figure 7. Input Not Referenced to GND
–6–
REV. F
AD7824/AD7828
interest. It is important that the amplifier driving the AD7824/
AD7828 analog inputs have sufficient loop gain at the input signal
frequency as to make the output impedance low.
INPUT CURRENT
Due to the novel conversion techniques employed by the AD7824/
AD7828, the analog input behaves somewhat differently than in
conventional devices. The ADC’s sampled-data comparators
take varying amounts of input current depending on which cycle
the conversion is in.
Suitable op amps for driving the AD7824/AD7828 are the AD544
or AD644.
The equivalent input circuit of the AD7824/AD7828 is shown
in Figure 8. When a conversion starts (CS and RD going low),
all input switches close, and the selected input channel is con-
nected to the most significant and least significant comparators.
Therefore, the analog input is simultaneously connected to
31 input capacitors of 1 pF each.
INHERENT SAMPLE-HOLD
A major benefit of the AD7824’s and AD7828’s analog input
structure is its ability to measure a variety of high speed signals
without the help of an external sample-and-hold. In a conven-
tional SAR type converter, regardless of its speed, the input
must remain stable to at least 1/2 LSB throughout the conversion
process if rated accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally sampled
and held stationary during the conversion. The AD7824/AD7828
input comparators, by nature of their input switching, inherently
accomplish this sample-and-hold function. Although the conver-
sion time for AD7824/AD7828 is 2 µs, the time for which any
selected analog input must be 1/2 LSB stable is much smaller.
The AD7824/AD7828 tracks the selected input channel for
approximately 1 µs after conversion start. The value of the analog
input at that instant (1 µs from conversion start) is the measured
value. This value is then used in the least significant flash to
generate the lower four bits of data.
C
S
2pF
1pF
R
R
ON
R MUX
S
AIN1
•
•
•
V
IN
C
S
12pF
TO LS
LADDER
1pF
15LSB
COMPARATORS
1pF
•
•
•
R
ON
AD7824/
AD7828
TO MS
SINUSOIDAL INPUTS
1pF
LADDER
The AD7824/AD7828 can measure input signals with slew rates
as high as 157 mV/µs to the rated specifications. This means that
the analog input frequency can be up to 10 kHz without the aid
of an external sample-and-hold. Furthermore, the AD7828 can
measure eight 10 kHz signals without a sample-and-hold. The
Nyquist criterion requires that the sampling rate be twice the
input frequency (i.e., 2 × 10 kHz). This requires an ideal anti-
aliasing filter with an infinite roll-off. To ease the problem of
antialiasing filter design, the sampling rate is usually much greater
16MSB
COMPARATORS
Figure 8. AD7824/AD7828 Equivalent Input Circuit
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 3 kΩ to 6 kΩ). In
addition, about 14 pF of input stray capacitance must be charged.
The analog input for any channel can be modelled as an RC
network, as shown in Figure 9. As RS increases, it takes longer
for the input capacitance to charge.
than the Nyquist criterion. The maximum sampling rate (FMAX
for the AD7824/AD7828 can be calculated as follows:
)
1
FMAX
=
=
R
350⍀
R MUX
ON
tCRD + tP
R
800⍀
S
AIN1
C
C
S2
2pF
S1
V
31pF
1
IN
12pF
FMAX
= 400 kHz
2E – 6 + 0.5E – 6
t
CRD = AD7824/AD7828 Conversion Time
tP = Minimum Delay Between Conversion
Figure 9. RC Network Model
This permits a maximum sampling rate of 50 kHz for each of
the eight channels when using the AD7828 and 100 kHz for
each of the four channels when using the AD7824.
The time for which the input comparators track the analog input
is approximately 1 µs at the start of conversion. Because of input
transients on the analog inputs, it is recommended that a source
impedance no greater than 100 Ω be connected to the analog
inputs. The output impedance of an op amp is equal to the open
loop output impedance divided by the loop gain at the frequency of
REV. F
–7–
AD7824/AD7828
UNIPOLAR OPERATION
25k⍀
The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
40k⍀
27k⍀
V
IN
AD544
AIN1
AD7824*
AD7828*
5V
12k⍀
5V
V
(+)
REF
5V
V
DD
0.1F
47F
DB7
DB0
V
(–)
REF
GND
5V
V
DD
0.1F
47F
V
REF
5V
V
(+)
(–)
REF
AIN1
*ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
AD7824*
AD7828*
V
IN
0VTO 5V
DB7
Figure 12. AD7824/AD7828 Bipolar 4 V Operation
V
REF
GND
DB0
11111111
FS = 8V
1LSB = FS/256
*ADDITIONAL PINS OMITTED FOR CLARITY.
11111110
11111101
10000010
10000001
ONLY CHANNEL 1 SHOWN.
Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation
+FS
2
FULL-SCALE
TRANSITION
10000000
01111111
–FS
2
+ 1LSB
11111111
11111110
11111101
01111110
00000010
00000001
00000000
FS
1LSB =
256
0V
AIN, INPUTVOLTAGE – LSB
00000011
00000010
00000001
00000000
Figure 13. Ideal Input/Output Transfer Characteristic for
4 V Operation
TIMING AND CONTROL
0
1LSB 2LSB 3LSB
AIN, INPUTVOLTAGE – LSB
FS
FS – 1LSB
The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (CS) and Read (RD). A READ
operation brings CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e., CS and RD are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.
Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (VIN) so that only
positive voltages appear at AIN1. The closed loop transfer func-
tion of the op amp for the resistor values shown is given below:
AIN1 = 2.5 − 0.625V Volts
(
)
IN
Table I. Truth Table for Input Channel Selection
The analog input range is 4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
AD7824
AD7828
A1 A0
A1
A0
A2
Channel
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
–8–
REV. F
AD7824/AD7828
MODE 0
MODE 1
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors that have a WAIT
state facility, whereby a READ instruction cycle can be extended
to accommodate slow memory devices. A READ operation brings
CS and RD low, which starts a conversion. The analog multiplexer
address inputs must remain valid while CS and RD are low. The
data bus (DB7–DB0) remains in the three-state condition until
conversion is complete. There are two converter status outputs on
the AD7824/AD7828, interrupt (INT) and ready (RDY), which
can be used to drive the microprocessor READY/WAIT input.
The RDY is an open-drain output (no internal pull-up device) that
goes low on the falling edge of CS and goes high impedance at the
end of conversion when the 8-bit conversion result appears on the
data outputs. If the RDY status is not required, the external
pull-up resistor can be omitted and the RDY output tied to GND.
The INT goes low when conversion is complete and returns high
on the rising edge of CS or RD.
Mode 1 operation is designed for applications where the micropro-
cessor is not forced into a WAIT state. A READ operation takes
CS and RD low, which triggers a conversion (see Figure 15). The
multiplexer address inputs are latched on the rising edge of RD.
Data from the previous conversion is read from the three-state
data outputs (DB7–DB0). This data may be disregarded if not
required. Note that the RDY output (open drain output) does
not provide any status information in this mode and must be
connected to GND. At the end of conversion, INT goes low. A
second READ operation is required to access the new conversion
result. This READ operation latches a new address into the multi-
plexer inputs and starts another conversion. INT returns high at the
end of the second READ operation, when CS or RD returns high.
A delay of 2.5 µs must be allowed between READ operations.
CS
tCSH
tCSS
tCSS
RD
tP
tAS
tAS
ANALOG
CHANNEL
ADDRESS
ADDRESS
VALID
ADDRESS
VALID
tAH
RDY
tRDY
tINTH
INT
tCRD
tACC2
tDH
HIGH IMPEDANCE
DATA
VALID
DATA
Figure 14. Mode 0 Timing Diagram
CS
RD
tCSS
tCSH
tCSS
tCSH
tRD
tRD
tP
tAS
tAS
ANALOG
CHANNEL
ADDRESS
ADDRESS
VALID
ADDRESS
VALID
tAH
tCRD
tAH
tINTH
tINTH
INT
tACC1
tDH
tACC1
tDH
OLD
VALID
NEW
VALID
DATA
Figure 15. Mode 1 Timing Diagram
REV. F
–9–
AD7824/AD7828
to any of the addresses in Table II starts a conversion and reads
the conversion result.
MICROPROCESSOR INTERFACING
The AD7824/AD7828 is designed to interface to microprocessors
as Read Only Memory (ROM). Analog channel selection, con-
version start, and data read operations are controlled by CS, RD,
and the channel address inputs. These signals are common to
all memory peripheral devices.
MOVE × B $C000, D0
Once conversion has begun, the MC68000 inserts WAIT states
until INT goes low, asserting DTACK at the end of conversion.
The microprocessor then places the conversion results into the
D0 register.
Z80 MICROPROCESSOR
Figure 16 shows a typical AD7824/AD7828–Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow-
ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the
conversion result.
A23
A2
A1
ADDRESS BUS
A0
A1
A0 A1 A2**
CS
ADDRESS
DECODE
AS
EN
LD B, (C000)
R/W
RD
At the beginning of the instruction cycle when the ADC
address is selected, RDY asserts the WAIT input so that the
Z80 is forced into a WAIT state. At the end of conversion,
RDY returns high and the conversion result is placed in the B
register of the microprocessor.
CLR
7474
MC68000
AD7824*
AD7828*
5V
5k⍀
D
DTACK
CK
RDY
DB7
Q
D7
DATA BUS
A15
A2
A1
D0
ADDRESS BUS
DB0
A0
A0
A0 A1 A2**
ADDRESS
DECODE
EN
MREQ
Z80
*
**
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FORTHE AD7828 ONLY
5V
5k⍀
CS
AD7824*
AD7828*
Figure 17. AD7824/AD7828–MC68000 Interface
RDY
WAIT
RD
RD
TMS32010 MICROCOMPUTER
D7
DB7
A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no µP WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
DATA BUS
D0
DB0
IN, A PA (PA = PORT ADDRESS)
*
**
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FORTHE AD7828 ONLY
The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete, a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5 µs must be allowed
between conversions.
Figure 16. AD7824/AD7828–Z80 lnterface
Table II. Address Channel Selection
AD7824
Channel
AD7828
Channel
Address
PA2
PA1
PA0
A2**
A1
C000
C001
C002
C003
C004
C005
C006
C007
1
2
3
4
1
2
3
4
5
6
7
8
AD7824*
AD7828*
A0
TMS32010
MEN
CS
DEN
RD
D7
DB7
DATA BUS
D0
DB0
MC68000 MICROPROCESSOR
Figure 17 shows an MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
*
**
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FORTHE AD7828 ONLY
Figure 18. AD7824/AD7828–TMS32010 Interface
REV. F
–10–
AD7824/AD7828
5V
SAMPLE
PULSE
15V
5V
BAND-PASS
FILTER 1
V
DD
AIN1
AIN2
CS
RD
10V
V
V
RD
INT
CS
DD
DD
BAND-PASS
FILTER 2
V
REF
WR
AIN1
AIN2
AIN3
AIN4
AD7226
SPEECH
INPUT
DB7
DB0
AMP
DB7
DB0
DB7
DB0
V
V
V
A
B
C
D
V 1
O
V
V
O
V
O
OUT
AD7828
DATA
2
3
4
BAND-PASS
FILTER 7
OUT
O
AIN7
AIN8
OUT
AD7824
A1
A0
A1
A0
A2
A1
A0
V
V
V
(+)
(–)
OUT
BAND-PASS
FILTER 8
REF
DGND
AGND
REF
GND
V
SS
V
(+)
5V
REF
V
(–) GND
REF
Figure 20. 4-Channel Fast Infinite Sample-and-Hold
Figure 19. Speech Analysis Using Real-Time Filtering
OUTLINE DIMENSIONS
24-Lead Plastic Dual-in-Line Package [PDIP]
(N-24)
Dimensions shown in inches and (millimeters)
1.185 (30.01)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
1.165 (29.59)
1.145 (29.08)
24
1
13
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.180
(4.57)
MAX
0.015 (0.38) MIN
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.100
(2.54)
BSC
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.060 (1.52) SEATING
0.050 (1.27)
0.045 (1.14)
PLANE
COMPLIANT TO JEDEC STANDARDS MO-095AG
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Plastic Dual-in-Line Package [PDIP]
(N-28)
Dimensions shown in inches and (millimeters)
1.565 (39.7)
1.380 (35.1)
28
1
15
14
0.580 (14.73)
0.485 (12.32)
0.100 (2.54)
BSC
0.625 (15.87)
0.600 (15.24)
0.195 (4.95)
0.125 (3.18)
0.015 (0.39)
MIN
0.250 (6.35)
MAX
0.200 (5.05)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.70 (1.77)
0.30 (0.77)
0.022 (0.558)
0.014 (0.356)
COMPLIANT TO JEDEC STANDARDS MS-011AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. F
–11–
AD7824/AD7828
OUTLINE DIMENSIONS
24-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-24)
Dimensions shown in millimeters and (inches)
15.60 (0.6142)
15.20 (0.5984)
24
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
؋
45؇ 0.30 (0.0118)
0.10 (0.0039)
8؇
0؇
SEATING
PLANE
1.27 (0.0500) 0.51 (0.020)
1.27 (0.0500)
0.40 (0.0157)
0.32 (0.0126)
0.23 (0.0091)
COPLANARITY
0.10
BSC
0.33 (0.013)
COMPLIANT TO JEDEC STANDARDS MS-013AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-28)
Dimensions shown in millimeters and (inches)
18.10 (0.7126)
17.70 (0.6969)
28
1
15
14
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
؋
45؇ 0.30 (0.0118)
0.10 (0.0039)
8؇
0؇
1.27 (0.0500) 0.51 (0.0201) SEATING
1.27 (0.0500)
0.40 (0.0157)
0.32 (0.0126)
0.23 (0.0091)
COPLANARITY
0.10
PLANE
BSC
0.33 (0.0130)
COMPLIANT TO JEDEC STANDARDS MS-013AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–12–
REV. F
AD7824/AD7828
OUTLINE DIMENSIONS
24-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]
(Q-24)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
MAX
0.005 (0.13)
MIN
0.310 (7.87)
0.220 (5.59)
24
13
12
PIN 1
1
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
MAX
1.280 (32.51) MAX
0.150 (3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
0
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
0.100 (2.54)
MAX
0.005 (0.13)
MIN
28
15
14
0.610 (15.49)
0.500 (12.70)
PIN 1
1
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
0
0.100
(2.54)
BSC
0.070 (1.78) SEATING
PLANE
0.030 (0.76)
0.026 (0.66)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Terminal Ceramic Leaded Chip Carrier [LCC]
(E-28A)
Dimensions shown in inches and (millimeters)
0.300 (7.62)
REF
0.100 (2.54)
0.064 (1.63)
0.075
(1.91)
REF
0.020 (0.51)
MIN
19
25
0.028 (0.71)
0.022 (0.56)
18
26
28
0.05 (1.27)
BSC
0.458
0.458 (11.63)
0.442 (11.23)
(11.63)
MAX
SQ
BOTTOM
VIEW
1
SQ
0.15 (3.81)
REF
0.075 (1.91)
REF
12
4
11
5
0.095 (2.41)
0.075 (1.90)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. F
–13–
AD7824/AD7828
OUTLINE DIMENSIONS
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
10.50
10.20
9.90
28
15
5.60
5.30
5.00
8.20
7.80
7.40
14
1
1.85
1.75
1.65
0.10
COPLANARITY
2.00 MAX
0.25
0.09
8؇
4؇
0؇
0.95
0.75
0.55
0.38
0.22
0.65
BSC
0.05
MIN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AH
28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28A)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.020 (0.51)
0.042 (1.07)
MIN
4
5
26
25
0.048 (1.22)
0.042 (1.07)
0.021 (0.53)
0.013 (0.33)
BOTTOM
VIEW
0.430 (10.9)
0.390 (9.9)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
(PINS UP)
0.032 (0.81)
0.026 (0.66)
11
12
19
18
0.040 (1.02)
0.025 (0.64)
0.456 (11.582)
0.450 (11.430)
SQ
0.120 (3.05)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
COMPLIANTTO JEDEC STANDARDS MO-047AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–14–
REV. F
AD7824/AD7828
Revision History
Location
Page
1/03—Data Sheet changed from REV. E to REV. F.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to DIP/SOIC/SSOP, LCCC, AND PLCC Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Circuit Information Basic Description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Input Current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4/02—Data Sheet changed from REV. D to REV. E.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
REV. F
–15–
–16–
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