5962-87700012A [ADI]
CMOS 8-Bit Buffered Multiplying DAC; CMOS 8位缓冲乘法DAC型号: | 5962-87700012A |
厂家: | ADI |
描述: | CMOS 8-Bit Buffered Multiplying DAC |
文件: | 总8页 (文件大小:164K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CMOS
a
8-Bit Buffered Multiplying DAC
AD7524
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Microprocessor Com patible (6800, 8085, Z80, Etc.)
TTL/ CMOS Com patible Inputs
On-Chip Data Latches
Endpoint Linearity
Low Pow er Consum ption
Monotonicity Guaranteed (Full Tem perature Range)
Latch Free (No Protection Schottky Required)
APPLICATIONS
Microprocessor Controlled Gain Circuits
Microprocessor Controlled Attenuator Circuits
Microprocessor Controlled Function Generation
Precision AGC Circuits
Bus Structured Instrum ents
GENERAL D ESCRIP TIO N
T he AD7524 is a low cost, 8-bit monolithic CMOS DAC
designed for direct interface to most microprocessors.
O RD ERING GUID E
Basically an 8-bit DAC with input latches, the AD7524’s load
cycle is similar to the “write” cycle of a random access
memory. Using an advanced thin-film on CMOS fabrication
process, the AD7524 provides accuracy to 1/8 LSB with a typi-
cal power dissipation of less than 10 milliwatts.
Tem perature
Range
Nonlinearity
P ackage
Model1
(VD D = +15 V) O ption2
AD7524JN
–40°C to +85°C
AD7524KN –40°C to +85°C
±1/2 LSB
±1/4 LSB
±1/8 LSB
±1/2 LSB
±1/4 LSB
±1/8 LSB
±1/2 LSB
±1/2 LSB
±1/4 LSB
±1/8 LSB
±1/2 LSB
±1/4 LSB
±1/8 LSB
±1/2 LSB
±1/4 LSB
±1/8 LSB
N-16
N-16
N-16
P-20A
P-20A
P-20A
R-16A
Q-16
Q-16
Q-16
Q-16
Q-16
AD7524LN
AD7524JP
AD7524KP
AD7524LP
AD7524JR
AD7524AQ
AD7524BQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
A newly improved design eliminates the protection Schottky
previously required and guarantees T T L compatibility when
using a +5 V supply. Loading speed has been increased for
compatibility with most microprocessors.
Featuring operation from +5 V to +15 V, the AD7524 inter-
faces directly to most microprocessor buses or output ports.
Excellent multiplying characteristics (2- or 4-quadrant) make
the AD7524 an ideal choice for many microprocessor con-
trolled gain setting and signal control applications.
AD7524CQ –40°C to +85°C
AD7524SQ –55°C to +125°C
AD7524T Q –55°C to +125°C
AD7524UQ –55°C to +125°C
Q-16
AD7524SE
AD7524T E
AD7524UE
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
E-20A
E-20A
E-20A
NOT ES
1T o order MIL-ST D-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD) see DESC drawing # 5962-87700.
2E = Leadless Ceramic Chip Carrier: N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +10 V, VOUT1 = VOUT2 = 0 V, unless otherwise noted)
REF
AD7524–SPECIFICATIONS
1
Lim it, TA = +25؇C
Lim it, T MIN, TMAX
P aram eter
VD D = +5 V VD D = +15 V VD D = 5 V
VD D = +15 V Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
8
8
Bits
Relative Accuracy
J, A, S Versions
K, B, T Versions
L, C, U Versions
Monotonicity
±1/2
±1/2
±1/2
±1/2
±1/4
±1/8
±1/2
±1/2
±1/2
±1/2
±1/4
±1/8
LSB max
LSB max
LSB max
Guaranteed Guaranteed Guaranteed Guaranteed
±2 1/2
±40
Gain Error2
±1 1/4
±10
±3 1/2
±40
±1 1/2
±10
LSB max
ppm/°C
Average Gain T C 3
Gain T C Measured from +25°C to
T MIN or from +25°C to T MAX
% FSR/% max ∆VDD = ±10%
DC Supply Rejection,3 ∆Gain/∆VDD
0.08
0.002
0.02
0.001
0.16
0.01
0.04
0.005
% FSR/% typ
Output Leakage Current
IOUT1 (Pin 1)
IOUT2 (Pin 2)
±50
±50
±50
±50
±400
±400
±200
±200
nA max
nA max
DB0–DB7 = 0 V; WR, CS = 0 V; VREF = ±10 V
DB0–DB7 = VDD; WR, CS = 0 V; VREF = ±10 V
DYNAMIC PERFORMANCE
Output Current Settling Time3
(to 1/2 LSB)
400
250
500
350
ns max
OUT1 Load = 100 Ω, CEXT = 13 pF; WR, CS =
0 V; DB0–DB7 = 0 V to VDD to 0 V.
AC Feedthrough3
at OUT1
at OUT2
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
% FSR max
% FSR max
VREF = ±10 V, 100 kHz Sine Wave; DB0–DB7 =
0 V; WR, CS = 0 V
REFERENCE INPUT
RIN (Pin 15 to GND)4
5
20
5
20
5
20
5
20
kΩ min
kΩ max
ANALOG OUTPUTS
Output Capacitance3
COUT1 (Pin 1)
120
30
30
120
30
30
120
30
30
120
30
30
pF max
pF max
pF max
pF max
DB0–DB7 = VDD; WR, CS = 0 V
DB0–DB7 = 0 V; WR, CS = 0 V
COUT2 (Pin 2)
COUT1 (Pin 1)
COUT2 (Pin 2)
120
120
120
120
DIGITAL INPUTS
Input HIGH Voltage Requirement
VIH
+2.4
+0.8
±1
+13.5
+1.5
±1
+2.4
+0.5
±10
+13.5
+1.5
±10
V min
Input LOW Voltage Requirement
VIL
V max
µA max
Input Current
IIN
VIN = 0 V or VDD
Input Capacitance3
DB0–DB7
WR, CS
5
20
5
20
5
20
5
20
pF max
pF max
VIN = 0 V
VIN = 0 V
SWITCHING CHARACTERISTICS
Chip Select to Write Setup Time5
tCS
See Timing Diagram
tWR = tCS
AD7524J, K, L, A, B, C
AD7524S, T, U
Chip Select to Write Hold Time
tCH
170
170
100
100
220
240
130
150
ns min
ns min
All Grades
0
0
0
0
ns min
Write Pulse Width
tWR
tCS ≥ tWR, tCH ≥ 0
AD7524J, K, L, A, B, C
AD7524S, T, U
Data Setup Time
tDS
170
170
100
100
220
240
130
150
ns min
ns min
AD7524J, K, L, A, B, C
AD7524S, T, U
Data Hold Time
tDH
135
135
60
60
170
170
80
100
ns min
ns min
All Grades
10
10
10
10
ns min
POWER SUPPLY
IDD
1
100
2
100
2
500
2
500
mA max
µA max
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
NOT ES
1T emperature ranges as follows: J, K, L versions: –40°C to +85°C
A, B, C versions: –40°C to +85°C
S, T , U versions: –55°C to +125°C
2Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = VREF
3Guaranteed not tested.
.
4DAC thin-film resistor temperature coefficient is approximately –300 ppm/°C.
5AC parameter, sample tested @ +25°C to ensure conformance to specification.
Specifications subject to change without notice
.
–2–
REV. B
AD7524
Power Dissipation (Any Package)
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C, unless otherwise noted)
T o +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating T emperature
Commercial (J, K, L) . . . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (A, B, C) . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T , U) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Digital Input Voltage to GND . . . . . . . . –0.3 V to VDD +0.3 V
OUT 1, OUT 2 to GND . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7524 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
with all 1s in the DAC after offset error has been adjusted out
and is expressed in LSBs. Gain Error is adjustable to zero with
an external potentiometer.
TERMINO LO GY
RELATIVE ACCURACY: A measure of the deviation from a
straight line through the end points of the DAC transfer function.
Normally expressed as a percentage of full scale range. For the
AD7524 DAC, this holds true over the entire VREF range.
FEED TH RO UGH ERRO R: Error caused by capacitive cou-
pling from VREF to output with all switches OFF.
RESO LUTIO N: Value of the LSB. For example, a unipolar con-
verter with n bits has a resolution of (2–n) (VREF). A bipolar con-
verter of n bits has a resolution of [2–(n–1)] [VREF]. Resolution in no
way implies linearity.
O UTP UT CAP ACITANCE: Capacity from OUT 1 and
OUT 2 terminals to ground.
O UTP UT LEAKAGE CURRENT: Current which appears
on OUT 1 terminal with all digital inputs LOW or on OUT 2
terminal when all inputs are HIGH. T his is an error current
which contributes an offset voltage at the amplifier output.
GAIN ERRO R: Gain Error is a measure of the output error be-
tween an ideal DAC and the actual device output. It is measured
P IN CO NFIGURATIO NS
P LCC
D IP , SO IC
LCCC
REV. B
–3–
AD7524
WRITE MO D E
CIRCUIT D ESCRIP TIO N
When CS and WR are both LOW, the AD7524 is in the
WRIT E mode, and the AD7524 analog output responds to data
activity at the DB0–DB7 data bus inputs. In this mode, the
AD7524 acts like a nonlatched input D/A converter.
CIRCUIT INFO RMATIO N
T he AD7524, an 8-bit multiplying D/A converter, consists of a
highly stable thin film R-2R ladder and eight N-channel current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
H O LD MO D E
When either CS or WR is HIGH, the AD7524 is in the HOLD
mode. T he AD7524 analog output holds the value correspond-
ing to the last digital input present at DB0–DB7 prior to WR or
CS assuming the HIGH state.
T he simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT 1 and OUT 2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
MO D E SELECTIO N TABLE
CS
WR
Mode
D AC Response
L
L
Write
DAC responds to data bus
(DB0–DB7) inputs.
H
X
X
H
Hold
Hold
Data bus (DB0–DB7) is
Locked Out:
DAC holds last data present
when WR or CS assumed
HIGH state.
L = Low State, H = High State, X = Don't Care.
WRITE CYCLE TIMING D IAGRAM
Figure 1. Functional Diagram
EQ UIVALENT CIRCUIT ANALYSIS
T he equivalent circuit for all digital inputs LOW is shown in
Figures 2. In Figure 2 with all digital inputs LOW, the refer-
ence current is switched to OUT 2. T he current source ILEAKAGE
is composed of surface and junction leakages to the substrate
1
while the
current source represents a constant 1-bit cur-
256
rent drain through the termination resistor on the R-2R ladder.
T he “ON” capacitance of the output N-channel switches is
120 pF, as shown on the OUT 2 terminal. T he “OFF” switch
capacitance is 30 pF, as shown on the OUT 1 terminal. Analysis
of the circuit for all digital inputs high is similar to Figure 2
however, the “ON” switches are now on terminal OUT 1, hence
the 120 pF appears at that terminal.
Figure 2. AD7524 DAC Equivalent Circuit—All Digital
Inputs Low
INTERFACE LO GIC INFO RMATIO N
MO D E SELECTIO N
AD7524 mode selection is controlled by the CS and WR inputs.
Figure 3. Supply Current vs. Logic Level
T ypical plots of supply current, IDD, versus logic input voltage,
IN, for VDD = +5 V and VDD = +15 V are shown above.
V
–4–
REV. B
AD7524
ANALO G CIRCUIT CO NNECTIO NS
AD7524
AD7524
Figure 5. Bipolar (4-Quadrant) Operation
Figure 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
Table II. Bipolar (O ffset Binary) Code Table
Table I. Unipolar Binary Code Table
D igital Input
D igital Input
MSB LSB
Analog O utput
MSB
LSB
Analog O utput
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
+VREF (127/128)
+VREF (1/128 )
0
–VREF (1/128)
–VREF (127/128)
–VREF (128/128)
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
–VREF (255/256)
–VREF (129/256)
–VREF (128/256) = –VREF/2
–VREF (127/256)
–VREF (1/256)
–VREF (0/256) = 0
Note: 1 LSB = (2–7)(VREF) = 1/128 (VREF
)
Note: 1 LSB = (2–8)(VREF) = 1/256 (VREF
)
MICRO P RO CESSO R INTERFACE
Figure 6. AD7524/8085A Interface
Figure 7. AD7524/MC6800 Interface
REV. B
–5–
AD7524
P O WER GENERATIO N
Figure 8.
–6–
REV. B
AD7524
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Term inal Ceram ic Leadless Chip Carrier
(E-20A)
20-Lead P lastic Leadless Chip Carrier (P LCC)
(P -20A)
0.200 (5.08)
BSC
0.180 (4.57)
0.075
(1.91)
REF
0.165 (4.19)
0.100 (2.54)
0.064 (1.63)
0.048 (1.21)
0.042 (1.07)
0.100 (2.54) BSC
0.015 (0.38)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.095 (2.41)
0.075 (1.90)
0.048 (1.21)
0.042 (1.07)
3
MIN
19
3
19
20
18
4
0.021 (0.53)
0.013 (0.33)
0.028 (0.71)
4
8
18
PIN 1
0.358
1
0.050
(1.27)
BSC
0.358 (9.09)
IDENTIFIER
0.011 (0.28)
0.330 (8.38)
0.290 (7.37)
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.342 (8.69)
SQ
0.007 (0.18)
R TYP
0.075 (1.91)
REF
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
0.050 (1.27)
BSC
14
13
8
14
13
9
9
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
45° TYP
0.356 (9.04)
0.350 (8.89)
SQ
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
0.110 (2.79)
0.085 (2.16)
0.395 (10.02)
0.385 (9.78)
SQ
16-Lead P lastic D IP (Narrow)
(N-16)
16-Lead Cerdip
(Q-16)
0.840 (21.33)
0.745 (18.93)
0.005 (0.13) MIN
0.080 (2.03) MAX
9
16
16
1
9
0.310 (7.87)
0.280 (7.11)
0.220 (5.59)
0.240 (6.10)
8
1
8
0.325 (8.25)
0.320 (8.13)
0.290 (7.37)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.210 (5.33)
MAX
0.200 (5.08)
MAX
0.130
(3.30)
MIN
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.070 (1.77) SEATING
0.100
(2.54)
BSC
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.022 (0.558)
0.014 (0.356)
0.008 (0.204)
15°
0°
PLANE
0.045 (1.15)
16-Lead Narrow-Body (SO IC)
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.2550 (6.20)
0.2284 (5.80)
0.1497 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. B
–7–
–8–
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