VME64 [ACTEL]
VME64 Slave Controller; VME64从控制器
| 型号： | VME64 |
| 厂家： | 
Actel Corporation |
| 描述： | VME64 Slave Controller |
| 文件： | 总2页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Optimized for
VME64 Slave Controller
Description
Features
The VMEbus was first standardized in 1981 and is still in wide use. With the
advances in integration technologies, custom integrated VME controllers open the
door for smaller and cheaper systems. Inicore offers a wide range of different VME
slave controllers. Each one optimized for a certain application. The difference lies
mainly in the address and data bus width and the supported data modes.
• ANSI/VITA 1-1994
compliant
• VME slave controller
• Data modes: D8, D16, D32
The VME slave controller shields all the complexity of the asynchronous VMEbus
and provides an easy-to-use, synchronous parallel user side interface towards
custom logic. A built-in interrupter handles all local interrupt requests and
acknowledgments.
• Address modes: A16, A24,
D32
• Supports read, write, read-
modify-write, D32-BLT and
MBLT cycles
INTCmod
TIMERmod
GPIOmod
UARTmod
Bus Bridge
• Configurable D8, D16 or
D32 interrupter
• Fully synchronous user side
interface
• User selectable wait-states
• Synchronous design
User Decode
VMEchip
Figure 1: Sample application
Applications
The figure above illustrates a typical application where several peripheral
functions together with the VME slave core as well as a bus bridge are integrated
into one FPGA.
• Industrial control
• Military
Supported modes
• Aerospace
• Telecom
•
•
•
•
Data modes: D8, D16, D32
Address modes: A16, A24, A32
• Medical
Access modes: Read, write, read-modify-write, D32-BLT, MBLT
Interrupter: D8, D16, D32, RORA, ROAK
Sample Utilization and Performance Table Optimized for Actel Devices
Family
Device
- (speed grade)
APA600
Utilization
c-mod
Performance
s-mod
Total
3%
[MHz]
43
Tiles
RAM
ProASIC PLUS
Axcelerator
SXA
729
AX500-3
225
225
223
354
355
334
7%
101
74
SX72A-3
10%
10%
RTSX72S-1 MIL
RTSX
47
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
Page 1/2
About Inicore
v m e _ a d d r _ i n [ 3 1 : 1 ]
v m e _ a d d r _ o u t [ 3 1 : 1 ]
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v m e _ a d d r _ d ir
u s e r _ a d d r [ 3 1 :2 ]
u s e r _ a m [ 5 :0 ]
u s e r _ a c c _ r e q
FPGA and ASIC Design
Easy-to-use IP Cores
u s e r _ a c c _ r d y
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u s e r _ r w n
v m e _ a m [ 5 :0 ]
v m e _ d a t a _ i n [ 3 1 : 0 ]
v m e _ d a t a _ o u t [ 3 1 : 0 ]
v m e _ d a t a _ i n t _ d r v _ n
v m e _ d a t a _ d r v _ n
v m e _ d a t a _ d ir
u s e r _ b y t e _ v a li d [ 3 : 0 ]
System-on-Chip Solutions
Consulting Services
v m e _ d s 0 _ n
u s e r _ ia c k
u s e r _ ir e q
v m e _ d s 1 _ n
u s e r _ il e v [ 2 : 0 ]
u s e r _ iv e c [ 3 1 :0 ]
v m e _ lw o r d _ i n _ n
v m e _ lw o r d _ o u t _ n
v m e _ a s _ n
ASIC to FPGA Migration
Obsolete ASIC Replacements
v m e _ w r it e _ n
v m e _ d t a c k _ n
in t _ u s e r _ a m [ 5 :0 ]
in t _ u s e r _ a d d r [ 3 1 : 1 ]
u s e r _ a c c e s s _ e b l
v m e _ b e r r _ n
v m e _ ia c k _ n
Inicore is an experienced
system design house providing
FPGA / ASIC and SoC design
services. The company's
expertise in architecture,
intellectual property,
methodology and tool handling
provides a complete design
environment that helps
customers shorten their design
cycle and speed time to market.
Our offering covers feasibility
study, concept analysis,
architecture definition, code
generation and implementation.
When ready, we deliver you a
FPGA or take your design to an
ASIC provider, whatever is
more suitable for your unique
solution.
v m e _ ia c k _ i n _ n
v m e _ ia c k _ o u t _ n
v m e _ ir q _ n [ 6 :0 ]
u s e r _ a c c e s s _ e b l _ m b lt
r e s e t _ n
c l k _ s y s
V M E S la v e
Figure 2: Symbol
Interfaces
Pin Name
Global Signals
clk
Type
Description
Pin Name
Type
Description
vme_iack_in_n
in
Interrupt acknowledge
chain in
in
in
System clock
vme_iack_out_n
out Interrupt acknowledge
chain out
reset_n
Asynchronous system
reset, active low
vme_irq_n[6:0]
User Side Bus
user_addr[31:2]
user_am[5:0]
user_acc_req
user_acc_rdy
out Interrupt request
VME Bus
vme_addr_in[31:1]
vme_addr_out[31:1]
in
Address bus input
out Address bus
out Address bus output
out Address modifier code
out Data access request
vme_addr_int_drv_n out Internal i/o driver enable
vme_addr_drv_n
out External address bus
driver enable
in
Data access request
ready
vme_addr_dir
out External address bus
driver direction
Deliverables
user_data_rd[31:0]
user_data_wr[31:0]
user_rwn
in
Data read bus
out Data write bus
vme_am[5:0]
in
in
Address modifier code
Data bus input
The core is available as Actel
optimized netlist or as RTL
version.
out Data read or write
access
vme_data_in[31:0]
vme_data_out [31:0] out Data bus output
user_byte_valid
[3:0]
out Data byte valid
vme_data_int_drv_n
vme_data_drv_n
out Internal i/o driver enable
Actel Optimized Netlist:
out External data bus driver
enable
User Decode
• Netlist for target FPGA, EDIF,
Verilog and VHDL format
• User Guide
int_user_addr[31:1]
int_user_am[5:0]
user_access_ebl
out Address bus
vme_data_dir
out External data bus driver
direction
out Address modifier code
vme_ds0_n
in
in
in
Data strobe 0
in
in
Valid user access
RTL Source Code:
vme_ds1_n
Data strobe 1
user_access_ebl_
mblt
Valid user access mblt
mode
vme_lword_in_n
vme_lword_out_n
vme_as_n
Long word indicator, in
• VHDL or Verilog source code
• Funtional verification
testbench
• Synthesis script
• Timing constraints
• User guide
Interrupt
out Long word indicator, out
user_iack
out Interrupt acknowledge
in
in
Address strobe
user_ireq
in
in
in
Interrupt request
Interrupt vector
vme_write_n
vme_dtack_n
vme_berr_n
vme_iack_n
Read write not indicator
user_ivec[31:0]
user_ilevel[2:0]
out Data acknowledge
Interrupt request level
in
in
Bus error
Interrupt acknowledge
© 2003, Inicore Inc, All rights reserved.
All brands or product names mentioned are
the property of their respective holders.
51415.71.02 Sept/2003
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
Page 2/2
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