RH1020-CQ84V [ACTEL]

Field Programmable Gate Array, 547 CLBs, 2000 Gates, 50MHz, 547-Cell, CMOS, CQFP84, CERAMIC, QFP-84;


型号：	RH1020-CQ84V
厂家：	Actel Corporation
描述：	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 50MHz, 547-Cell, CMOS, CQFP84, CERAMIC, QFP-84 时钟栅可编程逻辑
文件：	总30页 (文件大小：236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v3.1

Radiation-Hardened FPGAs

•

Significantly Greater Densities than Discrete Logic

Devices

Replaces up to 200 TTL Packages

Features

•

Guaranteed Total Dose Radiation Capability

Low Single Event Upset Susceptibility

High Dose Rate Survivability

Latch-Up Immunity Guaranteed

QML Qualified Devices

Commercial Devices Available for Prototyping and

Pre-Production Requirements

•

Design Library with over 500 Macro Functions

Single-Module Sequential Functions

Wide-Input Combinatorial Functions

Up to Two High-Speed, Low-Skew Clock Networks

Two In-Circuit Diagnostic Probe Pins Support

Speed Analysis to 50 MHz

Non-Volatile, User Programmable Devices

Fabricated in 0.8 µ Epitaxial Bulk CMOS Process

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer

•

Gate Capacities of 2,000 and 8,000 Gate Array

Gates

More Design Flexibility than Custom ASICs

•

Product Family Profile

Device

RH1020

RH1280

Capacity

System Gates

3,000

2,000

6,000

12,000

8,000

20,000

200

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

Logic Modules

S-Modules

C-Modules

547

1,232

624

608

Flip-Flops (Maximum)

273

998

Routing Resources

Horizontal Tracks/Channel

Vertical Tracks/Channel

PLICE Antifuse Elements

186,000

750,000

User I/Os (Maximum)

140

Packages (by Pin Count)

Ceramic Quad Flat Pack (CQFP)

172

April 2005

See the Actel website for the latest version of the datasheet.

Radiation-Hardened FPGAs

Ordering Information

RH1280 – CQ

172

Application

V = QML Qualified

Package Lead Count

Package Type

CQ = Ceramic Quad Flat Pack

Part Number

RH1280 = 8000 Gates

RH1020 = 2000 Gates

Figure 1-1 • Ordering Information

Ceramic Device Resources

CQFP 84-Pin

CQFP 172-Pin

RH1020

RH1280

–

140

v3.1

Radiation-Hardened FPGAs

Table of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

QML Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

RadHard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

The RH1020 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

QML Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Radiation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Timing Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

172-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

v3.1

iii

Radiation-Hardened FPGAs

line by expensive and destructive testing. QML also

ensures continuous process improvement, a focus on

enhanced quality and reliability, and shortened product

introduction and cycle time.

General Description

Actel Corporation, the leader in antifuse-based field

programmable gate arrays (FPGAs), offers fully

guaranteed RadHard versions of the A1280 and A1020

devices with gate densities of 8,000 and 2,000 gate array

gates, respectively.

Actel Corporation has also achieved QML certification.

All RH1020 and RH1280 devices will be shipped with a

"QML" marking, signifying that the devices and

processes have been reviewed and approved by DESC for

QML status.

The RH1020 and RH1280 devices are processed in 0.8 µ,

two-level metal epitaxial bulk CMOS technology. The

devices are based on the Actel patented channeled array

architecture, and employ Actel’s PLICE antifuse

technology. This architecture offers gate array flexibility,

high performance, and fast design implementation

through user programming.

Development Tool Support

The RadHard family of FPGAs is fully supported by both

Actel Libero^®Integrated Design Environment (IDE) and

Designer FPGA development software. Actel Libero IDE is

Actel devices also provide unique on-chip diagnostic

probe capabilities, allowing convenient testing and

debugging. On-chip clock drivers with hard-wired

distribution networks provide efficient clock distribution

design management environment, seamlessly

integrating design tools while guiding the user through

the design flow, managing all design and log files, and

passing necessary design data among tools. Additionally,

Libero IDE allows users to integrate both schematic and

HDL synthesis into a single flow and verify the entire

design in a single environment. Libero IDE includes

Synplify^®for Actel from Synplicity^®, ViewDraw^®for

Actel from Mentor Graphics^®, ModelSim^®HDL Simulator

from Mentor Graphics, WaveFormer Lite™ from

SynaptiCAD™, and Designer software from Actel. Refer

to the Libero IDE flow diagram for more information

(located on the Actel website).

with minimum skew.

security fuse may be

programmed to disable all further programming, and to

protect the design from being copied or reverse

engineered.

The RH1020 and RH1280 are available as fully qualified

QML devices. Unlike traditional ASIC devices, the design

does not have to be finalized six months prior to

receiving the devices. Customers can make design

modifications and program new devices within hours.

These devices are fabricated, assembled, and tested at

the Lockheed-Martin Space and Electronics facility in

Manassas, Virginia on an optimized radiation-hardened

CMOS process.

Actel Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

timing-driven place-and-route, and

world-class

integrated static timing analyzer and constraints editor.

With the Designer software, a user can select and lock

package pins while only minimally impacting the results

of place-and-route. Additionally, the back-annotation

flow is compatible with all the major simulators and the

simulation results can be cross-probed with Silicon

Explorer II, Actel’s integrated verification and logic

analysis tool. Another tool included in the Designer

software is the ACTgen macro builder, which easily

creates popular and commonly used logic functions for

implementation in your schematic or HDL design. Actel's

Designer software is compatible with the most popular

FPGA design entry and verification tools from companies

such as Mentor Graphics, Synplicity, Synopsys, and

Cadence Design Systems. The Designer software is

available for both the Windows and UNIX operating

systems.

Radiation Survivability

In addition to all electrical limits, all radiation

characteristics are tested and guaranteed, reducing

overall system-level risks. With total dose hardness of

300 krad (Si), latch-up immunity, and a tested single

event upset (SEU) of less than 1x10^–6errors/bit-day, these

are the only RadHard, high-density field programmable

products available today.

QML Qualification

Lockheed Martin Space and Electronics in Manassas,

Virginia has achieved full QML certification, assuring that

quality management, procedures, processes, and controls

are in place from wafer fabrication through final test.

QML qualification means that quality is built into the

production process rather than verified at the end of the

v3.1

1-1

Radiation-Hardened FPGAs

where

Applications

S0 = A0 × B0

S1 = A1 + B1

The RH1020 and RH1280 devices are targeted for use in

military and space applications subject to radiation

effects.

1. Accumulated Total Dose Effects

With the significant increase in Earth-orbiting

satellite launches and the ever-decreasing time-to-

launch design cycles, the RH1020 and RH1280 devices

offer the best combination of total dose radiation

hardness and quick design implementation necessary

for this increasingly competitive industry. In addition,

the high total dose capability allows the use of these

devices for deep space probes, which encounter other

planetary bodies where the total dose radiation

effects are more pronounced.

D00

D01

D10

D11

Figure 1-1 • C-Module Implementation

2. Single Event Effects (SEE)

The S-module, shown in Figure 1-2 on page 1-3, is

designed to implement high-speed sequential functions

within a single logic module. The S-module implements

the same combinatorial logic function as the C-module

while adding a sequential element. The sequential

element can be configured as either a D-flip-flop or a

transparent latch. To increase flexibility, the S-module

combinatorial logic.

Many space applications are more concerned with the

number of single event upsets and potential for latch-

up in space. The RH1020 and RH1280 devices are

latch-up immune, guaranteeing that no latch-up

failures will occur. Single event upsets can occur in

these devices as with all semiconductor products, but

the rate of upset is low, as shown in Table 1-2 on

page 1-6.

3. High Dose Rate Survivability

Flip-flops can also be created using two C-modules. The

single event upset (SEU) characteristics differ between an

S-module flip-flop and a flip-flop created using two

C-modules. For details see the Radiation Specifications

table on Table 1-2 on page 1-6 and the Design

Techniques for RadHard Field Programmable Gate Arrays

application note.

An additional radiation concern is high dose rate

survivability. Solar flares and sudden nuclear events

can cause immediate high levels of radiation. The

RadHard devices are appropriate for use in these

types of applications, including missile systems,

ground-based communication systems, and orbiting

satellites.

The RH1020 Logic Module

The RH1020 logic module is an 8-input, one-output logic

circuit chosen for the wide range of functions it

implements and for its efficient use of interconnect

routing resources (Figure 1-3 on page 1-3).

RadHard Architecture

The RH1020 and RH1280 architecture is composed of

fine-grained building blocks that produce fast and

efficient logic designs. All the devices are composed of

logic modules, routing resources, clock networks, and I/O

modules, which are the building blocks for fast logic

designs.

The logic module can implement the four basic logic

functions (NAND, AND, OR, and NOR) in gates of two,

three, or four inputs. Each function may have many

versions, with different combinations of active-low

inputs. The logic module can also implement a variety of

D-latches, exclusivity functions, AND-ORs, and OR-ANDs.

No dedicated hardwired latches or flip-flops are required

in the array, since latches and flip-flops may be

constructed from logic modules wherever needed in the

application.

Logic Modules

RH1280 devices contain two types of logic modules,

combinatorial (C-modules) and sequential (S-modules).

RH1020 devices contain only C-modules.

The C-module, shown in Figure 1-1, implements the

following function:

Y = !S1 × !S0 × D00 + !S1 × S0 × D01 + S1 × !S0

× D10 + S1 × S0 × D11

EQ 1-1

1-2

v3.1

Radiation-Hardened FPGAs

D00

D01

D00

D01

OUT

D10

D11

D10

D11

GATE

CLR

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D00

D01

OUT

D10

D11

GATE

CLR

Up to 8-Input Function (same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 1-2 • S-Module Implementation

From Array

To Array

PAD

G/CLK*

Note: *Can be configured as a Latch or D Flip-Flop (using

C-Module).

Figure 1-3 • RH1020 Logic Module

Figure 1-4 • I/O Module

I/O Modules

I/O modules provide the interface between the device

pins and the logic array. A variety of user functions,

determined by a library macro selection, can be

implemented in the I/O modules (refer to the Antifuse

Macro Library Guide for more information). I/O modules

contain a tristate buffer, and input and output latches

which can be configured for input, output, or

bidirectional pins (Figure 1-4).

v3.1

1-3

Radiation-Hardened FPGAs

RadHard devices contain flexible I/O structures in that each

output pin has a dedicated output enable control. The I/O

module can be used to latch input and/or output data,

providing a fast set-up time. In addition, the Actel Designer

software tools can build a D-flip-flop, using a C-module, to

Antifuse Structures

An antifuse is a "normally open" structure as opposed to

the normally closed fuse structure used in PROMs or

PALs. The use of antifuses to implement a programmable

logic device results in highly testable structures, as well

as efficient programming algorithms. The structure is

highly testable because there are no pre-existing

connections, enabling temporary connections to be

made using pass transistors. These temporary

connections can isolate individual antifuses to be

programmed, as well as isolate individual circuit

structures to be tested. This can be done both before and

after programming. For example, all metal tracks can be

tested for continuity and shorts between adjacent tracks,

and the functionality of all logic modules can be verified.

Actel Designer development tools provide a design

library of I/O macros that can implement all I/O

configurations supported by the RadHard FPGAs.

Routing Structure

The RadHard device architecture uses vertical and

horizontal routing tracks to interconnect the various

logic and I/O modules. These routing tracks are metal

interconnects that may either be of continuous length or

broken into segments. Varying segment lengths allow

over 90 percent of the circuit interconnects to be made

with only two antifuse connections. Segments can be

joined together at the ends, using antifuses to increase

their length up to the full length of the track. All

interconnects can be accomplished with a maximum of

four antifuses.

Logic

Modules

Segmented

Horizontal

Routing

Tracks

Antifuses

Horizontal Routing

Horizontal channels are located between the rows of

modules, and are composed of several routing tracks.

The horizontal routing tracks within the channel are

divided into one or more segments. The minimum

horizontal segment length is the width of a module-pair,

and the maximum horizontal segment length is the full

length of the channel. Any segment that spans more

than one-third the row length is considered a long

horizontal segment. A typical channel is shown in

Figure 1-5. Non-dedicated horizontal routing tracks are

used to route signal nets. Dedicated routing tracks are

used for the global clock networks and for power and

ground tie-off tracks.

Vertical Routing Tracks

Figure 1-5 • Routing Structure

Related Documents

Application Notes

Design Techniques for RadHard Field Programmable

Gate Arrays

Vertical Routing

Another set of routing tracks run vertically through the

module. There are three types of vertical tracks, input,

output, and long, that can be divided into one or more

segments. Each segment in an input track is dedicated to

the input of a particular module. Each segment in an

output track is dedicated to the output of a particular

module. Long segments are uncommitted and can be

assigned during routing. Each output segment spans

four channels (two above and two below), except near

the top and bottom of the array where edge effects

occur. Long vertical tracks contain either one or two

segments. An example of vertical routing tracks and

segments is shown in Figure 1-5.

http://www.actel.com/documents/Des_Tech_RH_AN.pdf

Analysis of SDI/DCLK Issue for RH1020 and RT1020

http://www.actel.com/documents/SDI_DCLK_AN.pdf

Simultaneously Switching Noise and Signal Integrity

http://www.actel.com/documents/SSN_AN.pdf

User’s Guides

Antifuse Macro Library Guide

http://www.actel.com/documents/libguide_UG.pdf

1-4

v3.1

Radiation-Hardened FPGAs

QML Flow

Test Inspection

Method

LMFS Procedure MAN-STC-Q014

Wafer Lot Acceptance

Serialization

Required – 100%

Die Adhesion Test

2027 (Stud Pull)

Bond Pull Test

2011 (Wirebond)

Internal Visual

2010, Condition A

1010, Condition C, 50 Cycles

Temperature Cycle

Constant Acceleration

Particle Impact Noise Detection (PIND)

X-Ray Radiography

2001, Condition D or E, Y1 Orientation Only

2020, Condition A

2012

Pre Burn-In Electrical Parameters (T0)

Dynamic Burn-In

Per Device Specification

1015, 240 Hour Minimum, 125°C

Per Device Specification

LMFS Procedure MAN-STC-Q016

1015, 144 Hour Minimum, 125°C Minimum

Per Device Specification

LMFS Procedure MAN-STC-Q016

1014

Interim Electrical Parameters (T1)

Percent Defective Allowable (PDA)

Static Burn-In

Final Electrical Parameters (T2)

Percent Defective Allowable (PDA)

Seal – Fine/Gross Leak

External Visual (as required)

2009

Absolute Maximum Ratings

Table 1-1 • Free Air Temperature Range

Symbol

V_CC

Parameter

DC Supply Voltage^2,3,4,5

Limits

–0.5 to +7.0

–0.5 to V_CC+0.5

Units

V_I

Input Voltage

V_O

Output Voltage

I_IO

I/O Source/Sink Current⁶

Storage Temperature²

°C

T_STG

Notes:

–65 to +150

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

2. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated

outside the recommended operating conditions.

3. V_PP= V_CC, except during device operation.

4. V_SV= V_CC, except during device operation.

5. V_KS= GND , except during device operation.

6. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than V_CC

0.5 V or less than GND – 0.5V, the internal protection diode will be forward-biased and can draw excessive current.

v3.1

1-5

Radiation-Hardened FPGAs

Recommended Operating Conditions

Parameter

Military

–55 to +125

Units

°C

Temperature Range¹

Power Supply Tolerance²

%V_CC

Notes:

1. Case temperature (T_C) is used.

2. All power supplies must be in the recommended operating range.

Electrical Specifications

Limits

Group A

Symbol

Test Conditions

(I_OH= –4 mA)

(I_OL= 4 mA)

Subgroups

1, 2, 3

—

Min.

Max.

Units

V_OH

3.7

V_OL

V_IH

V_IL

0.4

V_CC+ 0.3

0.8

2.2

–0.3

Input Transition Time t_R, t_F

C_IO, I/O Capacitance²

I_IH, I_IL

500

µA

V_IN= V_CCor GND

V_CC= 5.5 V

1, 2, 3

–10

_OZL, I_OZH

V_OUT= V_CCor GND

V_CC= 5.5 V

1, 2, 3

µA

_CCStandby³

Notes:

1. Only one output tested at a time. V_CC= min.

2. Not tested, for information only.

3. All outputs unloaded. All inputs = V_CCor GND.

Radiation Specifications

Table 1-2 • Radiation Specifications^{1, 2}

Symbol

RTD

Characteristics

Total Dose

Conditions

Min.

Max.

Units

300 k

Rad (Si)

SEL

Single Event Latch-Up

–55°C ≤ T_case≤ 125°C

Fails/Device-Day

Upsets/Bit-Day

SEU1³

SEU2³

SEU3³

RNF

Single Event Upset for S-modules

Single Event Upset for C-modules

Single Event Fuse Rupture

Neutron Fluence

1E-6

1E-7

Upsets/Bit-Day

FIT (Fails/Device/1E9 Hrs)

N/cm²

>1 E+12

Notes:

1. Measured at room temperature unless otherwise stated.

2. Device electrical characteristics are guaranteed for post-irradiation levels at worst-case conditions.

3. 10% worst-case particle environment, geosynchronous orbit, 0.025" of aluminum shielding. Specification set using the CREME

code upset rate calculation method with a 2 µ epi thickness.

1-6

v3.1

Radiation-Hardened FPGAs

Package Thermal Characteristics

The device junction to case thermal characteristics is θ_jc,

and the junction to ambient air characteristics is θ_ja. The

thermal characteristics for θ_jaare listed with

two different air flow rates, as shown in Table 1-3.

Maximum junction temperature is 150°C.

A sample calculation of the maximum power dissipation

for an 84-pin ceramic quad flat pack at commercial

temperature is shown in EQ 1-2.

Max. Junction Temperature (°C) – Max. Commercial Temperature (°C)

150°C – 70°C

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------------------------------

= 2.0 W

θ_ja(°C/W)

40°C/W

EQ 1-2

Table 1-3 • Thermal Characteristics

θ_ja

1.0 m/s

2.5 m/s

Package Type

Pin Count

θ_jc

2.0

Still Air

40.0

200 ft. / min. 500 ft. / min.

Units

Ceramic Quad Flat Pack

33.0

23.1

30.0

21.0

°C/W

172

28.0

Note: θ_jcfor CQFP packages refers to the thermal resistance between the junction and the bottom of the package.

greater reduction in board-level power dissipation can

be achieved.

Power Dissipation

The power due to standby current is typically a small

component of the overall power. Standby power is

calculated below for military, worst case conditions.

General Power Equation

P = [I_CCstandby + I_CCactive] × V_CC+ I_OL× V_OL

N + I_OH× (V_CC– V_OH) × M

I_CC

V_CC

Power

25 mA 5.5 V 138 mW (max)

1 mA 5.5 V 5.5 mW (typ)

EQ 1-3

where

_CCstandby is the current flowing when no inputs or

outputs are changing.

_CCactive is the current flowing due to CMOS

switching.

_OL, I_OHare TTL sink/source currents.

_OL, V_OHare TTL level output voltages.

N equals the number of outputs driving TTL loads to

V_OL

M equals the number of outputs driving TTL loads to

V_OH

Active Power Components

Power dissipation in CMOS devices is usually dominated

by the active (dynamic) power dissipation. This

component is frequency-dependent and a function of

the logic and the external I/O. Active power dissipation

results from charging internal chip capacitances of the

interconnect, unprogrammed antifuses, module inputs,

and module outputs, plus external capacitance due to PC

board traces and load device inputs. An additional

component of the active power dissipation is the

totempole current in CMOS transistor pairs. The net

effect can be associated with an equivalent capacitance

that can be combined with frequency and voltage to

represent active power dissipation.

Accurate values for N and M are difficult to determine

because they depend on the family type, design details,

and on the system I/O. The power can be divided into

two components: static and active.

The power dissipated by a CMOS circuit can be expressed

by EQ 1-4:

Static Power Components

Actel FPGAs have small static power components that

result in lower power dissipation than PALs or PLDs. By

integrating multiple PALs/PLDs into one FPGA, an even

Power (uW) = C_EQ× V_CC× F

EQ 1-4

v3.1

1-7

Radiation-Hardened FPGAs

where

C_EQCR= Equivalent capacitance of routed array clock

in pF

C_EQ

V_CC

= Equivalent capacitance in pF

= Power supply in volts (V)

= Switching frequency in MHz

C_L

f_m

f_n

f_p

f_q1

f_q2

= Output lead capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

Equivalent Capacitance

Equivalent capacitance is calculated by measuring I_CC

active at a specified frequency and voltage for each

circuit component of interest. Measurements have been

= Average second routed array clock rate in

MHz (RH1280 only)

made over a range of frequencies at a fixed value of V_CC

Fixed Capacitance Values for Actel FPGAs

(pF)

Equivalent capacitance is frequency-independent so the

results may be used over a wide range of operating

conditions. Equivalent capacitance values follow.

Device Type

routed_Clk1

routed_Clk2

Values for Actel FPGAs

RH1020

RH1280

168

N/A

168

RH1020 RH1280

5.2

11.6

23.8

3.5

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

)

3.7

22.1

31.2

4.6

Determining Average Switching

Frequency

To determine the switching frequency for a design, you

must have a detailed understanding of the data input

values to the circuit. The following guidelines are meant

to represent worst-case scenarios, so they can be

generally used to predict the upper limits of power

dissipation. These guidelines are as follow:

)

To calculate the active power dissipated from the

complete design, the switching frequency of each part of

the logic must be known. EQ 1-5 shows a piece-wise

linear summation over all components.

Logic Modules (m)

Inputs Switching (n)

Outputs Switching (p)

= 80% of Modules

= # Inputs/4

Power = V_CC× [(m × C_{EQM ×}f_m)_modules+ (n × C_EQI

× f_n)_inputs+ (p × (C_EQO+ C_L) × f_p)_outputs+ 0.5 ×

= # Outputs/4

(q₁

C_EQCR× f_q1

)

+ (r₁× f_q1

)

+ 0.5

routed_Clk1

First Routed Array Clock Loads = 40% of

(q₁) Sequential

Modules

(q₂× C_EQCR× f_q2

)

+ (r₂×

routed_Clk2

f_q2

)

]

routed_Clk2

Second Routed Array Clock Loads = 40% of

EQ 1-5

(q₂) (RH1280 only)

Sequential

Modules

where

= Number of logic modules switching at f_m

= Number of input buffers switching at f_n

= Number of output buffers switching at f_p

Load Capacitance (C_L)

= 35 pF

Average Logic Module Switching = F/10

Rate (f_m)

q₁

= Number of clock loads on the first routed

array clock

= Number of clock loads on the second routed

array clock (RH1280 only)

= Fixed capacitance due to first routed array

clock

= Fixed capacitance due to second routed array

clock (RH1280 only)

Average Input Switching Rate = F/5

(f_n)

q₂

r₁

r₂

Average Output Switching Rate = F/10

(f_p)

Average First Routed Array Clock = F

Rate (f_q1

)

Average Second Routed Array = F/2

Clock Rate (f_q2) (RH1280 only)

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

1-8

v3.1

Radiation-Hardened FPGAs

Timing Models

Predicted

Routing

Delays

Input Delay

Internal Delays

Logic Module

Output Delay

I/O Module

IRD2 = 1.9 ns

INYL = 4.2 ns

DLH = 9.1 ns

IRD1 = 1.2 ns

RD1 = 1.2 ns

IRD4 = 4.2 ns

PD = 3.9 ns

RD2 = 1.9 ns

ENHZ = 13.5 ns

IRD8 = 8.9 ns

CO = 3.9 ns

RD4 = 4.2 ns

RD8 = 8.9 ns

ARRAY

CLOCK

FO = 128

CKH = 7.6 ns

MAX = 55 MHz

Figure 1-6 • RH1020 Timing Model

Input Delays

I/O Module

Output Delays

Internal Delays

Combinatorial

Logic Module

I/O Module

Predicted

Routing

Delays

= 2.3 ns

†

= 7.5 ns

INYL

IRD2

DLH = 8.7 ns

RD1 = 2.7 ns

RH2 = 3.4 ns

RD4 = 4.8 ns

RD8 = 9.0 ns

= 4.7 ns

I/O Module

DLH = 8.7 ns

Sequential

INH = 0.0 ns

INSU = 0.6 ns

INGL = 5.3 ns

Logic Module

Combin-

atorial

Logic

RD1 = 2.7 ns

ENHZ = 9.7 ns

included

in t

SUD

OUTH = 0.0 ns

OUTSU = 0.6 ns

GLH = 7.6 ns

= 0.7 ns

= 0.0 ns

= 4.7 ns

SUD

ARRAY

CLOCKS

FO = 384

CKH = 11.2 ns

MAX = 95 MHz

LCO = 17.7 ns (64 loads, pad-pad)

Note: † Input module predicted routing delay.

Figure 1-7 • RH1280 Timing Model

v3.1

1-9

Radiation-Hardened FPGAs

Parameter Measurement

Output Buffer Delays

PAD To AC Test Loads (shown below)

TRIBUFF

50% 50%

V_OH

50% 50%

V_OH

1.5V

90%

PAD

GND

1.5V

10%

DLH

DHL

ENZL

ENLZ

ENZH

ENHZ

Figure 1-8 • Output Buffer Delays

AC Test Loads

Load 1

Load 2

(Used to Measure Propagation Delay)

(Used to Measure Rising/Falling Edges)

V_CC

GND

To the Output Under Test

R to V_CCfor PLZ / PZL

35 pF

R to GND for PHZ / PZH

R = 1 k

To the Output Under Test

35 pF

Figure 1-9 • AC Test Loads

Input Buffer Delays

PA D

INBUF

S, A or B 50% 50%

50%

PLH

PHL

PAD

1.5V 1.5V

V_CC

50%

PHL

PLH

GND

INYL

INYH

Figure 1-11 • Module Delays

Figure 1-10 • Input Buffer Delays

Module Delays

1-10

v3.1

Radiation-Hardened FPGAs

Sequential Module Timing Characteristics

Flip-Flops and Latches

CLK

PRE

CLR

(Positive Edge Triggered)

SUD

WC LKA

G, C LK

WCLKI

SUENA

HENA

PRE, CLR

WASYN

Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.

Figure 1-12 • Flip-Flops and Latches

PA D

DATA

IBDL

CLK

PA D

CLKBUF

DATA

INH

INSU

H EXT

CLK

SU EXT

Figure 1-13 • Input Buffer Latches

v3.1

1-11

Radiation-Hardened FPGAs

PAD

OBDLHS

OUTSU

OUTH

Figure 1-14 • Output Buffer Latches

1-12

v3.1

Radiation-Hardened FPGAs

Timing Characteristics

Table 1-4 • RH1020 Timing Characteristics

(Worst-Case Military Conditions, V_CC= 4.5 V, T_J= 125°C, RTD = 300 krad (Si))

Description

Logic Module Propagation Delays

Parameter

Min.

Max.

Units

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

3.9

9.2

3.9

Dual Module Macros

Sequential Clk to Q

Latch G to Q

Flip-Flop (Latch) Reset to Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.2

1.9

2.8

4.2

8.9

Logic Module Sequential Timing ²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

7.5

0.0

7.5

0.0

9.2

19.2

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

f_MAX

Flip-Flop (Latch) Clock Frequency

MHz

Input Module Propagation Delays

t_INYH

Pad to Y High

4.2

t_INYL

Pad to Y Low

Input Module Predicted Routing Delays^{1, 3}

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.2

1.9

2.8

4.2

8.9

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.

3. Optimization techniques may further reduce delays by 0 to 4 ns.

4. The hold time for the DFME1A macro may be greater than 0 ns. Use the Designer v3.0 (or later) Timer to check the hold time for

this macro.

v3.1

1-13

Radiation-Hardened FPGAs

Table 1-5 • RH1020 Timing Characteristics

(Worst-Case Military Conditions, V_CC= 4.5 V, T_J= 125°C, RTD = 300 krad (Si))

Description

Global Clock Network

Parameter

Min.

Max.

Units

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to High

FO = 16

FO = 128

6.6

7.6

Input High to Low

FO = 16

FO = 128

8.7

9.5

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

FO = 16

FO = 128

8.8

9.2

FO = 16

FO = 128

1.6

2.4

FO = 16

FO = 128

1.6

2.5

Minimum Period

FO = 16

FO = 128

17.9

19.2

f_MAX

Maximum Frequency

FO = 16

FO = 128

MHz

TTL Output Module Timing¹

t_DLH

Data to Pad High

9.1

10.2

8.9

t_DHL

Data to Pad Low

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to High

Enable Pad Z to Low

Enable Pad High to Z

Enable Pad Low to Z

Delta Low to High

Delta High to Low

10.7

13.5

12.2

0.08

0.11

ns/pF

CMOS Output Module Timing¹

t_DLH

Data to Pad High

10.7

8.7

t_DHL

Data to Pad Low

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

Enable Pad Z to High

Enable Pad Z to Low

Enable Pad High to Z

Enable Pad Low to Z

Delta Low to High

Delta High to Low

8.1

11.2

13.5

12.2

0.14

0.08

ns/pF

d_THL

Notes:

1. Delays based on 35 pF loading.

2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.

1-14

v3.1

Radiation-Hardened FPGAs

Table 1-6 • RH1280 Timing Characteristics

(Worst-Case Military Conditions, V_CC= 4.5 V, T_J= 125°C, RTD = 300 krad (Si))

Parameter

Description

Min.

Max.

Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

4.7

Sequential Clk to Q

Latch G to Q

Flip-Flop (Latch) Reset to Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.7

3.4

4.1

4.8

9.0

Sequential Timing Characteristics^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.7

0.0

1.4

0.0

6.6

13.5

0.0

0.6

0.0

0.6

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

t_INH

Input Buffer Latch Hold

t_INSU

Input Buffer Latch Set-Up

t_OUTH

t_OUTSU

f_MAX

Notes:

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock Frequency

MHz

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the DirectTime Analyzer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal set-up (hold) time.

v3.1

1-15

Radiation-Hardened FPGAs

Table 1-7 • RH1280 Timing Characteristics

(Worst-Case Military Conditions, V_CC= 4.5 V, T_J= 125°C, RTD = 300 krad (Si))

Description

Input Module Propagation Delays

Parameter

Min.

Max.

Units

t_INYH

t_INYL

t_INGH

t_INGL

Pad to Y High

Pad to Y Low

G to Y High

G to Y Low

1.9

2.3

4.1

5.3

Input Module Predicted Routing Delays*

t_IRD1

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

6.8

7.5

t_IRD2

t_IRD3

8.2

t_IRD4

8.9

t_IRD8

11.7

Global Clock Network

t_CKH

Input Low to High

FO = 32

FO = 384

9.6

11.2

t_CKL

Input High to Low

FO = 32

9.6

FO = 384

11.2

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

FO = 32

FO = 384

5.8

6.2

FO = 32

FO = 384

5.8

6.2

FO = 32

FO = 384

1.1

Input Latch External Set-Up

Input Latch External Hold

Minimum Period

FO = 32

FO = 384

0.0

FO = 32

FO = 384

4.6

5.8

FO = 32

FO = 384

11.8

13.0

f_MAX

Maximum Frequency

FO = 32

FO = 384

105

MHz

Note: *Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route

timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may

further reduce delays by 0 to 4 ns.

1-16

v3.1

Radiation-Hardened FPGAs

Table 1-8 • RH1280 Timing Characteristics

(Worst-Case Military Conditions, V_CC= 4.5 V, T_J= 125°C, RTD = 300 krad (Si))

Parameter

Description Min.

Max.

Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

t_ACO

d_TLH

d_THL

Data to Pad High

6.8

7.6

Data to Pad Low

Enable Pad Z to High

6.8

Enable Pad Z to Low

7.6

Enable Pad High to Z

9.7

Enable Pad Low to Z

9.7

G to Pad High

7.6

G to Pad Low

8.9

I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading

Array Clock-Out (Pad-to-Pad), 64 Clock Loading

Capacitive Loading, Low to High

Capacitive Loading, High to Low

17.7

25.0

0.07

0.09

ns/pF

CMOS Output Module Timing¹

t_DLH

Data to Pad High

8.7

6.4

t_DHL

Data to Pad Low

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

Enable Pad Z to High

6.8

Enable Pad Z to Low

7.6

Enable Pad High to Z

9.7

Enable Pad Low to Z

9.7

G to Pad High

7.6

t_GHL

G to Pad Low

8.9

t_LCO

I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading

Array Clock-Out (Pad-to-Pad), 64 Clock Loading

Capacitive Loading, Low to High

Capacitive Loading, High to Low

20.1

29.5

0.09

0.08

t_ACO

d_TLH

d_THL

Notes:

ns/pF

1. Delays based on 35 pF loading.

2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.

v3.1

1-17

Radiation-Hardened FPGAs

Pin Description

CLKA

Clock A (Input)

No Connection

TTL clock input for clock distribution networks. The clock

input is buffered prior to clocking the logic modules. This

pin can also be used as an I/O.

This pin is not connected to circuitry within the device.

PRA, I/O

Probe A (Output)

The Probe A pin is used to output data from any user-

defined design node within the device. This independent

diagnostic pin can be used in conjunction with the Probe

B pin to allow real-time diagnostic output of any signal

path within the device. The Probe A pin can be used as a

user-defined I/O when verification has been completed.

The pin’s probe capabilities can be permanently disabled

to protect programmed design confidentiality. PRA is

accessible when the MODE pin is HIGH. This pin functions

as an I/O when the MODE pin is LOW.

CLKB

Clock B (Input)

Not applicable for RH1020. TTL clock input for clock

distribution networks. The clock input is buffered prior

to clocking the logic modules. This pin can also be used

as an I/O.

DCLK

Diagnostic Clock (Input)

TTL clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin is

LOW. If the Program fuse is not programmed and DCLK is

undefined, it is configured as an inactive input. In this

case, tie the DCLK pin to ground. If the Program fuse is

programmed and DCLK is undefined, it will become an

active LOW output.The Program fuse must be

programmed if the DCLK pin is used as an output or a

bidirectional pin.

PRB, I/O

Probe B (Output)

The Probe B pin is used to output data from any user-

defined design node within the device. This independent

diagnostic pin can be used in conjunction with the Probe

A pin to allow real-time diagnostic output of any signal

path within the device. The Probe B pin can be used as a

user-defined I/O when verification has been completed.

The pin’s probe capabilities can be permanently disabled

to protect programmed design confidentiality. PRB is

accessible when the MODE pin is HIGH. This pin functions

as an I/O when the MODE pin is LOW.

GND

Ground

LOW supply voltage.

I/O

Input/Output (Input, Output)

SDI

Serial Data Input (Input)

The I/O pin functions as an input, output, three-state, or

bidirectional buffer. Input and output levels are

compatible with standard TTL and CMOS specifications.

Unused I/O pins are automatically driven LOW by the

Designer software.

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

If the Program fuse is not programmed and SDI is

undefined, it is configured as an inactive input. In this

case, tie the SDI pin to ground. If the Program fuse is

programmed and SDI is undefined, it will become an

active LOW output.The Program fuse must be

programmed if the SDI pin is used as an output or a

bidirectional pin.

MODE

Mode (Input)

The MODE pin controls the use of multi-function pins

(DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the

special functions are active. When the MODE pin is LOW,

the pins function as I/Os. To provide debugging

capability, the MODE pin should be terminated to GND

through a 10 kΩ resistor so that the MODE pin can be

pulled HIGH when required.

5.0V Supply Voltage

HIGH supply voltage.

1. Please refer to the Actel Technical Brief Analysis of SDI/DCLK Issue for RH1020 and RT1020.

1-18

v3.1

Radiation-Hardened FPGAs

Package Pin Assignments

84-Pin CQFP

Pin #1

Index

84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64

84-Pin

CQFP

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Figure 2-1 • 84-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-1

Radiation-Hardened FPGAs

84-Pin CQFP

RH1020

Number

Function

Number

Function

Number

Function

I/O

GND

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

GND

I/O

CLKA, I/O

I/O

MODE

V_CC

I/O

V_CC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

GND

I/O

V_CC

I/O

2-2

v3.1

Radiation-Hardened FPGAs

172-Pin CQFP

172 171 170 169 168 167 166 165 164

137 136 135 134 133 132 131 130

Pin #1

Index

129

128

127

126

125

124

123

122

172-Pin

CQFP

44 45 46 47 48 49 50 51 52

79 80 81 82 83 84 85 86

Figure 2-2 • 172-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Package Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-3

Radiation-Hardened FPGAs

172-Pin CQFP

RH1280A

172-Pin CQFP

RH1280A

172-Pin CQFP

RH1280A

Pin Number Function

MODE

I/O

GND

I/O

V_CC

I/O

GND

I/O

GND

V_CC

I/O

100

101

102

103

104

105

I/O

GND

I/O

V_CC

I/O

GND

I/O

GND

I/O

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

GND

V_CC

GND

V_CC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

V_CC

I/O

SDI, I/O

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

2-4

v3.1

Radiation-Hardened FPGAs

172-Pin CQFP

RH1280A

Pin Number Function

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

GND

I/O

PRA, I/O

I/O

CLKA, I/O

V_CC

GND

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

GND

I/O

V_CC

I/O

DCLK, I/O

I/O

v3.1

2-5

Radiation-Hardened FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v3.1)

Page

1-1

v3.0

"Development Tool Support" section was updated.

Table 1-1 was updated.

1-5

Table 1-2 was updated.

1-6

Table 1-3 was updated.

1-7

The "DCLK Diagnostic Clock (Input)" section was updated.

The "SDI1 Serial Data Input (Input)" section was updated.

1-18

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

International Traffic in Arms Regulations (ITAR)

The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They

require an approved export license prior to export from the United States. An export includes release of product or

disclosure of technology to a foreign national inside or outside the United States.

v3.1

3-1

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

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www.actel.com.cn

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Phone +852 2185 6460

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5172123-3/4.05

RH1020-CQ84V [ACTEL]

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