A40MX02-VQ208A_技术文档

40MX and 42MX Automotive FPGA Families

flops can be constructed from logic modules whenever

required in the application.

General Description

Actels' automotive-grade MX families provide a high-

performance, single-chip solution for shortening the

system design and development cycle, offering a cost-

effective alternative to ASICs for in-cabin telematics and

automobile interconnect applications. The 40MX and

42MX devices are excellent choices for integrating logic

that is currently implemented in multiple PALs, CPLDs,

and FPGAs.

The 42MX devices contain three types of logic modules:

combinatorial (C-modules), sequential (S-modules) and

decode

(D-modules).

Figure 1-2

illustrates

the

combinatorial logic module. The S-module, shown in

Figure 1-3 on page 1-2, implements the same

combinatorial logic function as the C-module while

adding a sequential element. The sequential element can

be configured as either a D-flip-flop or a transparent

latch. The S-module register can be bypassed so that it

implements purely combinatorial logic.

The MX device architecture is based on Actel’s patented

antifuse technology implemented in a 0.45µm triple-

metal CMOS process. With capacities ranging from 3,000

to 54,000 system gates, the MX devices are live on

power-up and have one-fifth the standby power

consumption of comparable FPGAs. Actel’s MX FPGAs

provide up to 202 user I/Os and are available in a wide

variety of packages and speed grades.

A42MX24 and A42MX36 devices contain D-modules,

which are arranged around the periphery of the device.

D-modules contain wide-decode circuitry, providing a

fast, wide-input AND function similar to that found in

CPLD architectures (Figure 1-4 on page 1-2). The D-

module allows A42MX24 and A42MX36 devices to

perform wide-decode functions at speeds comparable to

CPLDs and PALs. The output of the D-module has a

programmable inverter for active HIGH or LOW

assertion. The D-module output is hardwired to an

output pin, and can also be fed back into the array to be

incorporated into other logic.

The automotive-grade 42MX24 and 42MX36 include

system-level features such as IEEE Standard 1149.1 (JTAG)

Boundary Scan Testing and fast wide-decode modules. In

addition, the A42MX36 device offers dual-port SRAM for

implementing fast FIFOs, LIFOs, and temporary data

storage. The storage elements can efficiently address

applications requiring wide datapath manipulation.

MX Architectural Overview

The MX devices are composed of fine-grained building

blocks that enable fast, efficient logic designs. All devices

within these families are composed of logic modules, I/O

modules, routing resources and clock networks, which

are the building blocks for fast logic designs. In addition,

the A42MX36 device contains embedded dual-port

SRAM modules, which are optimized for high-speed

datapath functions such as FIFOs, LIFOs and scratchpad

memory. A42MX24 and A42MX36 also contain wide-

decode modules.

Figure 1-1 • 40MX Logic Module

A0

B0

S0

Logic Modules

D00

The 40MX logic module is an eight-input, one-output

logic circuit designed to implement a wide range of logic

functions with efficient use of interconnect routing

resources (Figure 1-1).

D01

D10

D11

Y

S1

The logic module can implement the four basic logic

functions (NAND, AND, OR and NOR) in gates of two,

three, or four inputs. The logic module can also

implement a variety of D-latches, exclusivity functions,

AND-ORs and OR-ANDs. No dedicated hardwired latches

or flip-flops are required in the array; latches and flip-

A1

B1

Figure 1-2 • 42MX C-Module Implementation

v3.1

1-1

40MX and 42MX Automotive FPGA Families

D00

D01

D00

D01

D

Y

Q

OUT

Q

OUT

Y

D10

S0

D11

S1

D11

S1

GATE

CLR

Up to 7-Input Function Plus Latch

D00

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

D0

D01

D10

D11

Y

OUT

Q

D

Y

OUT

S0

D1

GATE

S

S1

CLR

Up to 8-Input Function (Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 1-3 • 42MX S-Module Implementation

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

Feedback to Array

Figure 1-4 • A42MX24 and A42MX36 D-Module Implementation

Dual-Port SRAM Modules

The A42MX36 device contains dual-port SRAM modules,

which are arranged in 256-bit blocks and can be

configured as 32x8 or 64x4. SRAM modules can be

cascaded together to form memory spaces of user-

definable width and depth. A block diagram of the

A42MX36 dual-port SRAM block is shown in Figure 1-5

on page 1-3.

contain independent clocks (RCLK and WCLK) with

programmable polarities offering active HIGH or LOW

implementation. The SRAM block contains eight data

inputs (WD[7:0]) and eight outputs (RD[7:0]), which are

connected to segmented vertical routing tracks.

The A42MX36 dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring

FIFO and LIFO queues. The ACTgen Macro Builder within

Actel's Designer software provides capability to quickly

design memory functions with the SRAM blocks.

The A42MX36 SRAM modules are true dual-port

structures containing independent read and write ports.

Each SRAM module contains six bits of read and write

addressing (RDAD[5:0] and WRAD[5:0], respectively) for

64x4-bit blocks. When configured in byte mode, the

highest order address bits (RDAD5 and WRAD5) are not

used. The read and write ports of the SRAM block

1-2

v3.1

40MX and 42MX Automotive FPGA Families

Latches

WD[7:0]

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4 Port

Logic

Latches

Write

Port

Read

Logic

(256 Bits)

[5:0]

WRAD[5:0]

MODE

BLKEN

WEN

Read

Logic

Latches

REN

RD[7:0]

RCLK

Write

Logic

Routing Tracks

WCLK

Figure 1-5 • A42MX36 Dual-Port SRAM Block

above and two below), except near the top and bottom

of the array, where edge effects occur. Long vertical

tracks contain either one or two segments. An example

of vertical routing tracks and segments is shown in

Figure 1-6.

Routing Structure

The MX architecture uses vertical and horizontal routing

tracks to interconnect the various logic and I/O modules.

These routing tracks are metal interconnects that may be

continuous or split into segments. Varying segment

lengths allow the interconnect of over 90% of design

tracks to occur with only two antifuse connections.

Segments can be joined together at the ends using

antifuses to increase their lengths up to the full length of

the track. All interconnects can be accomplished with a

maximum of four antifuses.

Segmented

Horizontal

Routing

Logic

Modules

Antifuses

Horizontal Routing

Horizontal routing tracks span the whole row length or

are divided into multiple segments and are located in

between the rows of modules. Any segment that spans

more than one-third of the row length is considered a

long horizontal segment. A typical channel is shown in

Figure 1-6. Within horizontal routing, dedicated routing

tracks are used for global clock networks and for power

and ground tie-off tracks. Non-dedicated tracks are used

for signal nets.

Vertical Routing Tracks

Figure 1-6 • MX Routing Structure

Antifuse Structures

An antifuse is a "normally open" structure. The use of

antifuses to implement a programmable logic device

results in highly testable structures as well as efficient

programming algorithms. There are no pre-existing

connections; temporary connections can be made using

pass transistors. These temporary connections can isolate

individual antifuses to be programmed and individual

circuit structures to be tested, which can be done before

and after programming. For instance, all metal tracks can

be tested for continuity and shorts between adjacent

tracks, and the functionality of all logic modules can be

verified.

Vertical Routing

Another set of routing tracks run vertically through the

module. There are three types of vertical tracks: input,

output, and long. Long tracks span the column length of

the module, and can be divided into multiple segments.

Each segment in an input track is dedicated to the input

of a particular module; each segment in an output track

is dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

routing. Each output segment spans four channels (two

v3.1

1-3

40MX and 42MX Automotive FPGA Families

•

Internally from the CLKINTB input, using CLKINT

buffer

Clock Networks

The 40MX devices have one global clock distribution

network (CLK). A signal can be put on the CLK network

by being routed through the CLKBUF buffer.

The clock modules are located in the top row of I/O

modules. Clock drivers and a dedicated horizontal clock

track are located in each horizontal routing channel.

In 42MX devices, there are two low-skew, high-fanout

clock distribution networks, referred to as CLKA and

CLKB. Each network has a clock module (CLKMOD) that

can select the source of the clock signal from any of the

following (Figure 1-7):

Clock input pads in both 40MX and 42MX devices can

also be used as normal I/Os, bypassing the clock

networks.

The A42MX36 device has four additional register control

resources, called quadrant clock networks (Figure 1-8).

Each quadrant clock provides a local, high-fanout

resource to the contiguous logic modules within its

quadrant of the device. Quadrant clock signals can

originate from specific I/O pins or from the internal array

and can be used as a secondary register clock, register

clear, or output enable.

•

Externally from the CLKA pad, using CLKBUF

buffer

Externally from the CLKB pad, using CLKBUF

buffer

Internally from the CLKINTA input, using CLKINT

buffer

CLKB

CLKA

CLKINB

CLKINA

From

S0

S1

Pads

Internal

CLKMOD

Signal

CLKO(17)

Clock

CLKO(16)

CLKO(15)

Drivers

CLKO(2)

CLKO(1)

Clock Tracks

Figure 1-7 • Clock Networks of 42MX Devices

QCLKA

Quad

QCLKC

Quad

Clock

Modul

Clock

QCLK1

QCLK3

QCLKD

QCLKB

Modul

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Modul

Clock

QCLK2

QCLK4

Modul

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 1-8 • Quadrant Clock Network of A42MX36 Devices

1-4

v3.1

40MX and 42MX Automotive FPGA Families

there is the Security Fuse which, when programmed,

both disables the probing circuitry and prohibits further

programming of the device.

I/O Modules

The I/O modules provide the interface between the

device pins and the logic array. Figure 1-9 is a block

diagram of the 42MX I/O module. A variety of user

functions, determined by a library macro selection, can

be implemented in the module. (Refer to the Antifuse

Macro Library Guide for more information.) All 42MX I/O

modules contain tristate buffers, with input and output

latches that can be configured for input, output, or

bidirectional operation.

Look for this symbol to ensure your valuable IP is secure.

™

u

e

42MX devices contain flexible I/O structures, where each

output pin has a dedicated output-enable control

(Figure 1-9). The I/O module can be used to latch input or

output data, or both, providing fast setup time. In

addition, the Actel Designer software tools can build a D-

type flip-flop using a C-module combined with an I/O

module to register input and output signals. Refer to the

Antifuse Macro Library Guide for more details.

Figure 1-10 • Fuselock

For more information, refer to Actel's Implementation of

Security in Actel Antifuse FPGAs application note.

Programming

Device programming is supported through the Silicon

Sculptor series of programmers. Silicon Sculptor II is a

compact, robust, single-site and multi-site device

programmer for the PC. With standalone software,

Silicon Sculptor II is designed to allow concurrent

programming of multiple units from the same PC.

Actel's Designer software development tools provide a

design library of I/O macro functions that can implement

all I/O configurations supported by the MX FPGAs.

EN

Silicon Sculptor II programs devices independently to

achieve the fastest programming times possible. After

being programmed, each fuse is verified to insure that it

has been programmed correctly. Furthermore, at the end

of programming, there are integrity tests that are run to

ensure no extra fuses have been programmed. Not only

Q

D

PAD

From Array

To Array

G/CLK*

does

it

test

fuses

(both

programmed

and

Q

D

nonprogrammed), Silicon Sculptor II also allows self-test

to verify its own hardware extensively.

G/CLK*

The procedure for programming an MX device using

Silicon Sculptor II is as follows:

Note: *Can be configured as a Latch or D Flip-Flop (Using

1. Load the .AFM file

C-Module)

2. Select the device to be programmed

3. Begin programming

Figure 1-9 • 42MX I/O Module

Other Architectural Features

User Security

The Actel FuseLock provides robust security against

design theft. Special security fuses are hidden in the

fabric of the device and prevent unauthorized users from

accessing the programming and/or probe interfaces. It is

virtually impossible to identify or bypass these fuses

without damaging the device, making Actel antifuse

FPGAs immune to both invasive and noninvasive attacks.

When the design is ready to go to production, Actel

offers device volume-programming services either

through distribution partners or via In-House

Programming from the factory.

For more details on programming MX devices, please

refer to the Programming Antifuse Devices and the

Silicon Sculptor II user's guides.

Special security fuses in 40MX devices include the Probe

Fuse and Program Fuse. The former disables the probing

circuitry while the latter prohibits further programming

of all fuses, including the Probe Fuse. In 42MX devices,

v3.1

1-5

40MX and 42MX Automotive FPGA Families

Power Supply

Automotive MX devices are designed to operate in 5.0V environments. Table 1-1 describes the voltage settings of

automotive MX devices.

Table 1-1 • Voltage Support of Automotive-Grade MX Devices

Device

40MX

V_CC

5.0V

–

V_CCA

–

V_CCI

–

Maximum Input Tolerance

Nominal Output Voltage

5.25V

5.0V

42MX

5.0V

Silicon Explorer II is used to control the MODE, DCLK, SDI

and SDO pins in MX devices to select the desired nets for

debugging. The user simply assigns the selected internal

nets in the Silicon Explorer II software to the PRA/PRB

output pins for observation. Probing functionality is

activated when the MODE pin is held HIGH.

Power-Up/Down

When powering up MX devices, V_CCAmust be greater

than or equal to V_CCIthroughout the power-up

sequence. If V_CCIexceeds V_CCAduring power-up, either

the input protection junction on the I/Os will be forward-

biased or the I/Os will be at logical High, and I_CCrises to

high levels. During power-down, V_CCAmust be smaller

Figure 1-11 on page 1-7 illustrates the interconnection

between Silicon Explorer II and 40MX devices, while

Figure 1-12 on page 1-7 illustrates the interconnection

between Silicon Explorer II and 42MX devices

than or equal to V_CCI

.

Test Circuitry and Silicon Explorer II Probe

To allow for probing capabilities, the security fuses must

not be programmed. (Refer to "User Security" section on

page 1-5 for the security fuses of 40MX and 42MX

devices). Table 1-2 on page 1-7 summarizes the possible

device configurations for probing.

MX devices contain probing circuitry that provides built-

in access to every node in a design, via the use of Silicon

Explorer II. Silicon Explorer II is an integrated hardware

and software solution that, in conjunction with the

Designer software, allow users to examine any of the

internal nodes of the device while it is operating in a

prototyping or a production system. The user can probe

an MX device without changing the placement and

routing of the design and without using any additional

resources. Silicon Explorer II's noninvasive method does

not alter timing or loading effects, thus shortening the

debug cycle and providing a true representation of the

device under actual functional situations.

PRA and PRB pins are dual-purpose pins. When the

"Reserve

Probe

Pin"

is

checked

in

the

Designer software, PRA and PRB pins are reserved as

dedicated outputs for probing. If PRA and PRB pins are

required as user I/Os to achieve successful layout and

"Reserve Probe Pin" is checked, the layout tool will

override the option and place user I/Os on PRA and PRB

pins.

Silicon Explorer II samples data at 100 MHz

(asynchronous) or 66 MHz (synchronous). Silicon Explorer

II attaches to a PC's standard serial port, turning the PC

into a fully functional 18-channel logic analyzer. Silicon

Explorer II allows designers to complete the design

verification process at their desks and reduces

verification time from several hours per cycle to a few

seconds.

1-6

v3.1

40MX and 42MX Automotive FPGA Families

16 Logic Analyzer Channels

40MX

Serial Connection

to Windows PC

MODE

SDI

DCLK

Silicon

Explorer II

SDO

PRA

PRB

Figure 1-11 • Silicon Explorer II Setup with 40MX

16 Logic Analyzer Channels

42MX

Serial Connection

to Windows PC

MODE

SDI

DCLK

Silicon

Explorer II

SDO

PRA

PRB

Figure 1-12 • Silicon Explorer II Setup with 42MX

Table 1-2 • Device Configuration Options for Probe Capability

Security Fuse(s) Programmed

MODE

LOW

HIGH

–

PRA, PRB¹

User I/Os²

SDI, SDO, DCLK¹

User I/Os²

No

Probe Circuit Outputs

Probe Circuit Secured

Probe Circuit Inputs

Probe Circuit Secured

Yes

Notes:

1. Avoid using SDI, SDO, DCLK, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input

signals will not pass through these pins and may cause contention.

2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin Descriptions" section on

page 1-45 for information on unused I/O pins.

v3.1

1-7

40MX and 42MX Automotive FPGA Families

The TAP controller is a four-bit state machine. The '1's

and '0's represent the values that must be present at TMS

at a rising edge of TCK for the given state transition to

occur. IR and DR indicate that the instruction register or

the data register is operating in that state.

Design Consideration

It is recommended to use a series 70Ω termination

resistor on every probe connector (SDI, SDO, MODE,

DCLK, PRA and PRB). The 70Ω series termination is used

to prevent data transmission corruption during probing

and reading back the checksum.

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain high for five TCK cycles.

IEEE Standard 1149.1 Boundary Scan Test

(BST) Circuitry

Automotive-grade 42MX24 and 42MX36 devices are

compatible with IEEE Standard 1149.1 (informally known

as Joint Testing Action Group Standard or JTAG), which

defines a set of hardware architecture and mechanisms

for cost-effective, board-level testing. The basic MX

boundary-scan logic circuit is composed of the TAP (test

access port), TAP controller, test data registers and

instruction register (Figure 1-13). This circuit supports all

mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/

PRELOAD and BYPASS) and some optional instructions.

Table 1-3 on page 1-9 describes the ports that control

JTAG testing, while Table 1-4 on page 1-9 describes the

test instructions supported by these MX devices.

Automotive-grade 42MX24 and 42MX36 devices support

three types of test data registers: bypass, device

identification, and boundary scan. The bypass register is

selected when no other register needs to be accessed in a

device. This speeds up test data transfer to other devices

in a test data path. The 32-bit device identification

register is a shift register with four fields (lowest

significant byte (LSB), ID number, part number and

version). The boundary-scan register observes and

controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output and control

ports of an I/O buffer to capture and load data into the

register to control or observe the logic state of each I/O.

Each test section is accessed through the TAP, which has

four associated pins: TCK (test clock input), TDI and TDO

(test data input and output), and TMS (test mode

selector).

Boundary Scan Register

Output

MUX

TDO

Bypass

Register

Control Logic

JTAG

TMS

Instruction

Decode

TAP Controller

TCK

JTAG

TDI

Instruction

Register

Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry

1-8

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-3 • Test Access Port Descriptions

Port

Description

Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK)

TMS

(Test

Select)

TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge

of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency

for TCK is 20 MHz

TDI (Test Data Input)

Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock

TDO

Output)

(Test

Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high

impedance) when data scanning is not in progress

Table 1-4 • Supported BST Public Instructions

Instruction

IR Code [2:0]

Instruction Type

Description

EXTEST

000

Mandatory

Allows the external circuitry and board-level interconnections to

be tested by forcing a test pattern at the output pins and

capturing test results at the input pins

SAMPLE/PRELOAD

HIGH Z

001

101

110

Mandatory

Optional

Allows a snapshot of the signals at the device pins to be

captured and examined during operation

Tristates all I/Os to allow external signals to drive pins. Please

refer to the IEEE Standard 1149.1 specification for details

CLAMP

Allows state of signals driven from component pins to be

determined from the Boundary-Scan Register. Please refer to

the IEEE Standard 1149.1 specification for details

BYPASS

111

Mandatory

Enables the bypass register between the TDI and TDO pins. The

test data passes through the selected device to adjacent devices

in the test chain

v3.1

1-9

40MX and 42MX Automotive FPGA Families

JTAG Mode Activation

The JTAG test logic circuit is activated in the Designer

software by selecting Tools and then Device Selection.

This brings up the Device Selection dialog box as shown

in Figure 1-14. The JTAG test logic circuit can be enabled

by clicking the "Reserve JTAG Pins" check box. Table 1-5

explains the pins' behavior in either mode.

Figure 1-14 • Device Selection Wizard

Table 1-5 • Boundary Scan Pin Configuration and Functionality

Reserve JTAG

TCK

Checked

Unchecked

User I/O

BST input; must be terminated to logical HIGH or LOW to avoid floating

BST input; may float or be tied to HIGH. TDI may be tied to TDO of another device

BST output; may float or be connected to TDI of another device

TDI, TMS

TDO

User I/O

TRST Pin and TAP Controller Reset

Boundary Scan Description Language

(BSDL) File

An active reset (TRST) pin is not supported; however, MX

devices contain power-on circuitry that resets the

boundary-scan circuitry upon power-up. Also, the TMS

pin is equipped with an internal pull-up resistor. This

allows the TAP controller to remain in or return to the

Test-Logic-Reset state when there is no input or when a

logical 1 is on the TMS pin. To reset the controller, TMS

must be HIGH for at least five TCK cycles.

Conforming to the IEEE Standard 1149.1 requires that

the operation of the various JTAG components be

documented. The BSDL file provides the standard format

to describe the JTAG components that can be used by

automatic test equipment software. The file includes the

instructions that are supported, instruction-bit pattern,

and the boundary-scan chain order. For an in-depth

discussion on BSDL files, please refer to Actel BSDL Files

Format Description application note.

Actel BSDL files are grouped into two categories—

generic and device-specific. The generic files assign all

user I/Os as inouts. Device-specific files assign user I/Os as

inputs, outputs, or inouts.

Generic files for MX devices are available on Actel's website

at http://www.actel.com/techdocs/models/bsdl.html.

1-10

v3.1

40MX and 42MX Automotive FPGA Families

Development Tool Support

Related Documents

The automotive-grade MX family of FPGAs is fully

supported by both Actel's Libero™ Integrated Design

Environment (IDE) and Designer FPGA Development

software. Actel Libero IDE is a design management

environment, seamlessly integrating design tools while

guiding the user through the design flow, managing all

design and log files, and passing necessary design data

among tools. Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment. Libero IDE

includes Synplify® for Actel from Synplicity®, ViewDraw

for Actel from Mentor Graphics, ModelSim™ HDL

Simulator from Mentor Graphics®, WaveFormer Lite™

from SynaptiCAD™, and Designer software from Actel.

Refer to the Libero IDE flow (located on Actel’s website)

diagram for more information.

Application Notes

Actel BSDL Files Format Description

www.actel.com/documents/BSDLformat_AN.pdf

Programming Antifuse Devices

http://www.actel.com/documents/

AntifuseProgram_AN.pdf

Actel's Implementation of Security in Actel Antifuse

FPGAs

www.actel.com/documents/Antifuse_Security_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

www.actel.com/documents/libguide_UG.pdf

Silicon Sculptor II

www.actel.com/techdocs/manuals/default.asp#programmers

timing-driven place-and-route, and

a

world-class

integrated static timing analyzer and constraints editor.

With the Designer software, a user can select and lock

package pins while only minimally impacting the results

of place-and-route. Additionally, the back-annotation

flow is compatible with all the major simulators and the

simulation results can be cross-probed with Silicon

Explorer II, Actel’s integrated verification and logic

analysis tool. Another tool included in the Designer

software is the ACTgen macro builder, which easily

creates popular and commonly used logic functions for

implementation into your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

companies such as Mentor Graphics, Synplicity, Synopsys,

and Cadence Design Systems. The Designer software is

available for both the Windows and UNIX operating

systems.

Miscellaneous

Libero IDE Flow Diagram

www.actel.com/products/tools/libero/flow.html

v3.1

1-11

40MX and 42MX Automotive FPGA Families

5.0V Operating Conditions

*

Absolute Maximum Ratings

Recommended Operating Conditions

Parameter

Automotive¹

-40 to +125

4.75 to 5.25

Units

Free Air Temperature Range

Temperature Range²

°C

V

Symbol

Parameter

Limits

Units

V_CCI

V_CC/V_CCA/V_CCIDC Supply Voltage

–0.5 to +6.5

V

V_CCA

V_CC

V

V_I

Input Voltage

–0.5 to V_CC+0.5

–65 to +150

V

V_O

T_STG

Output Voltage

Storage Temperature

V

Notes:

°C

1. Automotive grade parts (A grade) devices are tested at room

temperature to specifications that have been guard banded

based on characterization across the recommended

operating conditions. A-grade parts are not tested at

extended temperatures. If testing to ensure guaranteed

operation at extended temperatures is required, please

contact your local Actel Sales office to discuss testing

options available.

Note: *Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for

extended periods may affect device reliability. Devices

should not be operated outside the Recommended

Operating Conditions.

2. Ambient temperature (T_A)

Electrical Specifications

Automotive

Units

Symbol Parameter

Conditions

(I_OH= –4 mA)

(I_OL= 4 mA)

Min.

Max.

1

V_OH

Output High Voltage

3.1

V

1

V_OL

V_IL

Output Low Voltage

Input Low Voltage

0.4

0.6

V

V_IH

Input High Voltage

2.1

–20

V

I_IL, I_IH

I_OZ

Input Leakage Current

Tristate Output Leakage Current

Input Transition Time

I/O Capacitance

20

µA

ns

pF

mA

t_R, t_F

C_IO

250

10

2

I_CC

Standby Current

35

I_IO

I/O source sink current

Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)

Notes:

1. Only one output tested at a time. V_CC/V_CCI= min.

2. All outputs unloaded. All inputs = V_CC/V_CCIor GND.

1-12

v3.1

40MX and 42MX Automotive FPGA Families

Active Power Component

Power Dissipation

Power dissipation in CMOS devices is usually dominated

by the active (dynamic) power dissipation. This

component is frequency-dependent and a function of

the logic and the external I/O. Active power dissipation

results from charging internal chip capacitances of the

interconnect, unprogrammed antifuses, module inputs,

and module outputs, plus external capacitance due to PC

board traces and load device inputs. An additional

component of the active power dissipation is the totem

pole current in the CMOS transistor pairs. The net effect

can be associated with an equivalent capacitance that

can be combined with frequency and voltage to

represent active power dissipation.

General Power Equation

P = [I_CCstandby + I_CCactive] * V_CCI+ I_OL* V_OL* N

+ I_OH* (V_CCI– V_OH) * M

where:

I

_CCstandby is the current flowing when no inputs or

outputs are changing.

_CCactive is the current flowing due to CMOS

switching.

_OL, I_OHare TTL sink/source currents.

_OL, V_OHare TTL level output voltages.

N equals the number of outputs driving TTL loads to

V_OL

M equals the number of outputs driving TTL loads to

V_OH

I

V

The power dissipated by a CMOS circuit can be expressed

by the equation:

.

Power (µW) = C_EQ* V_CCA²* F

EQ 1-1

.

Accurate values for N and M are difficult to determine

because they depend on the family type, on design

details, and on the system I/O. The power can be divided

into two components: static and active.

where:

C_EQ

=

Equivalent

picofarads (pF)

capacitance

expressed

in

=

V_CCA

F

Power supply in volts (V)

Switching frequency in megahertz (MHz)

Static Power Component

Actel FPGAs have small static power components that

result in power dissipation lower than PALs or CPLDs. By

integrating multiple PALs/CPLDs into one FPGA, an even

greater reduction in board-level power dissipation can

be achieved.

Equivalent Capacitance

Equivalent capacitance is calculated by measuring

I_CCactive at a specified frequency and voltage for each

circuit component of interest. Measurements have been

The power due to standby current is typically a small

component of the overall power.

made over a range of frequencies at a fixed value of V

.

CC

Equivalent capacitance is frequency-independent, so the

results can be used over a wide range of operating

conditions. Equivalent capacitance values are shown on

the following page.

The static power dissipation by TTL loads depends on the

number of outputs driving HIGH or LOW, and on the DC

load current. Again, this number is typically small. For

instance, a 32-bit bus sinking 4 mA at 0.33V will generate

42 mW with all outputs driving LOW, and 140 mW with

all outputs driving HIGH. The actual dissipation will

average somewhere in between, as I/Os switch states

with time.

v3.1

1-13

40MX and 42MX Automotive FPGA Families

C

Values for Actel MX FPGAs

Fixed Capacitance Values

for MX FPGAs (pF)

EQ

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

)

3.5

r1

r2

)

6.9

18.2

1.4

Device Type

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

routed_Clk1

routed_Clk2

)

41.4

68.6

118

165

185

220

N/A

118

165

185

220

)

To calculate the active power dissipated from the

complete design, the switching frequency of each part of

the logic must be known. The equation below shows a

piece-wise linear summation over all components.

Power = V_CCA²* [(m x C_EQM* f_m)_Modules

(n * C_EQI* f_n)_Inputs+ (p * (C_EQO+ C_L) * f_p)_outputs

0.5 * (q₁* C_EQCR* f_{q1 routed_Clk1}+ (r₁* f_{q1 routed_Clk1}

0.5 * (q₂* C_EQCR* f_{q2 routed_Clk2}+ (r₂* f_{q2 routed_Clk2}

+

)

+

)

Determining Average Switching

Frequency

EQ 1-2

where:

To determine the switching frequency for a design, the

data input values to the circuit must be clearly

understood. The following guidelines represent worst-

case scenarios; these can be used to generally predict the

upper limits of power dissipation.

m

n

=

Number of logic modules switching at frequency f_m

Number of input buffers switching at frequency f_n

Number of output buffers switching at frequency f_p

p

Logic Modules (m)

=

80% of

q₁

Number of clock loads on the first routed array

clock

Combinatorial

Modules

q₂

=

Number of clock loads on the second routed array

clock

Inputs Switching (n)

=

# of Inputs/4

Outputs Switching (p)

# of Outputs/4

r₁

=

Fixed capacitance due to first routed array clock

Fixed capacitance due to second routed array clock

Equivalent capacitance of logic modules in pF

Equivalent capacitance of input buffers in pF

Equivalent capacitance of output buffers in pF

Equivalent capacitance of routed array clock in pF

Output load capacitance in p

First Routed Array Clock Loads (q₁)

40% of Sequential

Modules

r₂

C_EQM

C_EQI

C_EQO

C_EQCR

C_L

Second Routed Array Clock Loads = 40% of Sequential

(q₂)

Modules

Load Capacitance (C_L)

=

35 pF

Average Logic Module Switching = F/10

Rate (f_m)

Average Input Switching Rate (f_n)

Average Output Switching Rate (f_p)

=

F/5

F/10

F

f_m

Average logic module switching rate in MHz

Average input buffer switching rate in MHz

Average output buffer switching rate in MHz

Average first routed array clock rate in MHz

Average second routed array clock rate in MHz

f_n

Average First Routed Array Clock =

Rate (f_q1

f_p

)

f_q1

Average Second Routed Array Clock = F/2

Rate (f_q2

)

f_q2

1-14

v3.1

40MX and 42MX Automotive FPGA Families

∆T = θ_ja* P

Junction Temperature

P = Power

The temperature variable in the Designer software refers

to the junction temperature, not the ambient

temperature. This is an important distinction because the

heat generated from dynamic power consumption is

usually hotter than the ambient temperature. EQ 1-3 can

be used to calculate junction temperature.

θ_ja= Junction to ambient of package. θ_janumbers are

located in the "Package Thermal Characteristics" section.

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θ_jc,

and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two

different air flow rates.

Junction Temperature = ∆T + T_a(1)

EQ 1-3

Where:

Maximum junction temperature is 150°C.

T_a= Ambient Temperature

A sample calculation of the absolute maximum power

dissipation allowed for a PQFP 160-pin package at

automotive temperature is as follows:

∆T = Temperature gradient between junction (silicon)

and ambient

Max. junction temp. (°C) – Max. automotive temp.

150°C – 125°C

---------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 0.95W

θ

(°C/W)

26.2°C/W

ja

Table 1-6 • Package Thermal Characteristics

θ_ja

1.0 m/s

2.5 m/s

Plastic Packages

Pin Count

100

θ_jc

Still Air

27.8

200 ft./min. 500 ft./min.

Units

°C/W

Plastic Quad Flat Pack

12.0

10.0

8.0

23.4

22.8

22.5

22.3

21.0

18.9

19.9

31.9

29.4

21.2

21.1

20.8

19.4

17.6

18.0

29.4

27.1

Plastic Quad Flat Pack

160

26.2

Plastic Quad Flat Pack

208

26.1

Plastic Quad Flat Pack

240

8.5

25.6

Plastic Leaded Chip Carrier

Thin Plastic Quad Flat Pack

Very Thin Plastic Quad Flat Pack

68

13.0

12.0

11.0

12.0

10.0

25.0

84

22.5

176

24.7

80

38.2

100

35.3

v3.1

1-15

40MX and 42MX Automotive FPGA Families

Timing Information

Input Delay

Internal Delays

Predicted

Routing

Delays

Output Delay

I/O Module

t_INYL= 1.2 ns

t_IRD2= 4.6 ns

Logic Module

t_DLH= 5.9 ns

t_IRD1= 3.7 ns

t_IRD4= 6.5 ns

t_IRD8= 10.2 ns

t

_RD1= 2.3 ns

t

_PD= 2.2 ns

t_CO= 2.2 ns

t_ENHZ= 14.1 ns

t_RD2= 3.2 ns

t

_RD4= 5.1 ns

_RD8= 8.8 ns

t

Array

Clock

t_CKH= 8.1 ns

F_MAX= 116 MHz

FO = 128

Note: * Values are shown for 40MX at worst-case 5.0V automotive conditions.

Figure 1-15 • 40MX Timing Model*

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t_IRD1

=

t

_INYL= 1.3 ns

3.4 ns†

Combinatorial

Logic Module

t_DLH= 4.0 ns

t_RD1= 1.1 ns

D

G

Q

t

_PD= 2.0 ns

t

_RD2= 1.6 ns

_RD4= 2.2 ns

t_RD8= 3.8 ns

I/O Module

t_DLH= 4.0 ns

Sequential

Logic Module

t

_INH= 0.0 ns

t

_INSU= 0.4 ns

t_INGL= 2.1 ns

Combin-

atorial

D

Q

D

G

Q

Logic

t_RD1= 1.1 ns

t

_ENHZ= 8.2 ns

included

in t_SUD

t

_OUTH= 0.00 ns

t_OUTSU= 0.4 ns

= 4.3 ns

t_SUD= 0.4 ns

t_HD= 0.0 ns

t_CO= 2.1 ns

Array

t_GLH

Clocks

t_CKH= 4.0 ns

FO = 32

F_MAX= 192 MHz

t_LCO= 8.6 ns (light loads, pad-to-pad)

Notes:

*Values are shown for A42MX09 at worst-case 5.0V automotive conditions.

† Input module predicted routing delay

Figure 1-16 • 42MX Timing Model*

1-16

v3.1

40MX and 42MX Automotive FPGA Families

Input Delays

Internal Delays

Predicted

Output Delays

I/O Module

Routing

Delays

I/O Module

t_INPY= 1.7 ns

t

_IRD1= 3.3 ns

Combinatorial

Module

t_DLH= 4.3 ns

t

_RD1= 1.6 ns

D

Q

t_PD= 2.3 ns

t_RD2= 2.2 ns

t_RD4= 3.3 ns

G

Decode

Module

t

_INH= 0.0 ns

t_RDD= 0.6 ns

t

_INSU= 0.8 ns

t_INGO= 2.4 ns

t

_PDD= 2.7 ns

I/O Module

t

_DLH= 4.3 ns

Sequential

Logic Module

t

_RD1= 1.6 ns

Combin-

D

Q

D

G

Q

atorial

Logic

t_ENHZ= 8.8 ns

included

in t _SUD

t

_LH= 0.0 ns

t

_LSU= 0.8 ns

_GHL= 5.0 ns

t_SUD= 0.6 ns

_HD= 0.0 ns

t_CO= 2.2 ns

t

Quadrant

Clocks

t_CKH= 4.5 ns†

F_MAX= 116 MHz

Notes:

* Values are shown for A42MX36 at worst-case 5.0V automotive conditions.

†Load-dependent

Figure 1-17 • A42MX36 Timing Model (Logic Functions using Quadrant Clocks)*

v3.1

1-17

40MX and 42MX Automotive FPGA Families

Input Delays

I/O Module

t

_INPY= 1.7 ns

t

_IRD1= 3.3 ns

D

G

Q

Predicted

Routing

Delays

I/O Module

_DLH= 4.3 ns

= 0.8 ns

= 0.0 ns

= 2.4 ns

t_INSU

t

t_INH

RD [7:0]

RDAD [5:0]

REN

WD [7:0]

t_INGO

t

_RD1= 1.6 ns

WRAD [5:0]

BLKEN

D

G

Q

WEN

WCLK

RCLK

t

_ADSU= 2.7 ns

t_ADH= 0.0 ns

t_ADSU= 2.7 ns

= 5.0 ns

= 0.8 ns

= 0.0 ns

t_GHL

t_LSU

t_LH

t

_ADH= 0.0 ns

t_RENSU= 1.0 ns

t_RCO= 5.7 ns

Array

Clocks

t

_WENSU= 4.5 ns

t_BENS= 4.6 ns

F

_MAX= 123 MHz

Note: *Values are shown for A42MX36 at worst-case 5.0V automotive conditions.

Figure 1-18 • A42MX36 Timing Model (SRAM Functions)*

1-18

v3.1

40MX and 42MX Automotive FPGA Families

Parameter Measurement

E

D

To AC test loads (shown below)

PAD

TRIBUFF

In

E

50% 50%

V_CCI

50%

V_OH

50%

V_OH

1.5V

PAD

1.5V

PAD

GND

PAD

90%

t

ENHZ

1.5V

10%

ENLZ

V_OL

t

DHL

t

DLH

t

ENZL

ENZH

Figure 1-19 • Output Buffer Delays

Load 2

(Used to measure rising/falling edges)

Load 1

(Used to measure propagation delay)

To the output under test

35 pF

V_CCI

GND

R toV_CCIfor t

_PLZ/t_PZL

R to GND for t

_PHZ/t _PZH

R = 1 k

Ω

To the output under test

35 pF

Figure 1-20 • AC Test Loads

v3.1

1-19

40MX and 42MX Automotive FPGA Families

Sequential Timing Characteristics

S

Y

A

Y

B

PAD

INBUF

S, A or B

Y

50% 50%

50%

3V

50%

PAD

0V

50%

1.5V 1.5V

V_CCI

t

PLH

PHL

Y

GND

50%

t

PLH

PHL

t_INYH

t_INYL

Figure 1-21 • Input Buffer Delays

Figure 1-22 • Module Delays

D

E

CLK

PRE

CLR

Y

(Positive Edge-Triggered)

t_HD

D¹

t_A

t_SUD

t_WCLKA

G, CLK

t_SUENA

t _WCLKI

t_HENA

E

t_CO

Q

t_RS

PRE, CLR

t_WASYN

Note: D represents all data functions involving A. B. and S for multiplexed flip-flops.

Figure 1-23 • Flip-Flops and Latches

1-20

v3.1

40MX and 42MX Automotive FPGA Families

D

G

PAD

OBDLHS

D

G

t

OUTSU

t

OUTH

Figure 1-25 • Output Buffer Latches

PA D

G

DATA

IBDL

CLK PA D

DATA

t

INH

G

t

INSU

t

HEXT

CLK

t

SU EXT

Figure 1-24 • Input Buffer Latches

v3.1

1-21

40MX and 42MX Automotive FPGA Families

Decode Module Timing

A

B

C

D

E

Y

H

F

G

A–G, H

Y

50%

t

PHL

t

PLH

Figure 1-26 • Decode Module Timing

Read Port

Write Port

WRAD [5:0]

BLKEN

RDAD [5:0]

LEW

RAM Array

32x8 or 64x4

(256 Bits)

WEN

REN

WCLK

RCLK

WD [7:0]

RD [7:0]

Figure 1-27 • SRAM Timing Characteristics

1-22

v3.1

40MX and 42MX Automotive FPGA Families

Dual-Port SRAM Timing Waveforms

t_RCKHL

WCLK

t_ADSU

t_ADH

WD[7:0]

WRAD[5:0]

Valid

t_WENSU

t_WENH

WEN

t_BENSU

t_BENH

Valid

BLKEN

Note: Identical timing for falling edge clock.

Figure 1-28 • 42MX SRAM Write Operation

t_CKHL

t_RCKHL

RCLK

REN

t_RENSU

t_RENH

t_ADSU

Valid

t_ADH

RDAD[5:0]

t_RCO

t_DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling edge clock.

Figure 1-29 • 42MX SRAM Synchronous Read Operation

v3.1

1-23

40MX and 42MX Automotive FPGA Families

(Read Address Controlled)

t_RDADV

RDAD[5:0]

RD[7:0]

ADDR1

t_DOH

Data 1

ADDR2

t_RPD

Data 2

Figure 1-30 • 42MX SRAM Asynchronous Read Operation—Type 1

(Write Address Controlled)

WEN

t_WENSU

t_WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t_ADSU

t_ADH

WCLK

t_RPD

t_DOH

Old Data

New Data

RD[7:0]

Figure 1-31 • 42MX SRAM Asynchronous Read Operation—Type 2

1-24

v3.1

40MX and 42MX Automotive FPGA Families

Critical Nets and Typical Nets

Predictable Performance: Tight

Delay Distributions

Propagation delay between logic modules depends on

the resistive and capacitive loading of the routing tracks,

the interconnect elements, and the module inputs being

driven. Propagation delay increases as the length of

routing tracks, the number of interconnect elements, or

the number of inputs increases.

Propagation delays in this datasheet apply to typical

nets, which are used for initial design performance

evaluation. Critical net delays can then be applied to the

most timing critical paths. Critical nets are determined by

net property assignment in Actel's Designer software

prior to placement and routing. Up to 6% of the nets in

a design may be designated as critical.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout

(number of loads) driven by a module. Higher fanout

usually requires some paths to have longer routing

tracks.

Long Tracks

Some nets in the design use long tracks, which are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and

sometimes four antifuse connections, which increase

capacitance and resistance, resulting in longer net delays

for macros connected to long tracks. Typically, up to

6 percent of nets in a fully utilized device require long

tracks. Long tracks add approximately a 3 ns to a 6 ns

delay, which is represented statistically in higher fanout

(FO=8) routing delays in the datasheet specifications

section beginning on page 1-16.

The MX FPGAs deliver a tight fanout delay distribution,

which is achieved in two ways: by decreasing the delay of

the interconnect elements and by decreasing the number

of interconnect elements per path.

Actel’s patented antifuse offers a very low resistive/

capacitive interconnect. The antifuses, fabricated in

0.45 µ lithography, offer nominal levels of 100 Ω

resistance and 7.0 femtofarad (fF) capacitance per

antifuse.

Timing Derating

MX fanout distribution is also tight due to the low

number of antifuses required for each interconnect path.

The proprietary architecture limits the number of

antifuses per path to a maximum of four, with

90 percent of interconnects using only two antifuses.

MX devices are manufactured with a CMOS process.

Therefore, device performance varies according to

temperature, voltage and process changes. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature and best-case

processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating

temperature and worst-case processing.

Timing Characteristics

Device timing characteristics fall into three categories:

family-dependent, device-dependent, and design-

dependent. The input and output buffer characteristics

are common to all MX devices. Internal routing delays

are device-dependent. Design dependency means actual

delays are not determined until after place-and-route of

the user’s design is complete. Delay values may then be

determined by using the Timer tool in the Designer

software or by performing simulation with post-

layout delays.

v3.1

1-25

40MX and 42MX Automotive FPGA Families

Temperature and Voltage Derating Factors

Table 1-7 • 42MX Temperature and Voltage Derating Factors

(Normalized to T_J= 125°C, V_CCA/V_CCI= 4.75V)

Temperature

42MX

Voltage

–55°C

0.66

–40°C

0.67

0°C

0.74

0.72

0.70

25°C

0.78

0.75

0.73

70°C

0.89

0.87

0.84

85°C

0.91

0.89

0.86

125°C

1.00

4.75

5.00

5.25

0.64

0.65

0.97

0.62

0.64

0.94

42MX Derating Factor (Normalized to T = 125°C, V_CCA/V_CCI=4.75V)

J

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

-55°C

-40°C

0°C

25°C

70°C

85°C

125°C

4.75

5.00

5.25

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

Figure 1-32 • 42MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 125°C, V_CCA/V_CCI= 4.75V)

1-26

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-8 • 40MX Temperature and Voltage Derating Factors

(Normalized to T_J= 125°C, V_CC= 4.75V)

Temperature

25°C

40MX

Voltage

–55°C

0.62

0.60

0.58

–40°C

0.64

0.62

0.60

0°C

0.71

0.69

0.67

70°C

0.86

0.84

0.82

85°C

0.90

0.88

0.85

125°C

1.00

0.97

0.94

4.75

5.00

5.25

0.75

0.73

0.71

40MX Derating Factor (Normalized to T = 125°C, V_CC= 4.75V)

J

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

-55°C

-40°C

0°C

25°C

70°C

85°C

125°C

4.75

5.00

5.25

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

Figure 1-33 • 40MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 125°C, V_CC4.75V)

v3.1

1-27

40MX and 42MX Automotive FPGA Families

Timing Characteristics

The timing numbers in the datasheet represent sample timing characteristics of the devices. Refer to the Timer tool in

the Designer software for design-specific timing information.

Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CC= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Logic Module Propagation Delays¹

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

2.2

4.7

2.2

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.3

3.2

4.2

5.1

8.8

ns

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

Flip-Flop (Latch) Data Input Hold

5.4

0.0

5.4

0.0

5.8

8.7

ns

3

t_HD

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse

Flip-Flop (Latch)

ns

Flip-Flop Clock Input Period

Flip-Flop (Latch) Clock Frequency

ns

f_MAX

116

MHz

Input Module Propagation Delays

t_INYH

Pad-to-Y HIGH

1.3

1.2

ns

t_INYL

Pad-to-Y LOW

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.7

4.6

ns

5.6

6.5

10.2

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this

macro.

4. Delays based on 35 pF loading.

1-28

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CC= 4.75V, T_J= 125°C (Continued)

Std. Speed

Parameter

Description

Min.

Max.

Units

Global Clock Networks

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to HIGH

8.1

8.6

ns

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

Input High to LOW

ns

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

3.9

4.2

3.9

4.2

ns

0.7

0.9

ns

Minimum Period

8.3

8.7

ns

f_MAX

Maximum Frequency

120

116

MHz

TTL Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

5.9

7.1

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

6.7

ns

8.3

ns

14.1

10.4

0.03

0.05

ns

ns/pF

d_THL

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this

macro.

4. Delays based on 35 pF loading.

v3.1

1-29

40MX and 42MX Automotive FPGA Families

Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CC= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Logic Module Propagation Delays¹

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

2.2

4.7

2.2

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.4

3.4

4.3

5.2

9.0

ns

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

5.4

0.0

5.4

0.0

5.8

8.7

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse

Flip-Flop (Latch)

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

ns

Flip-Flop Clock Input Period

Flip-Flop (Latch) Clock Frequency

ns

f_MAX

116

MHz

Input Module Propagation Delays

t_INYH

Pad-to-Y HIGH

1.3

1.2

ns

t_INYL

Pad-to-Y LOW

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.7

4.6

ns

5.6

6.5

10.2

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this

macro.

4. Delays based on 35 pF loading.

1-30

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CC= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to HIGH

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

FO = 16

FO = 128

8.2

8.7

ns

Input High to LOW

ns

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

3.9

4.2

3.9

4.2

ns

0.7

0.9

ns

Minimum Period

8.3

8.7

ns

f_MAX

Maximum Frequency

120

116

MHz

TTL Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

5.9

7.1

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

6.7

ns

8.3

ns

14.1

10.4

0.03

0.05

ns

ns/pF

d_THL

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this

macro.

4. Delays based on 35 pF loading.

v3.1

1-31

40MX and 42MX Automotive FPGA Families

Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

2.0

2.1

2.0

2.4

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.1

1.6

1.9

2.2

3.8

ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.4

0.0

0.6

0.0

4.8

6.3

4.8

0.0

0.4

0.0

0.4

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

ns

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

ns

t_INH

Input Buffer Latch Hold

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

ns

Output Buffer Latch Hold

ns

Output Buffer Latch Set-Up

ns

Flip-Flop (Latch) Clock Frequency

174

MHz

Input Module Propagation Delays

t_INYH

t_INYL

tI_NGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.8

1.3

2.1

ns

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-32

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.4

3.8

4.2

4.6

6.2

ns

Global Clock Network

t_CKHInput Low to HIGH

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

FO = 32

FO = 256

4.0

4.5

5.8

6.4

ns

t_CKL

Input High to LOW

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

2.0

2.2

2.0

2.2

ns

0.6

ns

Input Latch External Setup

Input Latch External Hold

Minimum Period

0.0

3.9

4.4

5.3

5.8

ns

f_MAX

Maximum Frequency

192

174

MHz

TTL Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

4.0

4.8

4.4

ns

t_DHL

t_ENZH

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-33

40MX and 42MX Automotive FPGA Families

Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

Description

Min.

Max.

Units

ns

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.8

8.2

8.9

4.3

ns

t_GHL

G-to-Pad LOW

ns

t_LSU

I/O Latch Set-Up

I/O Latch Hold

0.8

0.0

ns

t_LH

ns

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Capacity Loading, LOW to HIGH

8.6

ns

t_ACO

12.2

0.04

0.06

ns

d_TLH

ns/pF

d_THL

Capacity Loading, HIGH to LOW

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-34

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

2.2

2.4

2.2

2.6

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.7

2.1

2.6

4.3

ns

Logic Module Sequential Timing^3,4

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.6

0.0

1.1

0.0

5.6

7.4

11.3

0.0

0.8

0.0

0.8

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

t_WASYN

t_A

ns

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Flip-Flop Clock Input Period

ns

t_INH

Input Buffer Latch Hold

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

ns

Output Buffer Latch Hold

ns

Output Buffer Latch Set-Up

ns

Flip-Flop (Latch) Clock Frequency

139

MHz

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.8

1.3

2.4

ns

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is

appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-35

40MX and 42MX Automotive FPGA Families

Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Min. Max.

Parameter

Description

Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.0

3.5

3.9

4.4

6.1

ns

Global Clock Network

t_CKHInput Low to HIGH

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

FO = 32

FO = 384

4.4

4.8

6.3

7.4

ns

t_CKL

Input High to LOW

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

5.3

6.1

5.3

6.1

ns

0.6

ns

Input Latch External Setup

Input Latch External Hold

Minimum Period

0.0

4.6

5.3

6.5

7.2

ns

f_MAX

Maximum Frequency

153

139

MHz

TTL Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

4.2

4.9

4.5

ns

t_DHL

t_ENZH

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is

appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-36

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

t_ENZL

Description

Min.

Max.

4.9

Units

ns

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

t_ENHZ

t_ENLZ

9.0

ns

8.3

ns

t_GLH

4.8

ns

t_GHL

G-to-Pad LOW

4.8

ns

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Capacity Loading, LOW to HIGH

9.4

ns

t_ACO

13.3

0.04

0.06

ns

d_TLH

ns/pF

d_THL

Capacity Loading, HIGH to LOW

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is

appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-37

40MX and 42MX Automotive FPGA Families

Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Min. Max.

Parameter

Description

Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

2.0

2.4

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

tR_D4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.4

1.7

2.2

2.5

4.1

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

Latch Gate-to-Output

2.2

2.0

ns

t_GO

t_SUD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.6

0.0

t_HD

t_RO

2.4

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.7

0.0

5.5

7.4

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.7

2.2

ns

0.0

0.8

7.8

t_INSU

t_ILA

Input Latch Set-Up

Latch Active Pulse Width

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-38

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.1

3.5

3.8

4.2

5.8

ns

Global Clock Network

t_CKHInput Low to HIGH

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

FO = 32

FO = 486

4.4

4.9

6.1

7.1

ns

t_CKL

Input High to LOW

ns

t_PWH

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

3.6

4.0

3.6

4.0

ns

t_PWL

ns

t_CKSW

t_SUEXT

t_HEXT

t_P

0.9

ns

Input Latch External Setup

Input Latch External Hold

Minimum Period

0.0

4.6

5.5

7.4

8.0

ns

f_MAX

Maximum Frequency

135

124

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-39

40MX and 42MX Automotive FPGA Families

Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Min. Max.

Parameter

Description

Units

TTL Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.1

4.8

4.3

4.8

8.6

8.0

4.9

ns

G-to-Pad LOW

ns

I/O Latch Set-Up

0.8

0.0

ns

t_LH

I/O Latch Hold

ns

t_LCO

t_ACO

d_TLH

d_THL

Notes:

I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading

Capacity Loading, LOW to HIGH

9.2

ns

17.8

0.06

0.05

ns

ns/pF

Capacity Loading, HIGH to LOW

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-40

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C

Std. Speed

Parameter

Description

Min.

Max.

Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

2.3

2.7

ns

t_PDD

Internal Decode Module Delay

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.6

2.2

2.7

3.3

5.5

0.6

ns

Decode-to-Output Routing Delay

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

2.2

ns

t_GO

Latch Gate-to-Output

t_SUD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

0.6

0.0

t_HD

t_RO

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

2.6

t_SUENA

t_HENA

t_WCLKA

t_WASYN

1.1

0.0

5.5

7.2

Synchronous SRAM Operations

t_RC

Read Cycle Time

11.3

5.7

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

5.7

t_ADSU

t_ADH

Notes:

2.7

0.0

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-41

40MX and 42MX Automotive FPGA Families

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C (Continued)

Std. Speed

Min.

Parameter

t_RENSU

t_RENH

Description

Max.

13.6

2.0

Units

ns

Read Enable Set-Up

Read Enable Hold

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

1.0

5.7

4.5

0.0

4.6

0.0

ns

t_WENSU

t_WENH

ns

t_BENS

ns

t_BENH

ns

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

ns

t_RDADV

t_ADSU

t_ADH

14.7

2.7

0.0

1.0

5.7

4.5

0.0

Address/Data Set-Up Time

Address/Data Hold Time

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Read Enable Set-Up to Address Valid

Read Enable Hold

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.7

2.4

ns

0.0

0.8

7.8

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

Notes:

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.3

3.8

4.4

5.0

7.2

ns

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-42

v3.1

40MX and 42MX Automotive FPGA Families

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C (Continued)

Std. Speed

Parameter

Description

Min.

Max.

Units

Global Clock Network

t_CKH

Input Low to HIGH

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

FO = 32

FO = 635

4.5

5.0

6.3

8.1

ns

t_CKL

Input High to LOW

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

2.9

3.3

2.9

3.3

ns

1.1

ns

Input Latch External Setup

Input Latch External Hold

Minimum Period

0.0

4.8

5.5

8.6

9.4

ns

f_MAX

Maximum Frequency

116

107

MHz

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

4.3

5.0

4.4

4.9

8.8

8.3

5.0

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

v3.1

1-43

40MX and 42MX Automotive FPGA Families

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)

Worst-Case Automotive Conditions, V_CCA= 4.75V, T_J= 125°C (Continued)

Std. Speed

Parameter

t_GHL

Description

Min.

Max.

Units

ns

G-to-Pad LOW

I/O Latch Set-Up

I/O Latch Hold

5.0

t_LSU

0.8

0.0

ns

t_LH

ns

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad), 32 I/O

Array Clock-to-Out (Pad-to-Pad), 32 I/O

Capacity Loading, LOW to HIGH

9.5

ns

t_ACO

13.0

0.11

ns

d_TLH

ns/pF

d_THL

Capacity Loading, HIGH to LOW

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer tool.

4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/

hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to

the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

1-44

v3.1

40MX and 42MX Automotive FPGA Families

Pin Descriptions

CLK/A/B, I/O

Global Clock

PRA/B, I/O

Probe

Clock inputs for clock distribution networks. CLK is for

40MX while CLKA and CLKB are for 42MX devices. The

clock input is buffered prior to clocking the logic

modules. This pin can also be used as an I/O.

The Probe pin is used to output data from any user-

defined design node within the device. Each diagnostic

pin can be used in conjunction with the other probe pin

to allow real-time diagnostic output of any signal path

within the device. The Probe pin can be used as a user-

defined I/O when verification has been completed. The

pin's probe capabilities can be permanently disabled to

protect programmed design confidentiality. The Probe

pin is accessible when the MODE pin is High. This pin

functions as an I/O when the MODE pin is Low.

DCLK, I/O

Diagnostic Clock

TTL clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin is

LOW.

GND

Ground

QCLKA,B,C,D, I/O Quadrant Clock

Input LOW supply voltage.

Quadrant clock inputs for A42MX36 devices. When not

used as a register control signal, these pins can function

as general-purpose I/Os.

I/O

Input/Output

Input, output, tristate, or bidirectional buffer. Input and

output levels are compatible with standard TTL

specifications. Unused I/O pins are configured by the

Designer software as shown in Table 1-15.

SDI, I/O

Serial Data Input

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is High.

This pin functions as an I/O when the MODE pin is Low.

Table 1-15 • Configuration of Unused I/Os

SDO, TDO, I/O

Serial Data Output

Device

Configuration

Pulled LOW

Tristated

Serial data output for diagnostic probe and device

programming. SDO is active when the MODE pin is High.

This pin functions as an I/O when the MODE pin is Low.

SDO is available for 42MX devices only.

A40MX02, A40MX04

A42MX09, A42MX16

A42MX24, A42MX36

When Silicon Explorer II is being used, SDO will act as an

output while the "checksum" is run. It will return to user

I/O when "checksum" is complete.

In all cases, it is recommended to tie all unused I/O pins

to LOW on the board. This applies to all dual-purpose

pins when configured as I/Os as well.

TCK, I/O

Test Clock

MODE

Mode

Clock signal to shift the Boundary Scan Test (BST) data

into the device. This pin functions as an I/O when

"Reserve JTAG" is not checked in the Designer software.

BST pins are only available in the A42MX24 and

A42MX36 devices.

Controls the use of multifunction pins (DCLK, PRA, PRB,

SDI, TDO). To provide verification capability, the MODE

pin should be held HIGH. To facilitate this, the MODE pin

should be tied to GND through a 10kΩ resistor so that

the MODE pin can be pulled HIGH when required.

TDI, I/O

Test Data In

NC

No Connection

Serial data input for BST instructions and data. Data is

shifted in on the rising edge of TCK. This pin functions as

an I/O when "Reserve JTAG" is not checked in the

Designer software. BST pins are only available in the

A42MX24 and A42MX36 devices.

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

v3.1

1-45

40MX and 42MX Automotive FPGA Families

TDO, I/O

Test Data Out

V

Supply Voltage

CC

Serial data output for BST instructions and test data. This

pin functions as an I/O when "Reserve JTAG" is not

checked in the Designer software. BST pins are only

available in the A42MX24 and A42MX36 devices.

Supply voltage for 40MX devices.

V

Supply Voltage

CCA

Supply voltage for array in 42MX devices.

V

Supply Voltage

TMS, I/O

Test Mode Select

CCI

Supply voltage for I/Os in 42MX devices.

The TMS pin controls the use of the IEEE 1149.1

Boundary Scan pins (TCK, TDI, TDO). In flexible mode

when the TMS pin is set LOW, the TCK, TDI and TDO pins

are boundary-scan pins. Once the boundary scan pins are

in test mode, they will remain in that mode until the

internal boundary scan state machine reaches the "logic

reset" state. At this point, the boundary scan pins will be

released and will function as regular I/O pins. The "logic

reset" state is reached five TCK cycles after the TMS pin is

set High. In dedicated test mode, TMS functions as

specified in the IEEE 1149.1 specifications. IEEE JTAG

specification recommends a 10kΩ pull-up resistor on the

pin. BST pins are only available in A42MX24 and

A42MX36 devices.

WD, I/O

Wide Decode Output

When a wide decode module is used in a an A42MX24 or

A42MX36 device, this pin can be used as a dedicated

output from the wide decode module. This direct

connection eliminates additional interconnect delays

associated with regular logic modules. To implement the

direct I/O connection, connect an output buffer of any

type to the output of the wide decode macro and place

this output on one of the reserved WD pins. When a

wide decode module is not used, this pin functions as a

regular I/O pin.

1-46

v3.1

40MX and 42MX Automotive FPGA Families

Package Pin Assignments

68-Pin PLCC

1 68

68-Pin

PLCC

Figure 2-1 • 68-Pin PLCC

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-1

40MX and 42MX Automotive FPGA Families

68-Pin PLCC

A40MX02 Function

Pin Number

A40MX02 Function

Pin Number

1

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

V_CCy

I/O

GND

I/O

V_CC

I/O

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

I/O

2

3

I/O

4

GND

I/O

5

6

I/O

7

CLK, I/O

I/O

8

9

MODE

V_CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

GND

I/O

2-2

v3.1

40MX and 42MX Automotive FPGA Families

84-Pin PLCC

1 84

84-Pin

PLCC

Figure 2-2 • 84-Pin PLCC

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-3

40MX and 42MX Automotive FPGA Families

84-Pin PLCC

Number

A40MX04

Function

A42MX09

Function

Number

A40MX04

Function

A42MX09

Function

1

I/O

V_CC

I/O

NC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

CLKB, I/O

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

I/O

V_CCA

I/O

2

3

I/O

4

PRB, I/O

I/O

V_CC

I/O

5

I/O

6

GND

I/O

7

I/O

GND

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

DCLK, I/O

I/O

SDO, I/O

I/O

MODE

I/O

GND

I/O

GND

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

CLK, I/O

I/O

MODE

V_CC

I/O

GND

I/O

GND

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

SDI, I/O

I/O

PRA, I/O

I/O

GND

I/O

CLKA, I/O

V_CCA

I/O

2-4

v3.1

40MX and 42MX Automotive FPGA Families

100-Pin PQFP

100-Pin

PQFP

100

1

Figure 2-3 • 100-Pin PQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-5

40MX and 42MX Automotive FPGA Families

100-Pin PQFP

A40MX02

Function

A40MX04

Function

A42MX09

Function

A40MX02

A40MX04

Function

A42MX09

Function

Pin Number

Function

GND

I/O

1

NC

PRB, I/O

I/O

NC

PRB, I/O

I/O

DCLK, I/O

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

GND

I/O

2

3

I/O

4

MODE

I/O

5

I/O

V_CCA

I/O

6

I/O

7

I/O

8

I/O

V_CC

I/O

V_CC

I/O

9

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

GND

I/O

GND

I/O

GND

I/O

NC

V_CC

I/O

V_CCA

V_CCI

I/O

NC

V_CC

I/O

SDO, I/O

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

V_CCA

V_CCI

V_CCA

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

2-6

v3.1

40MX and 42MX Automotive FPGA Families

100-Pin PQFP

A40MX02

Function

A40MX04

Function

A42MX09

Function

Pin Number

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

GND

I/O

NC

I/O

NC

I/O

NC

SDI, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

CLKA, I/O

V_CCA

I/O

CLK, I/O

I/O

CLK, I/O

I/O

MODE

V_CC

NC

MODE

V_CC

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

NC

I/O

GND

I/O

NC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

SDI, I/O

DCLK, I/O

PRA, I/O

I/O

v3.1

2-7

40MX and 42MX Automotive FPGA Families

160-Pin PQFP

160

1

160-Pin

PQFP

Figure 2-4 • Pin PQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

2-8

v3.1

40MX and 42MX Automotive FPGA Families

160-Pin PQFP

A42MX09

Function

A42MX24

Function

A42MX09

Function

A42MX24

Function

Pin Number

1

I/O

DCLK, I/O

NC

I/O

DCLK, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

2

3

I/O

4

I/O

WD, I/O

V_CCI

GND

I/O

GND

I/O

5

I/O

6

NC

I/O

7

I/O

8

I/O

9

I/O

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

NC

I/O

GND

NC

GND

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

V_CCA

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

V_CCI

GND

V_CCA

GND

I/O

V_CCA

V_CCI

GND

V_CCA

GND

TCK, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

V_CCA

CLKA, I/O

I/O

V_CCA

CLKA, I/O

I/O

PRA, I/O

NC

PRA, I/O

WD, I/O

I/O

GND

I/O

GND

I/O

NC

I/O

WD, I/O

GND

NC

I/O

GND

I/O

GND

NC

WD, I/O

I/O

NC

V_CCI

NC

I/O

WD, I/O

SDI, I/O

I/O

NC

I/O

SDI, I/O

I/O

NC

GND

I/O

GND

v3.1

2-9

40MX and 42MX Automotive FPGA Families

160-Pin PQFP

A42MX09

Function

A42MX24

Function

A42MX09

Function

A42MX24

Function

Pin Number

81

82

I/O

SDO, I/O

I/O

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

I/O

SDO, TDO, I/O

WD, I/O

I/O

83

I/O

84

I/O

NC

GND

I/O

85

I/O

GND

I/O

86

NC

I/O

V_CCI

87

I/O

88

I/O

WD, I/O

GND

I/O

89

GND

NC

I/O

NC

GND

I/O

90

GND

I/O

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

NC

I/O

V_CCA

I/O

96

I/O

WD, I/O

I/O

97

I/O

98

V_CCA

GND

NC

I/O

V_CCA

GND

I/O

NC

V_CCI

GND

NC

I/O

V_CCA

V_CCI

GND

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

NC

I/O

GND

NC

I/O

GND

I/O

WD, I/O

I/O

GND

NC

I/O

GND

I/O

NC

GND

I/O

V_CCA

I/O

WD, I/O

I/O

NC

I/O

V_CCI

I/O

WD, I/O

I/O

GND

I/O

NC

I/O

TDI, I/O

TMS, I/O

GND

I/O

MODE

GND

MODE

GND

2-10

v3.1

40MX and 42MX Automotive FPGA Families

80-Pin VQFP

80

1

80-Pin

VQFP

Figure 2-5 • 80-Pin VQFP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-11

40MX and 42MX Automotive FPGA Families

80-Pin VQFP

A40MX02

Function

A40MX04

Function

A40MX02

Function

A40MX04

Function

Pin Number

44

1

I/O

NC

I/O

GND

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

NC

I/O

2

I/O

45

3

I/O

46

I/O

4

I/O

47

GND

I/O

GND

I/O

5

I/O

48

6

I/O

49

I/O

7

GND

I/O

50

CLK, I/O

I/O

CLK, I/O

I/O

8

51

9

I/O

52

MODE

V_CC

NC

MODE

V_CC

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

I/O

53

I/O

54

I/O

55

NC

I/O

V_CC

I/O

56

NC

I/O

57

SDI, I/O

DCLK, I/O

PRA, I/O

NC

SDI, I/O

DCLK, I/O

PRA, I/O

NC

I/O

58

I/O

59

I/O

60

I/O

61

PRB, I/O

I/O

PRB, I/O

I/O

62

V_CC

I/O

63

I/O

64

I/O

65

I/O

66

I/O

67

I/O

68

GND

I/O

GND

I/O

69

GND

I/O

70

I/O

71

I/O

72

I/O

73

I/O

74

V_CC

I/O

V_CC

I/O

75

V_CC

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

I/O

2-12

v3.1

40MX and 42MX Automotive FPGA Families

208-Pin PQFP

208

1

208-Pin PQFP

Figure 2-6 • 208-Pin PQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-13

40MX and 42MX Automotive FPGA Families

208-Pin PQFP

A42MX16

Function

A42MX24

Function

A42MX36

Function

A42MX16

Function

A42MX24

Function

A42MX36

Function

Pin Number

1

GND

NC

MODE

I/O

GND

V_CCA

MODE

I/O

GND

V_CCA

MODE

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

NC

I/O

7

I/O

8

I/O

9

NC

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

NC

I/O

NC

GND

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

WD, I/O

I/O

WD, I/O

I/O

V_CCI

NC

I/O

V_CCI

I/O

V_CCI

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

QCLKA, I/O

WD, I/O

I/O

WD, I/O

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

WD, I/O

2-14

v3.1

40MX and 42MX Automotive FPGA Families

208-Pin PQFP

A42MX16

Function

A42MX24

Function

A42MX36

Function

A42MX16

Function

A42MX24

Function

A42MX36

Function

Pin Number

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

I/O

WD, I/O

I/O

WD, I/O

I/O

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

NC

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

GND

V_CCA

NC

GND

V_CCA

V_CCI

I/O

GND

V_CCA

V_CCI

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

NC

I/O

QCLKB, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

WD, I/O

I/O

WD, I/O

I/O

TCK, I/O

GND

V_CCA

GND

V_CCI

V_CCA

I/O

TCK, I/O

GND

V_CCA

GND

V_CCI

V_CCA

I/O

GND

V_CCA

GND

V_CCI

V_CCA

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

WD, I/O

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

SDO, I/O

I/O

SDO, TDO, I/O SDO, TDO, I/O

I/O

GND

I/O

v3.1

2-15

40MX and 42MX Automotive FPGA Families

208-Pin PQFP

A42MX16

Function

A42MX24

Function

A42MX36

Function

A42MX16

Function

A42MX24

Function

A42MX36

Function

Pin Number

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

NC

I/O

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

WD, I/O

PRA, I/O

I/O

WD, I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

NC

CLKA, I/O

I/O

CLKA, I/O

I/O

NC

GND

I/O

NC

V_CCI

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

GND

I/O

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

NC

WD, I/O

I/O

WD, I/O

QCLKC, I/O

I/O

NC

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

V_CCI

NC

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

QCLKD, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

2-16

v3.1

40MX and 42MX Automotive FPGA Families

240-Pin PQFP

240

1

•

240-Pin

PQFP

Figure 2-7 • 240-Pin PQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-17

40MX and 42MX Automotive FPGA Families

240-Pin PQFP

Number

A42MX36

Function

A42MX36

Function

Number

A42MX36

Function

Number

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

1

I/O

DCLK, I/O

I/O

81

I/O

2

82

3

I/O

83

I/O

4

I/O

84

I/O

5

I/O

QCLKD, I/O

I/O

85

V_CCA

I/O

6

WD, I/O

V_CCI

86

7

WD, I/O

I/O

87

I/O

8

88

V_CCA

V_CCI

V_CCA

GND

TCK, I/O

I/O

9

I/O

89

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I/O

90

I/O

91

I/O

V_CCI

I/O

92

I/O

93

I/O

WD, I/O

I/O

94

GND

I/O

QCLKC, I/O

I/O

95

96

I/O

WD, I/O

I/O

SDI, I/O

I/O

97

I/O

98

I/O

V_CCA

GND

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

WD, I/O

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

GND

V_CCA

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

CLKA, I/O

I/O

PRA, I/O

I/O

WD, I/O

I/O

V_CCA

GND

I/O

2-18

v3.1

40MX and 42MX Automotive FPGA Families

240-Pin PQFP

A42MX36

Function

A42MX36

Function

Number

A42MX36

Function

Number

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

Number

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

GND

I/O

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

I/O

SDO, TDO, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

QCLKA, I/O

I/O

V_CCA

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

WD, I/O

I/O

V_CCI

I/O

WD, I/O

I/O

QCLKB, I/O

I/O

TDI, I/O

TMS, I/O

GND

V_CCA

GND

I/O

V_CCA

I/O

WD, I/O

I/O

V_CCI

I/O

V_CCI

V_CCA

GND

I/O

V_CCI

I/O

GND

MODE

V_CCA

GND

I/O

WD, I/O

I/O

v3.1

2-19

40MX and 42MX Automotive FPGA Families

100-Pin VQFP

100

1

100-Pin

VQFP

Figure 2-8 • 100-Pin VQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

2-20

v3.1

40MX and 42MX Automotive FPGA Families

100-Pin VQFP

A42MX09

Function

A42MX16

Function

A42MX09

Function

A42MX16

Function

Pin Number

1

I/O

MODE

I/O

MODE

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

2

3

V_CCA

I/O

V_CCA

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

GND

I/O

8

I/O

9

I/O

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

V_CCA

V_CCI

I/O

NC

V_CCI

I/O

SDO, I/O

I/O

SDO, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

V_CCA

V_CCI

V_CCA

I/O

GND

V_CCA

V_CCI

V_CCA

I/O

GND

I/O

GND

I/O

GND

v3.1

2-21

40MX and 42MX Automotive FPGA Families

100-Pin VQFP

A42MX09

Function

A42MX16

Function

Pin Number

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

V_CCA

I/O

CLKA, I/O

V_CCA

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

DCLK, I/O

2-22

v3.1

40MX and 42MX Automotive FPGA Families

176-Pin TQFP

176

1

176-Pin

TQFP

Figure 2-9 • 176-Pin TQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v3.1

2-23

40MX and 42MX Automotive FPGA Families

176-Pin TQFP

A42MX09

Function

A42MX16

Function

A42MX24

Function

A42MX09

Function

A42MX16

Function

A42MX24

Function

Pin Number

1

GND

MODE

I/O

GND

MODE

I/O

GND

MODE

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

NC

I/O

GND

I/O

V_CCI

I/O

NC

I/O

GND

V_CCA

I/O

2

NC

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

NC

I/O

NC

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

NC

I/O

GND

I/O

GND

TMS, I/O

TDI, I/O

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

WD, I/O

I/O

NC

I/O

V_CCI

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

I/O

WD, I/O

I/O

NC

GND

NC

V_CCA

NC

V_CCI

NC

I/O

NC

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

WD, I/O

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

GND

V_CCA

I/O

GND

V_CCA

WD, I/O

NC

I/O

NC

I/O

2-24

v3.1

40MX and 42MX Automotive FPGA Families

176-Pin TQFP

A42MX09

Function

A42MX16

Function

A42MX24

Function

A42MX09

Function

A42MX16

Function

A42MX24

Function

Pin Number

71

Pin Number

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

I/O

GND

NC

LP

GND

I/O

GND

I/O

72

I/O

73

I/O

TCK, I/O

LP

74

NC

I/O

LP

75

I/O

V_CCA

GND

V_CCI

V_CCA

NC

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

V_CCA

GND

V_CCI

V_CCA

I/O

76

I/O

77

NC

I/O

NC

I/O

WD, I/O

I/O

78

79

I/O

80

NC

I/O

81

I/O

V_CCA

I/O

V_CCA

I/O

82

NC

I/O

V_CCI

I/O

V_CCI

I/O

83

I/O

84

I/O

WD, I/O

I/O

85

I/O

86

NC

SDO, I/O

I/O

NC

I/O

NC

I/O

87

SDO, I/O

I/O

SDO, TDO, I/O

I/O

88

I/O

89

GND

I/O

GND

I/O

GND

I/O

NC

I/O

90

I/O

91

I/O

NC

I/O

92

I/O

93

I/O

94

I/O

95

I/O

96

NC

I/O

97

I/O

98

I/O

GND

I/O

GND

I/O

GND

I/O

99

I/O

100

101

102

103

104

105

I/O

SDI, I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

NC

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

NC

V_CCI

v3.1

2-25

40MX and 42MX Automotive FPGA Families

176-Pin TQFP

A42MX09

Function

A42MX16

Function

A42MX24

Function

A42MX09

Function

A42MX16

Function

A42MX24

Function

Pin Number

141

Pin Number

159

I/O

PRB, I/O

I/O

PRB, I/O

WD, I/O

I/O

142

160

PRB, I/O

NC

143

NC

I/O

161

144

NC

I/O

WD, I/O

I/O

162

I/O

145

NC

163

I/O

146

I/O

164

I/O

147

NC

I/O

165

NC

WD, I/O

I/O

148

I/O

166

NC

I/O

149

I/O

167

I/O

150

I/O

WD, I/O

PRA, I/O

I/O

168

NC

I/O

151

NC

I/O

169

I/O

152

PRA, I/O

I/O

PRA, I/O

I/O

170

NC

V_CCI

I/O

V_CCI

153

171

I/O

WD, I/O

I/O

154

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

172

I/O

155

173

NC

I/O

156

174

I/O

157

I/O

175

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

158

CLKB, I/O

176

2-26

v3.1

40MX and 42MX Automotive FPGA Families

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version v3.1

A note was added to the "Ordering Information".

Page

v3.0

ii

April 2004

v2.0

Note 1 was added to "Recommended Operating Conditions".

The "Speed Grade and Temperature Grade Matrix" table is new.

The "Clock Networks" section was updated.

The "I/O Modules" section was updated.

1-12

page 1-ii

page 1-4

page 1-5

page 1-11

page 1-12

page 1-15

page 1-16

page 1-17

page 1-18

page 1-25

page 1-26

page 1-27

The "Other Architectural Features" section is new

The "Development Tool Support" section was updated.

The "Electrical Specifications" table was updated.

The "Junction Temperature" section was updated.

Table 1-6 was updated.

Figure 1-15 and Figure 1-16 were updated.

Figure 1-17 was updated.

Figure 1-18 was updated.

The "Critical Nets and Typical Nets" section was updated.

The "Timing Derating" section is new.

Table 1-7 and Figure 1-32 were updated.

Table 1-8 and Figure 1-33 were updated.

All timing numbers contained in Table 1-9 through Table 1-14 were updated.

page1-28 to

page 1-41

The "Pin Descriptions" section was updated.

page 1-45

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The

definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a advanced datasheet (advanced or production) containing general

product information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Unmarked (production)

This datasheet version contains information that is considered to be final.

v3.1

3-1

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

www.jp.actel.com

Actel Hong Kong

www.actel.com.cn

2061 Stierlin Court

Mountain View, CA

94043-4655 USA

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Suite 2114, Two Pacific Place

88 Queensway, Admiralty

Hong Kong

Phone 650.318.4200

Fax 650.318.4600

Phone +44 (0) 1276 401 450

Fax +44 (0) 1276 401 490

Phone +81.03.3445.7671

Fax +81.03.3445.7668

Phone +852 2185 6460

Fax +852 2185 6488

51700025-2/5.06


型号：	A40MX02-VQ208A
厂家：	Actel Corporation
描述：	40MX and 42MX Automotive FPGA Families 40MX和42MX汽车FPGA系列
文件：	总78页 (文件大小：537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A40MX02-VQ208A [ACTEL]

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