A3PE3000L-1FG896 [ACTEL]
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 250MHz, 75264-Cell, CMOS, PBGA896, 31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-896;
| 型号： | A3PE3000L-1FG896 |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 250MHz, 75264-Cell, CMOS, PBGA896, 31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-896 时钟 栅 可编程逻辑 |
| 文件： | 总224页 (文件大小：7287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Revision 9
®
ProASIC3L Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
•
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os Programmable Output
Slew Rate and Drive Strength
Low Power
•
•
•
•
•
Dramatic Reduction in Dynamic and Static Power Savings
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry to / Exit from Low-Power Flash*Freeze
Mode
•
•
•
•
Supports Single-Voltage System Operation
Low-Impedance Switches
High Capacity
•
•
•
250,000 to 3,000,000 System Gates
Up to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
•
•
Reprogrammable Flash Technology
•
•
•
•
•
Programmable Input Delay (A3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
Weak Pull-Up/-Down
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
•
•
•
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
IEEE 1149.1 (JTAG) Boundary Scan Test
®
Pin-Compatible Packages across the ProASIC 3L Family
Retains Programmed Design when Powered Off
(except PQ208)
High Performance
Clock Conditioning Circuit (CCC) and PLL
•
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
•
•
•
Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All
with Integrated PLL (ProASIC3EL)
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems))
•
In-System Programming (ISP) and Security
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
SRAMs and FIFOs
®
•
FlashLock to Secure FPGA Contents
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
High-Performance Routing Hierarchy
•
•
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous
Operation:
•
•
•
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
– 250 MHz: For 1.2 V systems
Advanced and Pro (Professional) I/Os
– 350 MHz: For 1.5 V systems
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
ARM® Processor Support in ProASIC3L FPGAs
•
ARM Cortex™-M1 Soft Processor Available with or without
Debug
Table 1 • ProASIC3 Low-Power Product Family
ProASIC3L Devices
ARM Cortex-M1 Devices
System Gates
A3P250L
A3P600L
A3P1000L
A3PE3000L
1
M1A3P600L
M1A3P1000L
M1A3PE3000L
250,000
600,000
13,824
108
24
1,000,000
3,000,000
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
6,144
36
8
24,576
144
32
75,264
504
112
1
FlashROM Kbits
1
1
1
2
Secure (AES) ISP
Yes
1
Yes
1
Yes
1
Yes
6
3
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
18
4
18
18
18
4
4
8
Maximum User I/Os
157
235
300
620
Package Pins
VQFP
VQ100
PQ208
FG144, FG256
3
PQFP
PQ208
FG144, FG256, FG484
PQ208
FG144, FG256, FG484
PQ208
FBGA
FG324, FG484, FG896
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
February 2009
I
© 2010 Actel Corporation
ProASIC3 nano Flash FPGAs
1
I/Os Per Package
ProASIC3L
Low-Power
Devices
A3P250L 2
A3P600L
A3P1000L
A3PE3000L
ARM
Cortex-M1
Devices
M1A3P600L
M1A3P1000L
M1A3PE3000L 3
I/O Type
Single-
Differential
I/O Pairs
Single-
Differential
I/O Pairs
Single-
Differential
I/O Pairs
Single-
Differential
I/O Pairs
Package
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
Ended I/O 4
Ended I/O 4
Ended I/O 4
Ended I/O 4
68
151
97
157
–
13
34
24
38
–
–
35
25
43
–
–
154
97
177
–
–
35
25
44
–
–
–
154
97
177
–
147
65
–
–
221
341
620
110
168
310
–
–
235
–
60
–
300
–
74
–
–
–
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to
ensure you are complying with design and board migration requirements.
2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.
3. ARM Cortex-M1 support is TBD on this device.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. FG256 and FG484 are footprint-compatible packages.
6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the
part number.
7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
Table 2 • ProASIC3L FPGAs Package Sizes Dimensions
Package
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Length × Width
(mm\mm)
14 × 14
28 × 28
13 × 13
17 × 17
19 × 19
23 × 23
31 × 31
Nominal Area
(mm2)
196
784
169
289
361
529
961
Pitch (mm)
0.5
0.5
1.0
1.0
1.0
1.0
1.0
Height (mm)
1.00
3.40
1.45
1.60
1.63
2.23
2.23
II
Revision 9
ProASIC3L Low Power Flash FPGAs
ProASIC3L Ordering Information
_
A3P1000L
1
FG
G
144
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
=
=
=
VQ
PQ
FG
Very Thin Quad Flat Pack (0.5 mm pitch)
Plastic Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
ProASIC3L Devices
A3P250L = 250,000 System Gates
A3P600L = 600,000 System Gates
A3P1000L = 1,000,000 System Gates
A3PE3000L= 3,000,000 System Gates
ProASIC3L Devices with Cortex-M1
M1A3P600L = 600,000 System Gates
M1A3P1000L = 1,000,000 System Gates
M1A3PE3000L = 3,000,000 System Gates
ProASIC3L Device Status
ProASIC3L Devices
Status
Advance
Advance
Advance
Advance
ARM Cortex-M1 Devices
Status
A3P250L
A3P600L
M1A3P600L
M1A3P1000L
M1A3PE3000L
Advance
Advance
Advance
A3P1000L
A3PE3000L
Revision 9
III
ProASIC3 nano Flash FPGAs
Temperature Grade Offerings
Package
ARM Cortex-M1 Devices
VQ100
A3P250L
A3P600L
A3P1000L
A3PE3000L
M1A3P600L
M1A3P1000L
M1A3PE3000L
C, I
C, I
C, I
C, I
–
–
–
PQ208
C, I
C, I
C, I
–
C, I
C, I
C, I
–
C, I
FG144
FG256
FG324
C, I
C, I
C, I
FG484
–
C, I
–
C, I
–
FG896
–
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Speed Grade and Temperature Grade Matrix
Temperature Grade
Std.
✓
–1
✓
✓
C 1
I 2
✓
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
http://www.actel.com/contact/default.aspx.
IV
Revision 9
ProASIC3L Low Power Flash FPGAs
Table of Contents
ProASIC3L Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3L DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-128
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-143
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-144
Package Pin Assignments
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Revision 9
V
1 – ProASIC3L Device Family Overview
General Description
The ProASIC3L family of Actel flash FPGAs dramatically reduces dynamic power consumption by 40%
and static power by 50%. These power savings are coupled with performance, density, true single-chip,
1.2 V to 1.5 V core and I/O operation as low as 1.2 V, reprogrammability, and advanced features.
Using Actel's proven Flash*Freeze technology enables users to shut off dynamic power instantaneously
and switch the device to static mode without the need to switch off clocks or power supplies while
retaining internal states of the device. This greatly simplifies power management on a board done
through I/Os and clocks. In addition, optimized software tools using power-driven layout provide instant
push-button power reduction.
Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power,
single-chip solution that is live at power-up (LAPU). ProASIC3L offers dramatic dynamic power savings
giving the FPGA users flexibility to combine low power with high performance.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). ProASIC3L devices
support devices from 250 k system gates to 3 million system gates with up to 504 kbits of true dual-port
SRAM and 620 user I/Os.
M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM
for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in the FPGA
fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and
speed when implemented in an M1 ProASIC3L device. The processor runs the ARMv6-M instruction set,
has a configurable nested interrupt controller, and can be implemented with or without the debug block.
ARM Cortex-M1 is available for free from Actel for use in M1 ProASIC3L FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support AES
decryption.
Flash*Freeze Technology
The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which allows instantaneous
switching from an active state to a static state. ProASIC3L devices do not need additional components to
turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V) allows for an even greater
reduction in power consumption, which enables low total system power.
When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is
retained.
The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage
solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in portable
media, secure communications, radio applications as well as high performance portable, industrial, test,
scientific, and medical applications.
Revision 9
1-1
ProASIC3L Device Family Overview
Flash Advantages
Low Power
The ProASIC3L family of Actel flash-based FPGAs provide a low-power advantage, and when coupled
with high performance, enables designers to make power-smart choices using a single-chip,
reprogrammable, and live-at-power-up device.
ProASIC3L devices offer 40% dynamic power and 50% static power savings by reducing the core
operating voltage to 1.2 V. In addition, the Power Driven Layout (PDL) feature in Libero® Integrated
Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze technology,
ProASIC3L is able to retain device SRAM and logic while dynamic power is reduced to a minimum,
without the need to stop clock or power supplies. Combining these features provides a low-power,
feature-rich and high-performance solution.
Security
Nonvolatile, flash-based ProASIC3L devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead, advantages
that only an FPGA with nonvolatile flash programming can offer.
ProASIC3L devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in ProASIC3L devices can be
encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption
standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and
replaces the 1977 DES standard. ProASIC3L devices have a built-in AES decryption engine and a flash-
based AES key that make them the most comprehensive programmable logic device security solution
available today. ProASIC3L devices with AES-based security allow for secure, remote field updates over
public networks such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. The contents of a programmed device cannot be read
back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3L family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. The ProASIC3L family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
and secure, making remote ISP possible. A ProASIC3L device provides the most impenetrable security
for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3L FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Live at Power-Up
The Actel flash-based ProASIC3L devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor wakes
up, setup and configuration of memory blocks, clock generation, and bus activity management. The
LAPU feature of flash-based ProASIC3L devices greatly simplifies total system design and reduces total
system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and
brownouts in system power will not corrupt the ProASIC3L device's flash configuration, and unlike
SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This
enables the reduction or complete removal of the configuration PROM, expensive voltage monitor,
brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3L devices
simplify total system design and reduce cost and design risk while increasing system reliability and
improving system initialization time.
1-2
Revision 9
ProASIC3L Low Power Flash FPGAs
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3L devices allow all functionality to be live at power-up; no external
boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The ProASIC3L family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the ProASIC3L family a cost-effective ASIC replacement
solution, manipulation in portable media and secure communications, radio applications as well as high
performance portable Industrial, test, scientific and medical applications.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The ProASIC3L family offers many benefits, including nonvolatility and reprogrammability, through an
advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3L architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3L device consists of five distinct and programmable architectural features (Figure 1-1 on
page 1-4 and Figure 1-2 on page 1-4):
•
•
•
•
•
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT)
equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs. VersaTiles
are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout
the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming
of ProASIC3L devices via an IEEE 1532 JTAG interface.
Revision 9
1-3
ProASIC3L Device Family Overview
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(A3P600L and A3P1000L)
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 2
Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and
A3P1000L)
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Pro I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Figure 1-2 • ProASIC3EL Device Architecture Overview
1-4
Revision 9
ProASIC3L Low Power Flash FPGAs
Flash*Freeze Technology
The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to
instantaneously shut off dynamic power consumption while retaining all SRAM and register information.
Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by
activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition,
I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks
can still be driven or can be toggling without impact on power consumption; and the device retains all
core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can
be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is
consumed by the I/O banks, clocks, JTAG pins, or PLL. Flash*Freeze technology allows the user to
switch to active mode on demand, thus simplifying the power management of the device.
The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is
safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode
usage is not planned, which is advantageous because of the inherent low-power static and dynamic
capabilities of the ProASIC3L device. Refer to Figure 1-3 for an illustration of entering/exiting
Flash*Freeze mode.
Actel ProASIC3L
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-3 • ProASIC3L Flash*Freeze Mode
VersaTiles
The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The ProASIC3L VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-4 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-4 • VersaTile Configurations
Revision 9
1-5
ProASIC3L Device Family Overview
User Nonvolatile FlashROM
Actel ProASIC3L devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet Protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3L IEEE 1532 JTAG programming interface.The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for a
user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel ProASIC3L development software solutions, Libero IDE and Designer, have extensive support
for the FlashROM. One such feature is auto-generation of sequential programming files for applications
requiring a unique serial number in each part. Another feature allows the inclusion of static data for
system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero
IDE and Designer software tools. Comprehensive programming file support is also included to allow for
easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit port and
read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each
member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
1-6
Revision 9
ProASIC3L Low Power Flash FPGAs
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
•
•
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used
•
•
•
Maximum acquisition time is 300 µs
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC
Global Clocking
ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The ProASIC3L family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O standards,
including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized
into banks, with two, four, or eight (ProASIC3EL only) banks per device. The configuration of these banks
determines the I/O standards supported. For ProASIC3EL, each I/O bank is subdivided into VREF
minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os
in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is
configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up
to 20 loads.
Wide Range I/O Support
Actel ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support
both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of
2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to
1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the
flexibility to easily run custom voltage applications.
Revision 9
1-7
2 – ProASIC3L DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
V
V
V
V
V
VJTAG
VPUMP
Programming voltage
VCCPLL Analog power supply (PLL)
VCCI and DC I/O buffer supply voltage
VMV 3
VI
I/O input voltage
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
V
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+125
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
3. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter in the ProASIC3L
FPGA Fabric User’s Guide for further information.
Revision 9
2-1
ProASIC3L DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 1
Symbol
TA
Parameter
Commercial
0 to +70
Industrial
–40 to +85
–40 to +100
1.14 to 1.575
1.4 to 3.6
Units
°C
°C
V
Ambient temperature
Junction Temperature
TJ
0 to + 85
VCC 2
VJTAG
VPUMP 3
1.2 V–1.5 V wide range core voltage
JTAG DC voltage
1.14 to 1.575
1.4 to 3.6
V
Programming voltage
Programming Mode
Operation 3
3.15 to 3.45
0 to 3.45
3.15 to 3.45
0 to 3.45
V
V
VCCPLL 6
Analog power supply (PLL)
1.2 V–1.5 V wide range 1.14 to 1.575
core voltage
1.14 to 1.575
V
VCCI
and 1.2 V DC supply voltage4
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V wide range DC supply voltage7
3.3 V DC supply voltage
LVDS differential I/O
1.14 to 1.26
1.14 to 1.26
V
V
V
V
V
V
V
V
VMV 5
1.425 to 1.575 1.425 to 1.575
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
1.7 to 1.9
2.3 to 2.7
2.7 to 3.6
3.0 to 3.6
2.375 to 2.625 2.375 to 2.625
3.0 to 3.6 3.0 to 3.6
LVPECL differential I/O
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-13 on page 2-10. V should be at the same voltage within a given I/O bank.
CCI
3.
V
can be left floating during normal operation (not programming mode).
PUMP
®
4. For ProASIC 3L devices, V
≥ V
.
CCI
CC
5. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the ProASIC3L
FPGA Fabric User’s Guide for further information.
6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the ProASIC3L FPGA Fabric User’s
Guide for further information.
7. 3.3 V wide range is compliant to the JDEC8a specification and supports 3.0 V V
operation.
CCI
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1
Programmin
Product
Grade
g
Program Retention
Maximum Storage
Maximum Operating
Cycles
(biased/unbiased) Temperature TSTG (°C) 2 Junction Temperature TJ (°C) 2
Commercial
Industrial
Notes:
500
500
20 years
20 years
110
110
100
100
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or Undershoot
Maximum Overshoot/
Undershoot2
VCCI
Duration as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at junction temperature at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of
two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4 and Figure 2-2 on page 2-5.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and
Figure 2-2 on page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Revision 9
2-3
ProASIC3L DC and Switching Characteristics
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-
2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low-Power Flash Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
VCCI
Activation trip point:
Min VCCI datasheet specification
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Revision 9
ProASIC3L Low Power Flash FPGAs
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
Va = 0.85 V ± 0.2 V
Deactivation trip point:
Vd = 0.75 V ± 0.2 V
Region 1: I/O buffers are OFF
VCCI
Activation trip point:
Va = 0.9 V ± 0.15 V
Deactivation trip point:
Vd = 0.8 V ± 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Revision 9
2-5
ProASIC3L DC and Switching Characteristics
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction temperature to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
EQ 1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is
θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum junction
temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (°C) – Max. ambient temp. (°C)
100°C – 70°C
20.5°C/W
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.463 W
θja(°C/W)
EQ 2
Table 2-5 • Package Thermal Resistivities
θja
Package Type
Device
Pin Count θjc Still Air 200 ft./min. 500 ft./min. Units
Very Thin Quad Flat Pack (VQFP)
Plastic Quad Flat Pack (PQFP)
PQFP with embedded heatspreader
Fine Pitch Ball Grid Array (FBGA)
All devices
All devices
All devices
A3P250L
100
208
208
144
144
144
256
256
256
324
484
484
484
896
10.0
8.0
35.3
26.1
16.2
43.8
35.8
31.6
38.6
32.0
28.1
TBD
27.5
23.3
20.6
13.6
29.4
22.5
13.3
37.7
30.2
26.2
34.7
27.5
24.4
TBD
21.9
19.0
15.7
10.4
27.1
20.8
11.9
35.8
28.3
24.2
33.0
25.8
22.7
TBD
20.2
16.7
14.0
9.4
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
3.8
12.2
8.3
A3P600L
A3P1000L
A3P250L
6.3
12.0
8.5
A3P600L
A3P1000L
AGLE3000
A3P600L
6.6
TBD
9.5
A3P1000L
A3PE3000L
A3PE3000L
8.0
4.7
2.4
2-6
Revision 9
ProASIC3L Low Power Flash FPGAs
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.14 V)
Junction Temperature (°C)
Array Voltage VCC (V)
–40°C
0.90
0.87
0.83
0.81
0.78
0.75
0.74
0.70
0.67
0°C
0.94
0.90
0.86
0.84
0.81
0.78
0.77
0.72
0.70
25°C
0.96
0.92
0.88
0.86
0.83
0.80
0.78
0.74
0.72
70°C
1.00
0.96
0.92
0.90
0.87
0.83
0.82
0.77
0.75
85°C
1.01
0.97
0.93
0.91
0.88
0.84
0.83
0.79
0.76
110°C
1.03
0.99
0.85
0.93
0.89
0.86
0.85
0.80
0.77
1.14
1.2
1.26
1.3
1.35
1.4
1.425
1.5
1.575
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode*
Core Voltage
1.2 V
A3P250L
A3P600L
A3P1000L
A3PE3000L
Units
mA
Typical (25°C)
0.33
0.55
0.88
2.75
1.5 V
mA
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6
and PDC7).
Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)*
Core Voltage
A3P250L
A3P600L
A3P1000L A3PE3000L Units
VCCI / VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.7
1.7
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI / VJTAG = 1.5 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.8
1.9
2.2
2.5
1.8
1.9
2.2
2.5
VCCI / VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI / VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI / VJTAG = 3.3 V (per bank)
Typical (25°C)
* IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode (VCC, VCCI = 0 V)
Core Voltage
A3PE3000L
Units
Typical (25°C)
1.2 V / 1.5 V
0
µA
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Values do not include I/O static contribution (PDC6
and PDC7).
Revision 9
2-7
ProASIC3L DC and Switching Characteristics
Table 2-10 • Quiescent Supply Current (IDD), No ProASIC3L Flash*Freeze Mode1
Core Voltage
A3P250L A3P600L
A3P1000L A3PE3000L Units
ICCA Current2
Typical (25°C)
1.2 V
1.5 V
0.33
0.55
0.88
2.75
mA
mA
ICCI or IJTAG Current3, 4
VCCI / VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI / VJTAG = 1.5 V (per bank)
Typical (25°C)
VCCI / VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI / VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI / VJTAG = 3.3 V (per bank)
Typical (25°C)
Notes:
1. To calculate total device I , multiply the number of banks used by I
and add I contribution.
CCA
DD
CCI
2. Includes VCC , VCCPLL, and VPUMP currents.
3. Per VCCI or VJTAG bank.
4. Values do not include I/O static contribution (P
and P
).
DC6
DC7
2-8
Revision 9
ProASIC3L Low Power Flash FPGAs
Power per I/O Pin
Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Pro I/O Banks
Static Power
PDC6 (mW)1
Dynamic Power
VCCI (V)
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
2.5 V LVCMOS
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
3.3
3.3
3.3
3.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16.34
24.49
4.71
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
6.13
1.66
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.2 V LVCMOS
1.78
1.01
0.97
0.60
1.2 V LVCMOS – Schmitt trigger
3.3 V PCI
0.53
17.76
19.10
17.76
19.10
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
2.90
2.13
2.81
2.57
0.17
0.17
1.38
1.38
3.21
3.21
7.07
3.62
2.97
2.55
0.85
0.85
3.30
3.30
8.08
8.08
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
2.5
3.3
2.26
5.71
0.95
1.62
LVPECL
Notes:
1.
2.
P
P
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCCI.
DC6
AC9
Revision 9
2-9
ProASIC3L DC and Switching Characteristics
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
Static Power
PDC6 (mW)2
Dynamic Power
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
3.3 V PCI
3.3
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
–
16.22
4.65
1.65
0.98
0.61
17.64
17.64
3.3 V PCI-X
Differential
LVDS
2.5
3.3
2.26
5.72
0.95
1.63
LVPECL
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
P
is the static power (where applicable) measured on VCCI.
DC6
is the total dynamic power measured on VCCI.
AC10
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power
PDC6 (mW)1
Dynamic Power
VCCI (V)
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL /
3.3
–
16.23
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
3.3 V PCI
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
4.66
1.64
0.99
0.58
17.64
17.64
3.3 V PCI-X
Notes:
1.
P
is the static power (where applicable) measured on VCCI.
DC6
2. PAC9 is the total dynamic power measured on VCCI.
2-10
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Pro I/Os
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
CLOAD (pF)
VCCI (V)
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
3.3 V PCI
5
5
3.3
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
–
148.00
83.23
54.58
37.05
17.94
204.61
204.61
5
5
5
10
10
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
10
10
10
10
20
20
30
30
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
–
24.08
13.52
24.10
13.54
26.22
27.22
105.56
116.60
114.87
131.76
2.5 V GTL
–
3.3 V GTL+
2.5 V GTL+
HSTL (I)
–
–
7.08
13.88
16.69
25.91
26.02
42.21
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
–
–
2.5
3.3
7.70
89.62
LVPECL
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
P
is the static power (where applicable) measured on VCCI.
DC7
3.
P
is the total dynamic power measured on VCCI.
AC10
Revision 9
2-11
ProASIC3L DC and Switching Characteristics
Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Advanced I/O Banks
Static Power
PDC7 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
3.3 V PCI
5
5
3.3
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
–
141.97
79.98
52.26
35.62
21.29
201.02
201.02
5
5
5
10
10
3.3 V PCI-X
Differential
LVDS
–
–
2.5
3.3
7.74
89.71
LVPECL
19.54
167.54
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
P
is the static power (where applicable) measured on VCCI.
DC7
is the total dynamic power measured on VCCI.
AC10
Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Standard Plus I/O Banks
Static Power
PDC7 (mW)2
Dynamic Power
C
LOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
3.3 V PCI
5
5
3.3
2.5
1.8
1.5
1.2
3.3
3.3
–
–
–
–
–
–
–
125.97
70.82
36.39
25.34
16.24
184.92
184.92
5
5
5
10
10
3.3 V PCI-X
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
P
is the static power (where applicable) measured on VCCI.
DC7
is the total dynamic power measured on VCCI.
AC10
2-12
Revision 9
ProASIC3L Low Power Flash FPGAs
Power Consumption of Various Internal Resources
Table 2-17 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at
1.2 V VCC
Device Specific Dynamic Power (µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
A3PE3000L A3P1000L A3P600L A3P250L
12.61
2.66
0.56
9.28
1.59
8.19
1.19
0.52
7.07
1.01
PAC2
PAC3
PAC4
Clock contribution of a VersaTile used as a sequential
module
0.07
0.05
0.19
0.11
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a sequential
module
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
Module
PAC8
PAC9
Average contribution of a routing net
0.45
Contribution of an I/O input pin (standard-dependent)
See Table 2-11 on page 2-9. through
Table 2-13 on page 2-10.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O output pin (standard-dependent)
See Table 2-14 on page 2-11 through
Table 2-16 on page 2-12.
Average contribution of a RAM block during a read
operation
25.00
30.00
1.74
Average contribution of a RAM block during a write
operation
Dynamic contribution for PLL
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
Revision 9
2-13
ProASIC3L DC and Switching Characteristics
Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at
1.5 V VCC
Device Specific Dynamic Power (µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
A3PE3000L A3P1000L A3P600L A3P250L
19.7
4.16
0.88
14.50
2.48
12.80
1.85
0.81
11.00
1.58
PAC2
PAC3
PAC4
Clock contribution of a VersaTile used as a sequential
module
0.12
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a sequential
module
0.07
0.29
0.29
0.70
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
Module
PAC8
PAC9
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
See Table 2-11 on page 2-9. through
Table 2-13 on page 2-10.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O output pin (standard-dependent)
See Table 2-14 on page 2-11 through
Table 2-16 on page 2-12.
Average contribution of a RAM block during a read
operation
25.00
30.00
2.60
Average contribution of a RAM block during a write
operation
Dynamic contribution for PLL
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
Table 2-19 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices
Device Specific Dynamic Power (µW)
Parameter
PDC1
Definition
A3PE3000L A3P1000L A3P600L A3P250L
See Table 2-10 on page 2-8.
See Table 2-8 on page 2-7.
See Table 2-7 on page 2-7.
1.42 mW
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
PDC2
PDC3
PDC4
Static PLL contribution at 1.2 V core (operating mode
only)
Static PLL contribution at 1.5 V core (operating mode
only)
2.55 mW
PDC5
PDC6
PDC7
Bank quiescent power (VCCI-dependent)
See Table 2-7 on page 2-7, Table 2-8 on
page 2-7, Table 2-10 on page 2-8.
I/O input pin static power (standard-dependent)
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-9 through
Table 2-13 on page 2-10.
See Table 2-14 on page 2-11 through
Table 2-16 on page 2-12.
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
2-14
Revision 9
ProASIC3L Low Power Flash FPGAs
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-20 on
page 2-17.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-21 on
page 2-17.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-21 on page 2-17. The calculation should be repeated for each clock domain defined in
the design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7
NINPUTS is the number of I/O input buffers used in the design.
N
OUTPUTS is the number of I/O output buffers used in the design.
BANKS is the number of I/O banks powered in the design.
N
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
Table 2-20 on page 2-17.
NROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-20 on page 2-17.
F
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
N
P
S-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on
page 2-17.
FCLK is the global clock signal frequency.
Revision 9
2-15
ProASIC3L DC and Switching Characteristics
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on
page 2-17.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-20 on
page 2-17.
F
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-20 on page 2-17.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-21 on page 2-17.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
F
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-21 on
page 2-17.
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
2-16
Revision 9
ProASIC3L Low Power Flash FPGAs
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-20 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 2-21 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
β1
β2
β3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
Revision 9
2-17
ProASIC3L DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
Y
t
= 0.56 ns
t
= 0.49 ns
PD
PD
t
= 1.34 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
High slew rate
= 2.64 ns (Advanced I/O Banks)
LVTTL
t
DP
t
= 0.87 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
Output drive strength = 8 mA
LVTTL
t
= 1.05 ns
High slew rate
= 3.66 ns (Advanced I/O Banks)
PY
t
DP
LVPECL
(Applicable
to Advanced
I/O Banks only)
t
= 0.47 ns
PD
I/O Module
(Non-Registered)
D
Q
Combinational Cell
Y
Output drive strength = 4 mA
High slew rate
LVCMOS 1.5 V
t
t
= 0.24 ns
= 0.26 ns
ICLKQ
ISUD
t
= 3.97 ns (Advanced I/O Banks)
DP
t
= 0.47 ns
PD
Input LVTTL
Clock
I/O Module
Register Cell
(Registered)
Register Cell
Combinational Cell
Y
t
= 0.76 ns (Advanced I/O Banks)
PY
D
Q
D
Q
D
t
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
I/O Module
t
= 0.47 ns
PD
t
= 2.64 ns
(Non-Registered)
DP
(Advanced I/O Banks)
t
t
= 0.55 ns
= 0.43 ns
= 0.59 ns
= 0.31 ns
t
t
= 0.55 ns
= 0.43 ns
CLKQ
OCLKQ
CLKQ
LVDS,
BLVDS,
M-LVDS
t
SUD
OSUD
SUD
Input LVTTL
Clock
Input LVTTL
Clock
(Applicable for
Advanced I/O
Banks only)
t
= 1.20 ns
PY
t
= 0.76 ns
t
= 0.76 ns
PY
PY
(Advanced I/O Banks)
(Advanced I/O Banks)
Figure 2-3 • Timing Model
Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.14 V
2-18
Revision 9
ProASIC3L Low Power Flash FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
Revision 9
2-19
ProASIC3L DC and Switching Characteristics
tDOUT
tDP
D Q
CLK
PAD
DOUT
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
2-20
Revision 9
ProASIC3L Low Power Flash FPGAs
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
Revision 9
2-21
ProASIC3L DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Pro I/O
1
1
VIL
Max.
VIH
VOL
VOH
IOL IOH
Drive
Slew Min.
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard
Strength Rate
V
V
mA mA
12 12
3.3 V LVTTL /
12 mA High –0.3
0.8
2
3.6
0.4
2.4
3.3 V LVCMOS
3.3 V LVCMOS Any2
Wide Range
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS
1.8 V LVCMOS
12 mA High –0.3
0.7
1.7
2.7
1.9
0.7
1.7
12
12
12
12
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI
0.45
VCCI –
0.45
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12
12
2
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
Per PCI Specification
Per PCI-X Specification
1.26 0.25 * VCCI 0.75 * VCCI
2
3.3 V PCI-X
3.3 V GTL
25 mA3 High –0.3
VREF –
0.05
VREF + 0.05
3.6
0.4
0.4
–
–
25
25
25
25
2.5 V GTL
25 mA3 High –0.3
VREF –
0.05
VREF + 0.05
2.7
3.3 V GTL+
2.5 V GTL+
HSTL (I)
35 mA High –0.3 VREF – 0.1 VREF + 0.1
33 mA High –0.3 VREF – 0.1 VREF + 0.1
3.6
2.7
0.6
0.6
–
–
51
40
8
51
40
8
8 mA
High –0.3 VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
15 mA3 High –0.3 VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4 15
VCCI – 0.62 15
VCCI – 0.43 18
VCCI – 1.1 14
VCCI – 0.9 21
15
15
18
14
21
15 mA High –0.3 VREF – 0.1 VREF + 0.1
18 mA High –0.3 VREF – 0.1 VREF + 0.1
14 mA High –0.3 VREF – 0.1 VREF + 0.1
21 mA High –0.3 VREF – 0.1 VREF + 0.1
2.7
2.7
3.6
3.6
0.54
0.35
0.7
0.5
1. Currents are measured at 85°C junction temperature.
2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.
3. Output drive strength is below JEDEC specification.
4. Output slew rate can be extracted using the IBIS Models.
2-22
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
1
1
VIL
Max.
VIH
VOL
VOH
IOL IOH
Drive Slew Min.
Strength Rate
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard
V
V
mA mA
3.3 V LVTTL /
12 mA High –0.3
0.8
2
3.6
0.4
2.4
12 12
3.3 V LVCMOS
3.3 V LVCMOS Any3
Wide Range
High –0.3
0.8
0.7
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
12 mA High –0.3
1.7
2.7
1.9
0.7
1.7
12 12
12 mA
12 mA
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
0.45
VCCI – 0.45 12 12
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
Per PCI specifications
3.3 V PCI-X
Notes:
Per PCI-X specifications
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted using the IBIS Models
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.
Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
1
1
VIL
Max.
VIH
VOL
VOH
IOL IOH
Drive Slew Min.
Strength Rate
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard
V
V
mA mA
12 12
3.3 V LVTTL /
12 mA High –0.3
0.8
2
3.6
0.4
2.4
3.3 V LVCMOS
3.3 V LVCMOS Any3
Wide Range
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
12 mA High –0.3
0.7
1.7
2.7
1.9
0.7
1.7
12
8
12
8
8 mA
4 mA
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
0.45
VCCI – 0.45
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
4
4
High –0.3 0.35 * VCCI 0.65 * VCCI 1.26
0.25 * VCCI 0.75 * VCCI
2
2
Per PCI specifications
3.3 V PCI-X
Notes:
Per PCI-X specifications
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted using the IBIS Models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.
Revision 9
2-23
ProASIC3L DC and Switching Characteristics
Table 2-25 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL
IIH
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IIL
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
IIH
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
DC I/O Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
2-24
Revision 9
ProASIC3L Low Power Flash FPGAs
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-26 • Summary of AC Memory Points
Input Reference Voltage
Board Termination
Measuring Trip Point
(Vtrip
Standard
(VREF_TYP
)
Voltage (VTT_REF
)
)
3.3 V LVTTL /
–
–
1.4 V
3.3 V LVCMOS
3.3 V LVCMOS Wide
Range
–
–
1.4 V
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
–
–
–
–
–
–
–
–
–
–
1.2 V
0.90 V
0.75 V
0.6 V
0.285 * VCCI (RR)
0.615 * VCCI (FF))
0.285 * VCCI (RR)
0.615 * VCCI (FF)
VREF
3.3 V PCI-X
–
–
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
VREF
VREF
VREF
VREF
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
LVPECL
–
–
Table 2-27 • I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
tPY
tDOUT
tEOUT
tDIN
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
tZH
tLZ
tZL
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Revision 9
2-25
ProASIC3L DC and Switching Characteristics
1.5 V DC Core Voltage
Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425V, Worst Case
VCCI
Pro I/O Banks
Standard
3.3 V LVTTL /
12 mA High
5
–
0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64 3.13 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High
1.8 V LVCMOS 12 mA High
1.5 V LVCMOS 12 mA High
5
5
5
5
–
–
–
–
0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67 3.30 ns
0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89 3.47 ns
0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22 3.75 ns
0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V PCI
Per
PCI
High
spec.
3.3 V PCI-X
Per
PCI-X
spec.
High 10 25 0.50 2.15 0.03 2.10 2.84 0.33 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
25 mA High 10 25 0.50 1.59 0.03 1.80
25 mA High 10 25 0.50 1.63 0.03 1.75
35 mA High 10 25 0.50 1.57 0.03 1.80
33 mA High 10 25 0.50 1.69 0.03 1.75
8 mA High 20 25 0.50 2.43 0.03 2.12
15 mA High 20 50 0.50 2.32 0.03 2.12
15 mA High 30 25 0.50 1.63 0.03 1.61
18 mA High 30 50 0.50 1.66 0.03 1.61
14 mA High 30 25 0.50 1.77 0.03 1.54
21 mA High 30 50 0.50 1.58 0.03 1.54
–
–
–
–
–
–
–
–
–
–
–
–
0.33 1.56 1.59
0.33 1.66 1.63
0.33 1.60 1.57
0.33 1.72 1.61
0.33 2.48 2.41
0.33 2.36 2.08
0.33 1.66 1.41
0.33 1.69 1.36
0.33 1.80 1.41
0.33 1.61 1.28
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.27 3.30 ns
3.37 3.34 ns
3.31 3.29 ns
3.43 3.32 ns
4.19 4.12 ns
4.07 3.79 ns
1.66 1.41 ns
1.69 1.36 ns
1.80 1.41 ns
1.61 1.28 ns
24 mA High
24 mA High
-
-
-
-
0.50 1.40 0.03 1.85
0.50 1.40 0.03 1.67
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75
for connectivity. This resistor is not required during normal operation.
2-26
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst
Case VCCI
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA
High 5pF
–
0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High 5 pF
High 5 pF
High 5 pF
–
–
–
0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns
0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns
0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns
Per PCI spec. High 5 pF 25 2 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns
3.3 V PCI-X
Per PCI-X
spec.
High 10 pF 25 2 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns
LVDS
24 mA
24 mA
High
High
–
–
–
–
0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns
0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75 for
connectivity. This resistor is not required during normal operation.
Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst
Case VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA
High 5pF
–
0.46 1.56 0.03 0.77 0.33 1.59 1.20 2.14 2.47 3.30 2.91 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
8 mA
4 mA
High 5pF
High 5pF
High 5pF
–
–
–
0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns
0.46 1.59 0.03 0.99 0.33 1.61 1.32 2.16 2.38 3.33 3.03 ns
0.46 2.15 0.03 1.09 0.33 2.19 1.82 2.32 2.40 3.90 3.53 ns
Per PCI spec. High 10 pF 252 0.46 1.77 0.03 0.65 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns
Per PCI-X spec. High 10 pF 25 2 0.46 1.77 0.03 0.64 0.33 1.80 1.31 2.14 2.47 3.51 3.02 ns
3.3 V PCI-X
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75 for
connectivity. This resistor is not required during normal operation.
Revision 9
2-27
ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case
VCCI
Pro I/O Banks
Standard
3.3 V LVTTL /
12 mA High
5
–
0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High
1.8 V LVCMOS 12 mA High
1.5 V LVCMOS 12 mA High
1.2 V LVCMOS 2 mA High
5
5
5
5
–
–
–
–
–
0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns
0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns
0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns
0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns
0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V PCI
Per
PCI
High 10
spec.
3.3 V PCI-X
Per
PCI-X
spec.
High 10 25 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
25 mA High 10 25 0.66 1.59 0.04 1.80
25 mA High 10 25 0.66 1.63 0.04 1.75
35 mA High 10 25 0.66 1.57 0.04 1.80
33 mA High 10 25 0.66 1.69 0.04 1.75
8 mA High 20 25 0.66 2.43 0.04 2.12
15 mA High 20 50 0.66 2.32 0.04 2.12
15 mA High 30 25 0.66 1.63 0.04 1.61
18 mA High 30 50 0.66 1.66 0.04 1.61
14 mA High 30 25 0.66 1.77 0.04 1.54
21 mA High 30 50 0.66 1.58 0.04 1.54
–
–
–
–
–
–
–
–
–
–
–
–
0.43 1.56 1.59
0.43 1.66 1.63
0.43 1.60 1.57
0.43 1.72 1.61
0.43 2.48 2.41
0.43 2.36 2.08
0.43 1.66 1.41
0.43 1.69 1.36
0.43 1.80 1.41
0.43 1.61 1.28
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.27 3.30 ns
3.37 3.34 ns
3.31 3.29 ns
3.43 3.32 ns
4.19 4.12 ns
4.07 3.79 ns
1.66 1.41 ns
1.69 1.36 ns
1.80 1.41 ns
1.61 1.28 ns
24 mA High
24 mA High
-
-
-
-
0.66 1.43 0.04 1.85
0.66 1.37 0.04 1.67
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75
for connectivity. This resistor is not required during normal operation.
2-28
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case
VCCI
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA
High 5pF
–
0.60 1.83 0.04 0.78 0.43 1.87 1.39 2.46 2.74 3.58 3.10 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
2 mA
High 5 pF
High 5 pF
High 5 pF
High 5pF
–
–
–
–
0.60 1.85 0.04 1.00 0.43 1.88 1.55 2.53 2.63 3.59 3.26 ns
0.60 2.04 0.04 0.93 0.43 2.08 1.73 2.83 3.12 3.79 3.45 ns
0.60 2.33 0.04 1.10 0.43 2.37 2.01 3.02 3.22 4.08 3.72 ns
0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41 ns
Per PCI spec. High 10 pF 25 2 0.60 2.05 0.04 0.66 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns
3.3 V PCI-X
Per PCI-X
spec.
High 10 pF 25 2 0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns
LVDS
24 mA
24 mA
High
High
–
–
–
–
0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns
0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75 for
connectivity. This resistor is not required during normal operation.
Revision 9
2-29
ProASIC3L DC and Switching Characteristics
Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case
VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA
High 5pF
–
0.60 1.56 0.04 0.77 0.43 1.59 1.20 2.14 2.47 3.30 2.91 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
12 mA
8 mA
4 mA
2 mA
High 5pF
High 5pF
High 5pF
High 5pF
–
–
–
–
0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns
0.60 1.59 0.04 0.99 0.43 1.61 1.32 2.16 2.38 3.33 3.03 ns
0.60 2.15 0.04 1.09 0.43 2.19 1.82 2.32 2.40 3.90 3.53 ns
0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76 ns
Per PCI spec. High 10 pF 252 0.60 1.77 0.04 0.65 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns
Per PCI-X spec. High 10 pF 25 2 0.60 1.77 0.04 0.64 0.43 1.80 1.31 2.14 2.47 3.51 3.02 ns
3.3 V PCI-X
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-75 for
connectivity. This resistor is not required during normal operation.
Detailed I/O DC Characteristics
Table 2-34 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min.
Max.
Units
pF
Input capacitance
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
2-30
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-35 • I/O Output Buffer Maximum Resistances1
Applicable to Pro I/Os
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
(Ω) 2
100
50
(Ω) 3
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
8 mA
300
150
75
12 mA
16 mA
24 mA
4 mA
25
17
50
11
33
2.5 V LVCMOS
1.8 V LVCMOS
100
50
200
100
50
8 mA
12 mA
16 mA
24 mA
2 mA
25
20
40
11
22
200
100
50
225
112
56
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
50
56
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
12 mA
2 mA
33
37
33
37
1.2 V LVCMOS
3.3 V PCI/PCI-X
TBD
25
TBD
75
Per PCI/PCI-X
specification
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA
25 mA
35 mA
33 mA
8 mA
11
14
12
15
50
25
27
13
44
18
–
–
–
–
50
25
31
15
69
32
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
15 mA
15 mA
18 mA
14 mA
21 mA
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on V , drive strength selection, temperature, and process. For board design considerations and detailed output buffer
CCI
resistances,
use
the
corresponding
IBIS
models
located
on
the
Actel
website
at
http://www.actel.com/download/ibis/default.aspx.
2.
3.
R
R
= (V
) / I
OLspec OLspec
(PULL-DOWN-MAX)
= (V
– V
) / I
(PULL-UP-MAX)
CCImax
OHspec OHspec
Revision 9
2-31
ProASIC3L DC and Switching Characteristics
Table 2-36 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
(Ω) 2
(Ω) 3
3.3 V LVTTL / 3.3 V LVCMOS
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
24 mA
2 mA
25
17
50
11
33
2.5 V LVCMOS
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
24 mA
2 mA
25
17
50
11
33
1.8 V LVCMOS
100
100
50
200
200
100
100
50
4 mA
6 mA
8 mA
50
12 mA
16 mA
2 mA
25
20
40
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
2 mA
33
37
1.2 V LVCMOS
3.3 V PCI/PCI-X
TBD
25
TBD
75
Per PCI/PCI-X
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on
, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
V
CCI
resistances,
use
the
corresponding
IBIS
models
located
on
the
Actel
website
at
http://www.actel.com/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
2-32
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-37 • I/O Output Buffer Maximum Resistances1
Applicable to Standard Plus I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
(Ω) 2
(Ω) 3
3.3 V LVTTL / 3.3 V LVCMOS
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
2 mA
25
25
75
2.5 V LVCMOS
100
100
50
200
200
100
100
50
4 mA
6 mA
8 mA
50
12 mA
2 mA
25
1.8 V LVCMOS
1.5 V LVCMOS
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
2 mA
200
100
TBD
25
224
112
TBD
75
4 mA
1.2 V LVCMOS
3.3 V PCI/PCI-X
2 mA
Per PCI/PCI-X
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on V , drive strength selection, temperature, and process. For board design considerations and detailed output buffer
CCI
resistances,
use
the
corresponding
IBIS
models
located
on
the
Actel
website
at
http://www.actel.com/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
Revision 9
2-33
ProASIC3L DC and Switching Characteristics
Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 k
11 k
18 k
19 k
TBD
Max.
45 k
55 k
70 k
90 k
TBD
Min.
Max.
45 k
3.3 V
10 k
12 k
17 k
19 k
TBD
2.5 V
74 k
1.8 V
110 k
140 k
TBD
1.5 V
1.2 V LVCMOS
Notes:
1.
2.
R
R
= (VOLspec) / I
(WEAK PULL-UP-MIN)
(WEAK PULL-UP-MAX)
(WEAK PULL-UP-MAX)
= (VCCImax – VOHspec) / I
(WEAK PULL-UP-MIN)
2-34
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-39 • I/O Short Currents IOSH OSL
/I
Applicable to Pro I/Os
Drive Strength
4 mA
I
OSL (mA)*
25
IOSH (mA)*
27
3.3 V LVTTL / 3.3 V LVCMOS
8 mA
51
54
12 mA
16 mA
24 mA
4 mA
103
132
268
16
109
127
181
18
2.5 V LVCMOS
8 mA
32
37
12 mA
16 mA
24 mA
2 mA
65
74
83
87
169
9
124
11
1.8 V LVCMOS
4 mA
17
22
6 mA
35
44
8 mA
45
51
12 mA
16 mA
2 mA
91
74
91
74
1.5 V LVCMOS
13
16
4 mA
25
33
6 mA
32
39
8 mA
66
55
12 mA
2 mA
66
55
1.2 V LVCMOS
3.3 V PCI/PCIX
TBD
TBD
Per PCI/PCI-X
Specification
Per PCI Curves
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA
25 mA
35 mA
33 mA
8 mA
268
169
268
169
32
181
124
181
124
39
HSTL (II)
15 mA
15 mA
18 mA
14 mA
66
55
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
* TJ = 100°C
83
87
169
51
124
54
Revision 9
2-35
ProASIC3L DC and Switching Characteristics
Table 2-40 • I/O Short Currents IOSH OSL
/I
Applicable to Advanced I/O Banks
Drive Strength
I
OSL (mA)*
IOSH (mA)*
27
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
25
4 mA
25
27
6 mA
51
54
8 mA
51
54
12 mA
103
132
268
16
109
127
181
18
16 mA
24 mA
2.5 V LVCMOS
2 mA
4 mA
16
18
6 mA
32
37
8 mA
32
37
12 mA
65
74
16 mA
83
87
24 mA
169
9
124
11
1.8 V LVCMOS
2 mA
4 mA
17
22
6 mA
35
44
8 mA
45
51
12 mA
91
74
16 mA
91
74
1.5 V LVCMOS
2 mA
13
16
4 mA
25
33
6 mA
32
39
8 mA
12 mA
66
55
66
55
1.2 V LVCMOS
3.3 V PCI/PCI-X
* TJ = 100°C
2 mA
TBD
103
TBD
109
Per PCI/PCI-X specification
2-36
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-41 • I/O Short Currents IOSH OSL
/I
Applicable to Standard Plus I/O Banks
Drive Strength
I
OSL (mA)*
25
IOSH (mA)*
27
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
25
27
6 mA
51
54
8 mA
51
54
12 mA
103
103
16
109
109
18
16 mA
2.5 V LVCMOS
2 mA
4 mA
16
18
6 mA
32
37
8 mA
32
37
12 mA
65
74
1.8 V LVCMOS
1.5 V LVCMOS
2 mA
9
11
4 mA
17
22
6 mA
35
44
8 mA
35
44
2 mA
13
16
4 mA
2 mA
25
33
1.2 V LVCMOS
3.3 V PCI/PCI-X
* TJ = 100°C
TBD
103
TBD
109
Per PCI/PCI-X specification
Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
240 mV
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
140 mV
80 mV
60 mV
40 mV
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection, but
such protection would only be needed in extremely prolonged stress conditions.
Revision 9
2-37
ProASIC3L DC and Switching Characteristics
Table 2-43 • Duration of Short Circuit Event before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
110°C
6 months
3 months
Table 2-44 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.)
No requirement
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
10 ns *
10 ns *
20 years (110°C)
10 years (100°C)
LVDS/B-LVDS/
No requirement
M-LVDS/LVPECL
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the
rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the
more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization
of the system to ensure that there is no excessive noise coupling into input signals.
2-38
Revision 9
ProASIC3L Low Power Flash FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all
LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8a
specification.
Table 2-45 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
Drive Strength
4 mA
V
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
4
8
4
8
25
51
27
54
6 mA
8 mA
12 12
16 16
24 24
24 24
103
132
268
27
109
127
181
25
12 mA
16 mA
24 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-46 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
Drive Strength
2 mA
V
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
8
2
4
6
8
25
25
27
27
4 mA
6 mA
51
54
8 mA
51
54
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
103
132
268
109
127
181
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Revision 9
2-39
ProASIC3L DC and Switching Characteristics
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
Drive Strength
2 mA
V
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
2
25
25
27
27
4 mA
4
6 mA
6
51
54
8 mA
8
8
51
54
12 mA
16 mA
Notes:
12 12
16 16
103
103
109
109
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-48 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Pro, Advanced, and Standard Plus I/O Banks
3.3 V LVCMOS Wide
Range
VIL
VIH
VOL
VOH
IOL IOH
IIL
IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Drive Strength
All2
mA mA µA2 µA2
10 10
–0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
Notes:
1. Currents are measured at 85°C junction temperature.
2. All LVMCOS 3.3 V software macros supports LVCMOS 3.3 V wide range as specified in the JDEC8a specification
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
1.4
5
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-40
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.59 5.48 0.04 1.58 2.17 0.38 5.58 4.40 2.42 2.20 7.60
6.42
5.46
5.78
4.91
5.29
4.50
5.19
4.41
5.20
4.42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 4.66 0.03 1.34 1.85 0.33 4.75 3.75 2.06 1.87 6.46
0.59 4.48 0.04 1.58 2.17 0.38 4.56 3.76 2.73 2.76 6.57
0.50 3.81 0.03 1.34 1.85 0.33 3.88 3.20 2.33 2.35 5.59
0.59 3.77 0.04 1.58 2.17 0.38 3.84 3.28 2.95 3.12 5.85
0.50 3.21 0.03 1.34 1.85 0.33 3.27 2.79 2.51 2.65 4.98
0.59 3.57 0.04 1.58 2.17 0.38 3.63 3.18 2.99 3.22 5.64
0.50 3.03 0.03 1.34 1.85 0.33 3.09 2.70 2.54 2.74 4.80
0.59 3.46 0.04 1.58 2.17 0.38 3.52 3.19 3.05 3.57 5.54
0.50 2.94 0.03 1.34 1.85 0.33 3.00 2.71 2.59 3.03 4.71
8 mA
Std.
–1
12 mA
16 mA
24 mA
Std.
–1
Std.
–1
Std.
–1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.59 3.08 0.04 1.58 2.17 0.38 3.14 2.36 2.42 2.33 5.15
4.38
3.72
3.90
3.32
3.68
3.13
3.64
3.09
3.58
3.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 2.62 0.03 1.34 1.85 0.33 2.67 2.01 2.06 1.98 4.38
0.59 2.53 0.04 1.58 2.17 0.38 2.58 1.89 2.74 2.89 4.59
0.50 2.16 0.03 1.34 1.85 0.33 2.20 1.61 2.33 2.46 3.91
0.59 2.22 0.04 1.58 2.17 0.38 2.27 1.67 2.95 3.25 4.28
0.50 1.89 0.03 1.34 1.85 0.33 1.93 1.42 2.51 2.77 3.64
0.59 2.17 0.04 1.58 2.17 0.38 2.21 1.63 3.00 3.35 4.23
0.50 1.85 0.03 1.34 1.85 0.33 1.88 1.38 2.55 2.85 3.59
0.59 2.19 0.04 1.58 2.17 0.38 2.24 1.57 3.05 3.71 4.25
0.50 1.87 0.03 1.34 1.85 0.33 1.90 1.33 2.59 3.16 3.61
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-41
ProASIC3L DC and Switching Characteristics
Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
7.22
6.14
6.39
5.44
6.39
5.44
5.76
4.90
5.57
4.74
5.47
4.65
tZHS
6.34
5.40
5.76
4.90
5.76
4.90
5.33
4.53
5.23
4.45
5.26
4.48
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
5.11 0.04 0.91
4.35 0.03 0.78
4.30 0.04 0.91
3.66 0.03 0.78
4.30 0.04 0.91
3.66 0.03 0.78
3.68 0.04 0.91
3.13 0.03 0.78
3.50 0.04 0.91
2.97 0.03 0.78
3.39 0.04 0.91
2.88 0.03 0.78
5.21 4.33 2.38 2.21
4.43 3.68 2.02 1.88
4.38 3.75 2.68 2.74
3.73 3.19 2.28 2.33
4.38 3.75 2.68 2.74
3.73 3.19 2.28 2.33
3.75 3.32 2.89 3.07
3.19 2.82 2.45 2.62
3.56 3.21 2.93 3.16
3.03 2.73 2.49 2.69
3.45 3.25 2.99 3.50
2.94 2.76 2.54 2.97
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
4.97
4.23
4.47
3.80
4.47
3.80
4.21
3.58
4.17
3.54
4.19
3.56
tZHS
4.29
3.65
3.85
3.28
3.85
3.28
3.64
3.10
3.61
3.07
3.56
3.03
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
2.90 0.04 0.91
2.47 0.03 0.78
2.41 0.04 0.91
2.05 0.03 0.78
2.41 0.04 0.91
2.05 0.03 0.78
2.16 0.04 0.91
1.83 0.03 0.78
2.11 0.04 0.91
1.80 0.03 0.78
2.14 0.04 0.91
1.82 0.03 0.78
2.96 2.28 2.38 2.35
2.52 1.94 2.03 2.00
2.46 1.84 2.69 2.88
2.09 1.57 2.29 2.45
2.46 1.84 2.69 2.88
2.09 1.57 2.29 2.45
2.20 1.63 2.89 3.22
1.87 1.39 2.46 2.74
2.15 1.59 2.94 3.31
1.83 1.36 2.50 2.82
2.17 1.55 2.99 3.65
1.85 1.32 2.54 3.11
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–-1
Std.
–-1
Std.
–1
ns
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-42
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
6.71
5.71
5.88
5.00
5.88
5.00
5.30
4.51
5.30
4.51
tZHS
5.92
5.04
5.41
4.60
5.41
4.60
5.01
4.27
5.01
4.27
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
4.61 0.04 0.90
3.92 0.03 0.77
3.80 0.04 0.90
3.23 0.03 0.77
3.80 0.04 0.90
3.23 0.03 0.77
3.22 0.04 0.90
2.74 0.03 0.77
3.22 0.04 0.90
2.74 0.03 0.77
4.70 3.91 2.05 1.99
4.00 3.32 1.74 1.69
3.87 3.40 2.32 2.47
3.29 2.89 1.98 2.10
3.87 3.40 2.32 2.47
3.29 2.89 1.98 2.10
3.28 3.00 2.51 2.77
2.79 2.55 2.14 2.36
3.28 3.00 2.51 2.77
2.79 2.55 2.14 2.36
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
4.57
3.89
4.10
3.49
4.10
3.49
3.88
3.30
3.88
3.30
tZHS
4.02
3.42
3.62
3.08
3.62
3.08
3.42
2.91
3.42
2.91
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
2.51 0.04 0.90
2.14 0.03 0.77
2.05 0.04 0.90
1.74 0.03 0.77
2.05 0.04 0.90
1.74 0.03 0.77
1.83 0.04 0.90
1.56 0.03 0.77
1.83 0.04 0.90
1.56 0.03 0.77
2.56 2.01 2.05 2.10
2.18 1.71 1.74 1.79
2.09 1.61 2.32 2.59
1.78 1.37 1.97 2.20
2.09 1.61 2.32 2.59
1.78 1.37 1.97 2.20
1.86 1.41 2.51 2.90
1.59 1.20 2.14 2.47
1.86 1.41 2.51 2.90
1.59 1.20 2.14 2.47
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-43
ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.77 5.48 0.05 1.58 2.17 0.50 5.58 4.40 2.42 2.20 7.60
6.42
5.46
5.78
4.91
5.29
4.50
5.19
4.41
5.20
4.42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 4.66 0.04 1.34 1.85 0.43 4.75 3.75 2.06 1.87 6.46
0.77 4.48 0.05 1.58 2.17 0.50 4.56 3.76 2.73 2.76 6.57
0.66 3.81 0.04 1.34 1.85 0.43 3.88 3.20 2.33 2.35 5.59
0.77 3.77 0.05 1.58 2.17 0.50 3.84 3.28 2.95 3.12 5.85
0.66 3.21 0.04 1.34 1.85 0.43 3.27 2.79 2.51 2.65 4.98
0.77 3.57 0.05 1.58 2.17 0.50 3.63 3.18 2.99 3.22 5.64
0.66 3.03 0.04 1.34 1.85 0.43 3.09 2.70 2.54 2.74 4.80
0.77 3.46 0.05 1.58 2.17 0.50 3.52 3.19 3.05 3.57 5.54
0.66 2.94 0.04 1.34 1.85 0.43 3.00 2.71 2.59 3.03 4.71
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.77 3.08 0.05 1.58 2.17 0.50 3.14 2.36 2.42 2.33 5.15
4.38
3.72
3.90
3.32
3.68
3.13
3.64
3.09
3.58
3.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 2.62 0.04 1.34 1.85 0.43 2.67 2.01 2.06 1.98 4.38
0.77 2.53 0.05 1.58 2.17 0.50 2.58 1.89 2.74 2.89 4.59
0.66 2.16 0.04 1.34 1.85 0.43 2.20 1.61 2.33 2.46 3.91
0.77 2.22 0.05 1.58 2.17 0.50 2.27 1.67 2.95 3.25 4.28
0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64
0.77 2.17 0.05 1.58 2.17 0.50 2.21 1.63 3.00 3.35 4.23
0.66 1.85 0.04 1.34 1.85 0.43 1.88 1.38 2.55 2.85 3.59
0.77 2.19 0.05 1.58 2.17 0.50 2.24 1.57 3.05 3.71 4.25
0.66 1.87 0.04 1.34 1.85 0.43 1.90 1.33 2.59 3.16 3.61
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-44
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
7.22
6.14
6.39
5.44
6.39
5.44
5.76
4.90
5.57
4.74
5.47
4.65
tZHS
6.34
5.40
5.76
4.90
5.76
4.90
5.33
4.53
5.23
4.45
5.26
4.48
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
5.11 0.05 0.91
4.35 0.04 0.78
4.30 0.05 0.91
3.66 0.04 0.78
4.30 0.05 0.91
3.66 0.04 0.78
3.68 0.05 0.91
3.13 0.04 0.78
3.50 0.05 0.91
2.97 0.04 0.78
3.39 0.05 0.91
2.88 0.04 0.78
5.21 4.33 2.38 2.21
4.43 3.68 2.02 1.88
4.38 3.75 2.68 2.74
3.73 3.19 2.28 2.33
4.38 3.75 2.68 2.74
3.73 3.19 2.28 2.33
3.75 3.32 2.89 3.07
3.19 2.82 2.45 2.62
3.56 3.21 2.93 3.16
3.03 2.73 2.49 2.69
3.45 3.25 2.99 3.50
2.94 2.76 2.54 2.97
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
4.97
4.23
4.47
3.80
4.47
3.80
4.21
3.58
4.17
3.54
4.19
3.56
tZHS
4.29
3.65
3.85
3.28
3.85
3.28
3.64
3.10
3.61
3.07
3.56
3.03
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
2.90 0.05 0.91
2.47 0.04 0.78
2.41 0.05 0.91
2.05 0.04 0.78
2.41 0.05 0.91
2.05 0.04 0.78
2.16 0.05 0.91
1.83 0.04 0.78
2.11 0.05 0.91
1.80 0.04 0.78
2.14 0.05 0.91
1.82 0.04 0.78
2.96 2.28 2.38 2.35
2.52 1.94 2.03 2.00
2.46 1.84 2.69 2.88
2.09 1.57 2.29 2.45
2.46 1.84 2.69 2.88
2.09 1.57 2.29 2.45
2.20 1.63 2.89 3.22
1.87 1.39 2.46 2.74
2.15 1.59 2.94 3.31
1.83 1.36 2.50 2.82
2.17 1.55 2.99 3.65
1.85 1.32 2.54 3.11
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–-1
Std.
–-1
Std.
–1
ns
ns
ns
ns
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-45
ProASIC3L DC and Switching Characteristics
Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
6.71
5.71
5.88
5.00
5.88
5.00
5.30
4.51
5.30
4.51
tZHS
5.92
5.04
5.41
4.60
5.41
4.60
5.01
4.27
5.01
4.27
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
4.61 0.05 0.90
3.92 0.04 0.77
3.80 0.05 0.90
3.23 0.04 0.77
3.80 0.05 0.90
3.23 0.04 0.77
3.22 0.05 0.90
2.74 0.04 0.77
3.22 0.05 0.90
2.74 0.04 0.77
4.70 3.91 2.05 1.99
4.00 3.32 1.74 1.69
3.87 3.40 2.32 2.47
3.29 2.89 1.98 2.10
3.87 3.40 2.32 2.47
3.29 2.89 1.98 2.10
3.28 3.00 2.51 2.77
2.79 2.55 2.14 2.36
3.28 3.00 2.51 2.77
2.79 2.55 2.14 2.36
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
4.57
3.89
4.10
3.49
4.10
3.49
3.88
3.30
3.88
3.30
tZHS
4.02
3.42
3.62
3.08
3.62
3.08
3.42
2.91
3.42
2.91
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
2.51 0.05 0.90
2.14 0.04 0.77
2.05 0.05 0.90
1.74 0.04 0.77
2.05 0.05 0.90
1.74 0.04 0.77
1.83 0.05 0.90
1.56 0.04 0.77
1.83 0.05 0.90
1.56 0.04 0.77
2.56 2.01 2.05 2.10
2.18 1.71 1.74 1.79
2.09 1.61 2.32 2.59
1.78 1.37 1.97 2.20
2.09 1.61 2.32 2.59
1.78 1.37 1.97 2.20
1.86 1.41 2.51 2.90
1.59 1.20 2.14 2.47
1.86 1.41 2.51 2.90
1.59 1.20 2.14 2.47
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-46
Revision 9
ProASIC3L Low Power Flash FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 2-62 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/Os
2.5 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
Drive Strength
4 mA
mA mA mA1
mA1 µA2 µA2
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
4
8
4
8
16
32
18
37
10 10
10 10
10 10
10 10
10 10
8 mA
12 mA
12 12
16 16
24 24
65
74
16 mA
83
87
24 mA
169
124
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-63 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
Drive Strength
2 mA
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
16
16
18
18
4 mA
6 mA
32
37
8 mA
32
37
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
65
74
83
87
169
124
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Revision 9
2-47
ProASIC3L DC and Switching Characteristics
Table 2-64 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
µA2 µA2
10 10
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
16
16
32
32
65
18
18
37
37
74
12 12
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
5
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-48
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-66 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.59 6.24 0.04 1.86 2.31 0.38 6.36 5.30 2.45 1.98 8.37
7.31
6.22
6.50
5.53
5.92
5.04
5.79
4.93
5.81
4.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 5.31 0.03 1.58 1.97 0.33 5.41 4.51 2.08 1.68 7.12
0.59 5.10 0.04 1.86 2.31 0.38 5.20 4.49 2.79 2.64 7.21
0.50 4.34 0.03 1.58 1.97 0.33 4.42 3.82 2.37 2.24 6.13
0.59 4.29 0.04 1.86 2.31 0.38 4.37 3.91 3.03 3.05 6.39
0.50 3.65 0.03 1.58 1.97 0.33 3.72 3.32 2.58 2.60 5.43
0.59 4.05 0.04 1.86 2.31 0.38 4.12 3.78 3.08 3.17 6.13
0.50 3.44 0.03 1.58 1.97 0.33 3.51 3.22 2.62 2.70 5.22
0.59 3.94 0.04 1.86 2.31 0.38 4.01 3.80 3.15 3.60 6.03
0.50 3.35 0.03 1.58 1.97 0.33 3.41 3.23 2.68 3.06 5.13
8 mA
Std.
–1
12 mA
16 mA
24 mA
Std.
–1
Std.
–1
Std.
–1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-67 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.59 3.18 0.04 1.86 2.31 0.38 3.24 2.84 2.45 2.06 5.25
4.85
4.13
4.20
3.57
3.88
3.30
3.82
3.25
3.74
3.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 2.71 0.03 1.58 1.97 0.33 2.76 2.42 2.08 1.75 4.47
0.59 2.61 0.04 1.86 2.31 0.38 2.65 2.19 2.79 2.73 4.67
0.50 2.22 0.03 1.58 1.97 0.33 2.26 1.86 2.37 2.32 3.97
0.59 2.26 0.04 1.86 2.31 0.38 2.30 1.86 3.03 3.15 4.32
0.50 1.92 0.03 1.58 1.97 0.33 1.96 1.59 2.58 2.68 3.67
0.59 2.20 0.04 1.86 2.31 0.38 2.24 1.80 3.08 3.26 4.26
0.50 1.87 0.03 1.58 1.97 0.33 1.91 1.54 2.62 2.77 3.62
0.59 2.21 0.04 1.86 2.31 0.38 2.25 1.73 3.15 3.70 4.27
0.50 1.88 0.03 1.58 1.97 0.33 1.92 1.47 2.68 3.14 3.63
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-49
ProASIC3L DC and Switching Characteristics
Table 2-68 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
7.91
6.73
6.94
5.90
6.94
5.90
6.22
5.29
5.99
5.10
5.88
5.01
tZHS
7.19
6.11
6.44
5.48
6.44
5.48
5.93
5.04
5.81
4.94
5.87
4.99
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
5.79 0.04 1.18
4.92 0.03 1.00
4.84 0.04 1.18
4.11 0.03 1.00
4.84 0.04 1.18
4.11 0.03 1.00
4.13 0.04 1.18
3.52 0.03 1.00
3.91 0.04 1.18
3.32 0.03 1.00
3.85 0.04 1.18
3.28 0.03 1.00
5.90 5.18 2.41 1.98
5.01 4.40 2.05 1.69
4.93 4.43 2.74 2.60
4.19 3.77 2.33 2.21
4.93 4.43 2.74 2.60
4.19 3.77 2.33 2.21
4.21 3.92 2.97 2.99
3.58 3.33 2.53 2.54
3.98 3.80 3.02 3.09
3.39 3.23 2.57 2.63
3.87 3.85 3.09 3.48
3.29 3.28 2.63 2.96
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-69 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
5.04
4.29
4.50
3.83
4.50
3.83
4.22
3.59
4.17
3.55
4.19
3.56
tZHS
4.75
4.04
4.13
3.51
4.13
3.51
3.83
3.26
3.78
3.21
3.72
3.16
Units
ns
4 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
2.97 0.04 1.18
2.53 0.03 1.00
2.44 0.04 1.18
2.08 0.03 1.00
2.44 0.04 1.18
2.08 0.03 1.00
2.17 0.04 1.18
1.85 0.03 1.00
2.12 0.04 1.18
1.81 0.03 1.00
2.13 0.04 1.18
1.81 0.03 1.00
3.03 2.74 2.41 2.07
2.58 2.33 2.05 1.76
2.49 2.12 2.74 2.70
2.12 1.80 2.33 2.30
2.49 2.12 2.74 2.70
2.12 1.80 2.33 2.30
2.21 1.82 2.97 3.09
1.88 1.55 2.53 2.63
2.16 1.76 3.03 3.19
1.84 1.50 2.57 2.72
2.17 1.71 3.09 3.60
1.85 1.45 2.63 3.06
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-50
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-70 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
7.38
6.28
6.42
5.46
6.42
5.46
5.74
4.89
tZHS
6.69
5.69
6.04
5.14
6.04
5.14
5.57
4.74
Units
ns
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
5.27 0.04 1.17
4.49 0.03 0.99
4.32 0.04 1.17
3.68 0.03 0.99
4.32 0.04 1.17
3.68 0.03 0.99
3.66 0.04 1.17
3.12 0.03 0.99
5.37 4.68 2.03 1.79
4.57 3.98 1.73 1.52
4.40 4.03 2.33 2.35
3.75 3.43 1.98 2.00
4.40 4.03 2.33 2.35
3.75 3.43 1.98 2.00
3.73 3.56 2.54 2.71
3.17 3.03 2.16 2.30
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-71 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
4.66
3.96
4.16
3.54
4.16
3.54
3.91
3.33
tZHS
4.40
3.74
3.84
3.27
3.84
3.27
3.57
3.03
Units
ns
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
2.60 0.04 1.17
2.21 0.03 0.99
2.10 0.04 1.17
1.79 0.03 0.99
2.10 0.04 1.17
1.79 0.03 0.99
1.86 0.04 1.17
1.59 0.03 0.99
2.65 2.39 2.03 1.87
2.25 2.03 1.72 1.59
2.14 1.83 2.33 2.44
1.82 1.56 1.98 2.07
2.14 1.83 2.33 2.44
1.82 1.56 1.98 2.07
1.90 1.55 2.54 2.80
1.61 1.32 2.16 2.38
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-51
ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-72 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.77 6.24 0.05 1.86 2.31 0.50 6.36 5.30 2.45 1.98 8.37
7.31
6.22
6.50
5.53
5.92
5.04
5.79
4.93
5.81
4.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 5.31 0.04 1.58 1.97 0.43 5.41 4.51 2.08 1.68 7.12
0.77 5.10 0.05 1.86 2.31 0.50 5.20 4.49 2.79 2.64 7.21
0.66 4.34 0.04 1.58 1.97 0.43 4.42 3.82 2.37 2.24 6.13
0.77 4.29 0.05 1.86 2.31 0.50 4.37 3.91 3.03 3.05 6.39
0.66 3.65 0.04 1.58 1.97 0.43 3.72 3.32 2.58 2.60 5.43
0.77 4.05 0.05 1.86 2.31 0.50 4.12 3.78 3.08 3.17 6.13
0.66 3.44 0.04 1.58 1.97 0.43 3.51 3.22 2.62 2.70 5.22
0.77 3.94 0.05 1.86 2.31 0.50 4.01 3.80 3.15 3.60 6.03
0.66 3.35 0.04 1.58 1.97 0.43 3.41 3.23 2.68 3.06 5.13
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-73 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/Os
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.77 3.18 0.05 1.86 2.31 0.50 3.24 2.84 2.45 2.06 5.25
4.85
4.13
4.20
3.57
3.88
3.30
3.82
3.25
3.74
3.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 2.71 0.04 1.58 1.97 0.43 2.76 2.42 2.08 1.75 4.47
0.77 2.61 0.05 1.86 2.31 0.50 2.65 2.19 2.79 2.73 4.67
0.66 2.22 0.04 1.58 1.97 0.43 2.26 1.86 2.37 2.32 3.97
0.77 2.26 0.05 1.86 2.31 0.50 2.30 1.86 3.03 3.15 4.32
0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67
0.77 2.20 0.05 1.86 2.31 0.50 2.24 1.80 3.08 3.26 4.26
0.66 1.87 0.04 1.58 1.97 0.43 1.91 1.54 2.62 2.77 3.62
0.77 2.21 0.05 1.86 2.31 0.50 2.25 1.73 3.15 3.70 4.27
0.66 1.88 0.04 1.58 1.97 0.43 1.92 1.47 2.68 3.14 3.63
8 mA
Std.
–1
12 mA
16 mA
24 mA
Notes:
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-52
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-74 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/Os
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
7.91
6.73
6.94
5.90
6.94
5.90
6.22
5.29
5.99
5.10
5.88
5.01
tZHS
7.19
6.11
6.44
5.48
6.44
5.48
5.93
5.04
5.81
4.94
5.87
4.99
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
5.79 0.05 1.18
4.92 0.04 1.00
4.84 0.05 1.18
4.11 0.04 1.00
4.84 0.05 1.18
4.11 0.04 1.00
4.13 0.05 1.18
3.52 0.04 1.00
3.91 0.05 1.18
3.32 0.04 1.00
3.85 0.05 1.18
3.28 0.04 1.00
5.90 5.18 2.41 1.98
5.01 4.40 2.05 1.69
4.93 4.43 2.74 2.60
4.19 3.77 2.33 2.21
4.93 4.43 2.74 2.60
4.19 3.77 2.33 2.21
4.21 3.92 2.97 2.99
3.58 3.33 2.53 2.54
3.98 3.80 3.02 3.09
3.39 3.23 2.57 2.63
3.87 3.85 3.09 3.48
3.29 3.28 2.63 2.96
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-75 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/Os
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
5.04
4.29
4.50
3.83
4.50
3.83
4.22
3.59
4.17
3.55
4.19
3.56
tZHS
4.75
4.04
4.13
3.51
4.13
3.51
3.83
3.26
3.78
3.21
3.72
3.16
Units
ns
4 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
2.97 0.05 1.18
2.53 0.04 1.00
2.44 0.05 1.18
2.08 0.04 1.00
2.44 0.05 1.18
2.08 0.04 1.00
2.17 0.05 1.18
1.85 0.04 1.00
2.12 0.05 1.18
1.81 0.04 1.00
2.13 0.05 1.18
1.81 0.04 1.00
3.03 2.74 2.41 2.07
2.58 2.33 2.05 1.76
2.49 2.12 2.74 2.70
2.12 1.80 2.33 2.30
2.49 2.12 2.74 2.70
2.12 1.80 2.33 2.30
2.21 1.82 2.97 3.09
1.88 1.55 2.53 2.63
2.16 1.76 3.03 3.19
1.84 1.50 2.57 2.72
2.17 1.71 3.09 3.60
1.85 1.45 2.63 3.06
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
24 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-53
ProASIC3L DC and Switching Characteristics
Table 2-76 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/Os
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
7.38
6.28
6.42
5.46
6.42
5.46
5.74
4.89
tZHS
6.69
5.69
6.04
5.14
6.04
5.14
5.57
4.74
Units
ns
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
5.27 0.05 1.17
4.49 0.04 0.99
4.32 0.05 1.17
3.68 0.04 0.99
4.32 0.05 1.17
3.68 0.04 0.99
3.66 0.05 1.17
3.12 0.04 0.99
5.37 4.68 2.03 1.79
4.57 3.98 1.73 1.52
4.40 4.03 2.33 2.35
3.75 3.43 1.98 2.00
4.40 4.03 2.33 2.35
3.75 3.43 1.98 2.00
3.73 3.56 2.54 2.71
3.17 3.03 2.16 2.30
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-77 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/Os
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
4.66
3.96
4.16
3.54
4.16
3.54
3.91
3.33
tZHS
4.40
3.74
3.84
3.27
3.84
3.27
3.57
3.03
Units
ns
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
2.60 0.05 1.17
2.21 0.04 0.99
2.10 0.05 1.17
1.79 0.04 0.99
2.10 0.05 1.17
1.79 0.04 0.99
1.86 0.05 1.17
1.59 0.04 0.99
2.65 2.39 2.03 1.87
2.25 2.03 1.72 1.59
2.14 1.83 2.33 2.44
1.82 1.56 1.98 2.07
2.14 1.83 2.33 2.44
1.82 1.56 1.98 2.07
1.90 1.55 2.54 2.80
1.61 1.32 2.16 2.38
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-54
Revision 9
ProASIC3L Low Power Flash FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-78 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/Os
1.8 V
LVCMOS
VIL
Max.
VIH
Min. V
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA1
mA1 µA2 µA2
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
–0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
0.45
0.45
0.45
0.45
0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
2
4
6
8
2
4
6
8
9
11
22
44
51
74
74
10 10
10 10
10 10
10 10
10 10
10 10
4 mA
17
35
45
91
91
6 mA
8 mA
12 mA
16 mA
Notes:
VCCI – 0.45 12 12
VCCI – 0.45 16 16
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-79 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA1
V
mA mA mA1
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
1.9
1.9
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
9
11
22
44
51
74
74
4 mA
17
35
45
91
91
6 mA
6
8 mA
8
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Revision 9
2-55
ProASIC3L DC and Switching Characteristics
Table 2-80 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
V
mA mA mA1 mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
9
11
22
44
44
10 10
10 10
10 10
10 10
17
35
35
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
5
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-56
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-82 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.59 8.32 0.04 1.80 2.55 0.38 8.48 6.99 2.50 1.42 10.49 9.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 7.08 0.03 1.53 2.17 0.33 7.21 5.95 2.13 1.21 8.92
0.59 6.85 0.04 1.80 2.55 0.38 6.98 5.89 2.93 2.50 8.99
0.50 5.83 0.03 1.53 2.17 0.33 5.94 5.01 2.49 2.12 7.65
0.59 5.81 0.04 1.80 2.55 0.38 5.92 5.13 3.21 3.02 7.93
0.50 4.94 0.03 1.53 2.17 0.33 5.03 4.37 2.73 2.57 6.75
0.59 5.46 0.04 1.80 2.55 0.38 5.56 4.99 3.28 3.17 7.57
0.50 4.64 0.03 1.53 2.17 0.33 4.73 4.24 2.79 2.70 6.44
0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47
0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35
0.59 5.36 0.04 1.80 2.55 0.38 5.46 4.99 3.37 3.70 7.47
0.50 4.56 0.03 1.53 2.17 0.33 4.64 4.25 2.86 3.14 6.35
7.66
7.90
6.72
7.15
6.08
7.00
5.95
7.01
5.96
7.01
5.96
Std.
–1
Std.
–1
Std.
–1
Std.
–1
Std.
–1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-83 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.59 3.76 0.04 1.80 2.55 0.38 3.83 3.68 2.50 1.47 5.84
5.70
4.85
4.75
4.04
4.28
3.64
4.19
3.57
4.08
3.47
4.08
3.47
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 3.20 0.03 1.53 2.17 0.33 3.26 3.13 2.13 1.25 4.97
0.59 3.05 0.04 1.80 2.55 0.38 3.11 2.73 2.92 2.58 5.12
0.50 2.59 0.03 1.53 2.17 0.33 2.64 2.33 2.49 2.19 4.35
0.59 2.61 0.04 1.80 2.55 0.38 2.66 2.27 3.21 3.12 4.67
0.50 2.22 0.03 1.53 2.17 0.33 2.26 1.93 2.73 2.65 3.98
0.59 2.53 0.04 1.80 2.55 0.38 2.58 2.18 3.27 3.26 4.59
0.50 2.15 0.03 1.53 2.17 0.33 2.19 1.85 2.78 2.77 3.90
0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58
0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89
0.59 2.52 0.04 1.80 2.55 0.38 2.56 2.07 3.36 3.81 4.58
0.50 2.14 0.03 1.53 2.17 0.33 2.18 1.76 2.86 3.24 3.89
4 mA
Std.
–1
6 mA
Std.
–1
8 mA
Std.
–1
12 mA
16 mA
Notes:
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-57
ProASIC3L DC and Switching Characteristics
Table 2-84 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
9.93
8.45
8.51
7.24
7.59
6.46
7.27
6.19
7.17
6.10
7.17
6.10
tZHS
8.81
7.49
7.79
6.63
7.12
6.06
6.98
5.94
7.04
5.99
7.04
5.99
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
7.77 0.04 1.18
6.61 0.03 1.00
6.38 0.04 1.18
5.43 0.03 1.00
5.48 0.04 1.18
4.66 0.03 1.00
5.17 0.04 1.18
4.40 0.03 1.00
5.06 0.04 1.18
4.30 0.03 1.00
5.06 0.04 1.18
4.30 0.03 1.00
7.92 6.80 2.50 1.44
6.73 5.78 2.13 1.22
6.50 5.78 2.91 2.46
5.53 4.91 2.47 2.09
5.58 5.11 3.18 2.94
4.75 4.35 2.71 2.51
5.26 4.97 3.24 3.07
4.48 4.23 2.76 2.61
5.15 5.03 3.34 3.55
4.38 4.28 2.84 3.02
5.15 5.03 3.34 3.55
4.38 4.28 2.84 3.02
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-85 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
5.68
4.83
4.88
4.15
4.53
3.85
4.46
3.79
4.45
3.79
4.45
3.79
tZHS
5.53
4.71
4.65
3.96
4.22
3.59
4.14
3.52
4.05
3.45
4.05
3.45
Units
ns
2 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
3.60 0.04 1.10
3.06 0.03 0.93
2.81 0.04 1.10
2.39 0.03 0.93
2.47 0.04 1.10
2.10 0.03 0.93
2.40 0.04 1.10
2.04 0.03 0.93
2.39 0.04 1.10
2.04 0.03 0.93
2.39 0.04 1.10
2.04 0.03 0.93
3.66 3.52 2.49 1.49
3.12 3.00 2.12 1.27
2.87 2.64 2.90 2.55
2.44 2.25 2.47 2.17
2.51 2.21 3.18 3.04
2.14 1.88 2.70 2.59
2.45 2.13 3.24 3.17
2.08 1.81 2.76 2.70
2.44 2.04 3.33 3.67
2.08 1.73 2.83 3.12
2.44 2.04 3.33 3.67
2.08 1.73 2.83 3.12
ns
4 mA
Std.
–1
ns
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-58
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-86 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
9.36
7.96
7.93
6.74
7.06
6.01
7.06
6.01
tZHS
8.16
6.94
7.27
6.19
6.66
5.67
6.66
5.67
Units
ns
2 mA
4 mA
6 mA
8 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
7.21 0.04 1.17
6.13 0.03 0.99
5.81 0.04 1.17
4.94 0.03 0.99
4.96 0.04 1.17
4.22 0.03 0.99
4.96 0.04 1.17
4.22 0.03 0.99
7.35 6.14 2.03 1.32
6.25 5.23 1.72 1.12
5.92 5.26 2.39 2.25
5.03 4.47 2.03 1.91
5.05 4.65 2.64 2.69
4.30 3.96 2.25 2.29
5.05 4.65 2.64 2.69
4.30 3.96 2.25 2.29
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-87 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
5.30
4.50
4.54
3.86
4.22
3.59
4.22
3.59
tZHS
5.06
4.30
4.26
3.63
3.87
3.29
3.87
3.29
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
3.22 0.04 1.08
2.74 0.03 0.92
2.48 0.04 1.08
2.11 0.03 0.92
2.17 0.04 1.08
1.85 0.03 0.92
2.17 0.04 1.08
1.85 0.03 0.92
3.28 3.04 2.02 1.37
2.79 2.59 1.72 1.17
2.53 2.25 2.38 2.34
2.15 1.92 2.03 1.99
2.21 1.86 2.64 2.79
1.88 1.58 2.24 2.37
2.21 1.86 2.64 2.79
1.88 1.58 2.24 2.37
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-59
ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-88 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.77 8.32 0.05 1.80 2.55 0.50 8.48 6.99 2.50 1.42 10.49 9.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 7.08 0.04 1.53 2.17 0.43 7.21 5.95 2.13 1.21 8.92
0.77 6.85 0.05 1.80 2.55 0.50 6.98 5.89 2.93 2.50 8.99
0.66 5.83 0.04 1.53 2.17 0.43 5.94 5.01 2.49 2.12 7.65
0.77 5.81 0.05 1.80 2.55 0.50 5.92 5.13 3.21 3.02 7.93
0.66 4.94 0.04 1.53 2.17 0.43 5.03 4.37 2.73 2.57 6.75
0.77 5.46 0.05 1.80 2.55 0.50 5.56 4.99 3.28 3.17 7.57
0.66 4.64 0.04 1.53 2.17 0.43 4.73 4.24 2.79 2.70 6.44
0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47
0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35
0.77 5.36 0.05 1.80 2.55 0.50 5.46 4.99 3.37 3.70 7.47
0.66 4.56 0.04 1.53 2.17 0.43 4.64 4.25 2.86 3.14 6.35
7.66
7.90
6.72
7.15
6.08
7.00
5.95
7.01
5.96
7.01
5.96
4 mA
Std.
–1
6 mA
Std.
–1
8 mA
Std.
–1
12 mA
16 mA
Notes:
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-89 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.77 3.76 0.05 1.80 2.55 0.50 3.83 3.68 2.50 1.47 5.84
5.70
4.85
4.75
4.04
4.28
3.64
4.19
3.57
4.08
3.47
4.08
3.47
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 3.20 0.04 1.53 2.17 0.43 3.26 3.13 2.13 1.25 4.97
0.77 3.05 0.05 1.80 2.55 0.50 3.11 2.73 2.92 2.58 5.12
0.66 2.59 0.04 1.53 2.17 0.43 2.64 2.33 2.49 2.19 4.35
0.77 2.61 0.05 1.80 2.55 0.50 2.66 2.27 3.21 3.12 4.67
0.66 2.22 0.04 1.53 2.17 0.43 2.26 1.93 2.73 2.65 3.98
0.77 2.53 0.05 1.80 2.55 0.50 2.58 2.18 3.27 3.26 4.59
0.66 2.15 0.04 1.53 2.17 0.43 2.19 1.85 2.78 2.77 3.90
0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58
0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89
0.77 2.52 0.05 1.80 2.55 0.50 2.56 2.07 3.36 3.81 4.58
0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89
4 mA
Std.
–1
6 mA
Std.
–1
8 mA
Std.
–1
12 mA
16 mA
Notes:
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-60
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-90 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
9.93
8.45
8.51
7.24
7.59
6.46
7.27
6.19
7.17
6.10
7.17
6.10
tZHS
8.81
7.49
7.79
6.63
7.12
6.06
6.98
5.94
7.04
5.99
7.04
5.99
Units
ns
2 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
7.77 0.05 1.18
6.61 0.04 1.00
6.38 0.05 1.18
5.43 0.04 1.00
5.48 0.05 1.18
4.66 0.04 1.00
5.17 0.05 1.18
4.40 0.04 1.00
5.06 0.05 1.18
4.30 0.04 1.00
5.06 0.05 1.18
4.30 0.04 1.00
7.92 6.80 2.50 1.44
6.73 5.78 2.13 1.22
6.50 5.78 2.91 2.46
5.53 4.91 2.47 2.09
5.58 5.11 3.18 2.94
4.75 4.35 2.71 2.51
5.26 4.97 3.24 3.07
4.48 4.23 2.76 2.61
5.15 5.03 3.34 3.55
4.38 4.28 2.84 3.02
5.15 5.03 3.34 3.55
4.38 4.28 2.84 3.02
ns
4 mA
Std.
–1
ns
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-91 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
5.68
4.83
4.88
4.15
4.53
3.85
4.46
3.79
4.45
3.79
4.45
3.79
tZHS
5.53
4.71
4.65
3.96
4.22
3.59
4.14
3.52
4.05
3.45
4.05
3.45
Units
ns
2 mA
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
3.60 0.05 1.10
3.06 0.04 0.93
2.81 0.05 1.10
2.39 0.04 0.93
2.47 0.05 1.10
2.10 0.04 0.93
2.40 0.05 1.10
2.04 0.04 0.93
2.39 0.05 1.10
2.04 0.04 0.93
2.39 0.05 1.10
2.04 0.04 0.93
3.66 3.52 2.49 1.49
3.12 3.00 2.12 1.27
2.87 2.64 2.90 2.55
2.44 2.25 2.47 2.17
2.51 2.21 3.18 3.04
2.14 1.88 2.70 2.59
2.45 2.13 3.24 3.17
2.08 1.81 2.76 2.70
2.44 2.04 3.33 3.67
2.08 1.73 2.83 3.12
2.44 2.04 3.33 3.67
2.08 1.73 2.83 3.12
ns
4 mA
Std.
–1
ns
ns
6 mA
Std.
–1
ns
ns
8 mA
Std.
–1
ns
ns
12 mA
16 mA
Notes:
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-61
ProASIC3L DC and Switching Characteristics
Table 2-92 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
9.36
7.96
7.93
6.74
7.06
6.01
7.06
6.01
tZHS
8.16
6.94
7.27
6.19
6.66
5.67
6.66
5.67
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
7.21 0.05 1.17
6.13 0.04 0.99
5.81 0.05 1.17
4.94 0.04 0.99
4.96 0.05 1.17
4.22 0.04 0.99
4.96 0.05 1.17
4.22 0.04 0.99
7.35 6.14 2.03 1.32
6.25 5.23 1.72 1.12
5.92 5.26 2.39 2.25
5.03 4.47 2.03 1.91
5.05 4.65 2.64 2.69
4.30 3.96 2.25 2.29
5.05 4.65 2.64 2.69
4.30 3.96 2.25 2.29
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-93 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
5.30
4.50
4.54
3.86
4.22
3.59
4.22
3.59
tZHS
5.06
4.30
4.26
3.63
3.87
3.29
3.87
3.29
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
3.22 0.05 1.08
2.74 0.04 0.92
2.48 0.05 1.08
2.11 0.04 0.92
2.17 0.05 1.08
1.85 0.04 0.92
2.17 0.05 1.08
1.85 0.04 0.92
3.28 3.04 2.02 1.37
2.79 2.59 1.72 1.17
2.53 2.25 2.38 2.34
2.15 1.92 2.03 1.99
2.21 1.86 2.64 2.79
1.88 1.58 2.24 2.37
2.21 1.86 2.64 2.79
1.88 1.58 2.24 2.37
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-62
Revision 9
ProASIC3L Low Power Flash FPGAs
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-94 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/Os
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
V
mA mA mA1 mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
6
8
13
25
32
66
66
16
33
39
55
55
10 10
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-95 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
mA mA mA1 mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
6
8
13
25
32
66
66
16
33
39
55
55
10 10
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Revision 9
2-63
ProASIC3L DC and Switching Characteristics
Table 2-96 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA1
mA1 µA2 µA2
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
2
4
13
25
16
33
10 10
10 10
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
5
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-64
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-98 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.59 8.65 0.04 1.99 2.77 0.38 8.81 7.17 3.06 2.41 10.83 9.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 7.36 0.03 1.69 2.36 0.33 7.50 6.10 2.61 2.05 9.21
0.59 7.40 0.04 1.99 2.77 0.38 7.53 6.26 3.39 3.02 9.55
0.50 6.29 0.03 1.69 2.36 0.33 6.41 5.33 2.89 2.57 8.12
0.59 6.94 0.04 1.99 2.77 0.38 7.07 6.09 3.46 3.19 9.08
0.50 5.91 0.03 1.69 2.36 0.33 6.01 5.18 2.94 2.72 7.73
0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99
0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65
0.59 6.85 0.04 1.99 2.77 0.38 6.98 6.10 3.57 3.80 8.99
0.50 5.83 0.03 1.69 2.36 0.33 5.94 5.19 3.04 3.23 7.65
7.81
8.27
7.04
8.11
6.90
8.11
6.90
8.11
6.90
Std.
–1
Std.
–1
Std.
–1
Std.
–1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-99 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.59 3.55 0.04 1.99 2.77 0.38 3.62 3.22 3.05 2.51 5.63
5.23
4.45
4.65
3.96
4.54
3.86
4.41
3.75
4.41
3.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.50 3.02 0.03 1.69 2.36 0.33 3.08 2.74 2.60 2.14 4.79
0.59 3.03 0.04 1.99 2.77 0.38 3.08 2.64 3.38 3.13 5.10
0.50 2.58 0.03 1.69 2.36 0.33 2.62 2.25 2.87 2.66 4.34
0.59 2.93 0.04 1.99 2.77 0.38 2.98 2.53 3.45 3.30 4.99
0.50 2.49 0.03 1.69 2.36 0.33 2.54 2.15 2.93 2.81 4.25
0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96
0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22
0.59 2.90 0.04 1.99 2.77 0.38 2.95 2.39 3.57 3.94 4.96
0.50 2.46 0.03 1.69 2.36 0.33 2.51 2.04 3.03 3.35 4.22
Std.
–1
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-65
ProASIC3L DC and Switching Characteristics
Table 2-100 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
tZHS
9.02
7.68
8.22
7.00
8.06
6.86
8.12
6.91
8.12
6.91
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
8.00 0.04 1.18
6.80 0.03 1.00
6.91 0.04 1.18
5.88 0.03 1.00
6.51 0.04 1.18
5.54 0.03 1.00
6.41 0.04 1.18
5.45 0.03 1.00
6.41 0.04 1.18
5.45 0.03 1.00
8.15 7.01 3.06 2.38 10.16
6.93 5.96 2.60 2.02
7.04 6.21 3.37 2.94
5.99 5.28 2.87 2.50
6.63 6.05 3.45 3.09
5.64 5.15 2.93 2.63
6.53 6.11 3.56 3.64
5.56 5.20 3.03 3.10
6.53 6.11 3.56 3.64
5.56 5.20 3.03 3.10
8.64
9.05
7.70
8.64
7.35
8.54
7.27
8.54
7.27
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-101 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
5.68
4.83
4.88
4.15
4.53
3.85
4.46
3.79
4.45
3.79
tZHS
5.53
4.71
4.65
3.96
4.22
3.59
4.14
3.52
4.05
3.45
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
0.54
0.46
3.60 0.04 1.10
3.06 0.03 0.93
2.81 0.04 1.10
2.39 0.03 0.93
2.47 0.04 1.10
2.10 0.03 0.93
2.40 0.04 1.10
2.04 0.03 0.93
2.39 0.04 1.10
2.04 0.03 0.93
3.66 3.52 2.49 1.49
3.12 3.00 2.12 1.27
2.87 2.64 2.90 2.55
2.44 2.25 2.47 2.17
2.51 2.21 3.18 3.04
2.14 1.88 2.70 2.59
2.45 2.13 3.24 3.17
2.08 1.81 2.76 2.70
2.44 2.04 3.33 3.67
2.08 1.73 2.83 3.12
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-66
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-102 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
9.46
8.05
8.42
7.16
tZHS
8.40
7.14
7.67
6.52
Units
ns
2 mA
4 mA
Std.
–1
0.54
0.46
0.54
0.46
7.32 0.04 1.17
6.22 0.03 0.99
6.29 0.04 1.17
5.35 0.03 0.99
7.45 6.38 2.44 2.18
6.34 5.43 2.08 1.86
6.40 5.65 2.73 2.70
5.45 4.81 2.33 2.29
ns
Std.
–1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-103 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.38
0.33
0.38
0.33
tZL
tZH
tLZ
tHZ
tZLS
4.97
4.23
4.58
3.90
tZHS
4.64
3.95
4.15
3.53
Units
ns
2 mA
4 mA
Notes:
Std.
–1
0.54
0.46
0.54
0.46
2.90 0.04 1.28
2.47 0.03 1.09
2.52 0.04 1.28
2.15 0.03 1.09
2.95 2.63 2.44 2.29
2.51 2.24 2.07 1.95
2.57 2.14 2.73 2.82
2.19 1.82 2.32 2.40
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-67
ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-104 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.77 8.65 0.05 1.99 2.77 0.50 8.81 7.17 3.06 2.41 10.83 9.18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 7.36 0.04 1.69 2.36 0.43 7.50 6.10 2.61 2.05 9.21
0.77 7.40 0.05 1.99 2.77 0.50 7.53 6.26 3.39 3.02 9.55
0.66 6.29 0.04 1.69 2.36 0.43 6.41 5.33 2.89 2.57 8.12
0.77 6.94 0.05 1.99 2.77 0.50 7.07 6.09 3.46 3.19 9.08
0.66 5.91 0.04 1.69 2.36 0.43 6.01 5.18 2.94 2.72 7.73
0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99
0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65
0.77 6.85 0.05 1.99 2.77 0.50 6.98 6.10 3.57 3.80 8.99
0.66 5.83 0.04 1.69 2.36 0.43 5.94 5.19 3.04 3.23 7.65
7.81
8.27
7.04
8.11
6.90
8.11
6.90
8.11
6.90
Std.
–1
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-105 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.77 3.55 0.05 1.99 2.77 0.50 3.62 3.22 3.05 2.51 5.63
5.23
4.45
4.65
3.96
4.54
3.86
4.41
3.75
4.41
3.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.66 3.02 0.04 1.69 2.36 0.43 3.08 2.74 2.60 2.14 4.79
0.77 3.03 0.05 1.99 2.77 0.50 3.08 2.64 3.38 3.13 5.10
0.66 2.58 0.04 1.69 2.36 0.43 2.62 2.25 2.87 2.66 4.34
0.77 2.93 0.05 1.99 2.77 0.50 2.98 2.53 3.45 3.30 4.99
0.66 2.49 0.04 1.69 2.36 0.43 2.54 2.15 2.93 2.81 4.25
0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96
0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22
0.77 2.90 0.05 1.99 2.77 0.50 2.95 2.39 3.57 3.94 4.96
0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22
Std.
–1
Std.
–1
Std.
–1
Std.
–1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-68
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-106 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
tZHS
9.02
7.68
8.22
7.00
8.06
6.86
8.12
6.91
8.12
6.91
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
8.00 0.05 1.18
6.80 0.04 1.00
6.91 0.05 1.18
5.88 0.04 1.00
6.51 0.05 1.18
5.54 0.04 1.00
6.41 0.05 1.18
5.45 0.04 1.00
6.41 0.05 1.18
5.45 0.04 1.00
8.15 7.01 3.06 2.38 10.16
6.93 5.96 2.60 2.02
7.04 6.21 3.37 2.94
5.99 5.28 2.87 2.50
6.63 6.05 3.45 3.09
5.64 5.15 2.93 2.63
6.53 6.11 3.56 3.64
5.56 5.20 3.03 3.10
6.53 6.11 3.56 3.64
5.56 5.20 3.03 3.10
8.64
9.05
7.70
8.64
7.35
8.54
7.27
8.54
7.27
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-107 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
5.33
4.53
4.90
4.17
4.82
4.10
4.80
4.08
4.80
4.08
tZHS
5.12
4.36
4.59
3.90
4.48
3.81
4.37
3.72
4.37
3.72
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
0.70
0.60
3.26 0.05 1.30
2.77 0.04 1.10
2.84 0.05 1.30
2.41 0.04 1.10
2.76 0.05 1.30
2.35 0.04 1.10
2.74 0.05 1.30
2.33 0.04 1.10
2.74 0.05 1.30
2.33 0.04 1.10
3.32 3.11 3.05 2.49
2.82 2.64 2.59 2.12
2.89 2.57 3.37 3.06
2.46 2.19 2.86 2.60
2.81 2.47 3.44 3.21
2.39 2.10 2.92 2.73
2.79 2.36 3.55 3.78
2.37 2.01 3.02 3.22
2.79 2.36 3.55 3.78
2.37 2.01 3.02 3.22
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-69
ProASIC3L DC and Switching Characteristics
Table 2-108 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
9.46
8.05
8.42
7.16
tZHS
8.40
7.14
7.67
6.52
Units
ns
2 mA
4 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
7.32 0.05 1.17
6.22 0.04 0.99
6.29 0.05 1.17
5.35 0.04 0.99
7.45 6.38 2.44 2.18
6.34 5.43 2.08 1.86
6.40 5.65 2.73 2.70
5.45 4.81 2.33 2.29
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-109 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.50
0.43
0.50
0.43
tZL
tZH
tLZ
tHZ
tZLS
4.97
4.23
4.58
3.90
tZHS
4.64
3.95
4.15
3.53
Units
ns
2 mA
4 mA
Notes:
Std.
–1
0.70
0.60
0.70
0.60
2.90 0.05 1.28
2.47 0.04 1.09
2.52 0.05 1.28
2.15 0.04 1.09
2.95 2.63 2.44 2.29
2.51 2.24 2.07 1.95
2.57 2.14 2.73 2.82
2.19 1.82 2.32 2.40
ns
Std.
–1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-70
Revision 9
ProASIC3L Low Power Flash FPGAs
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2
V applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-110 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.2 V
LVCMO
S
1
1
2
2
VIL
VIH
VOL
VOH
IOL IOH IOSH
IOSL
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA mA mA
Max.
mA
µA µA
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2
2
TBD
TBD
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-111 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.2 V
LVCMOS
1
1
2
2
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSH
Max. Max.
mA mA mA mA µA µA
TBD 10 10
IOSL IIL IIH
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
V
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
TBD
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-112 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.2 V
LVCMOS
1
1
2
2
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSH
IOSL
IIL IIH
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA mA mA
Max.
mA
V
µA µA
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
TBD
TBD
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Revision 9
2-71
ProASIC3L DC and Switching Characteristics
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
5 pF
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-11 • AC Loading
Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-72
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.2 V DC Core Voltage
Table 2-114 • 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Speed
Unit
Strength
Grade tDOUT tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
s
2 mA
Std.
–1
0.77 11.80 0.05 2.38 3.52 0.50 10.97 8.61 4.79 4.38 12.91 10.55
0.66 10.04 0.04 2.02 2.99 0.43 9.33 7.32 4.08 3.72 10.98 8.97
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-115 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Pro I/O Banks
Drive
Strength
Speed
Grade tDOUT tDP
Unit
s
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
5.90
5.02
2 mA
Std.
–1
0.77
0.66
4.84 0.05 2.38 3.52 0.50
4.12 0.04 2.02 2.99 0.43
4.50 3.96 4.78 4.51 6.44
3.83 3.37 4.06 3.84 5.48
ns
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-116 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
Std.
–1
0.70 8.77 0.05 1.82 0.50 6.17 5.45 2.80 2.77 8.11 7.39
0.60 7.46 0.04 1.55 0.43 5.25 4.63 2.39 2.35 6.90 6.28
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-117 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
Std.
–1
0.70 3.73 0.05 1.82 0.50 2.48 2.06 2.80 2.89 4.42 4.00
0.60 3.17 0.04 1.55 0.43 2.11 1.76 2.38 2.46 3.76 3.41
ns
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-118 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
Std.
–1
0.70 9.67 0.05 1.83 0.50 6.78 5.99 4.08 4.57 8.72 7.93
0.60 8.23 0.04 1.56 0.43 5.77 5.09 3.47 3.88 7.42 6.74
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-73
ProASIC3L DC and Switching Characteristics
Table 2-119 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
2 mA
Std.
–1
0.70 4.17 0.05 1.83 0.50 2.79 2.48 4.23 4.55 4.73 4.42
0.60 3.54 0.04 1.56 0.43 2.37 2.11 3.60 3.87 4.02 3.76
ns
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-74
Revision 9
ProASIC3L Low Power Flash FPGAs
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
Table 2-120 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
VIH
Max.
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Min.
V
Max.
V
Min.
V
Max.
V
Max.
mA1
Max.
mA1
Drive Strength
Per PCI specification
Notes:
V
V
mA mA
µA2 µA2
Per PCI curves
10 10
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path
characterization are described in Figure 2-12.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-12 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in Table 2-121.
Table 2-121 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
10
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-122 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Speed Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT
3.33 0.38
2.84 0.33
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
Std.
–1
0.59 2.52
0.50 2.15
0.04 2.47
0.03 2.10
2.57 1.80
2.19 1.53
2.95 3.25
2.51 2.77
4.58 3.81
3.90 3.24
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-75
ProASIC3L DC and Switching Characteristics
Table 2-123 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT
0.38 2.46
0.33 2.09
tZL
tZH
tLZ
tHZ
tZLS
3.77
3.21
tZHS Units
Std.
–1
0.54 2.41
0.46 2.05
0.04 0.78
0.03 0.66
1.76 2.89
1.49 2.46
3.22 4.47
2.74 3.80
ns
ns
0.54
0.46
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-124 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT
0.38 2.12
0.33 1.80
tZL
tZH
tLZ
tHZ
tZLS
3.55
3.02
tZHS Units
Std.
–1
0.54 2.08
0.46 1.77
0.04 0.77
0.03 0.65
1.53 2.51
1.31 2.14
2.90 4.13
2.47 3.51
ns
ns
0.54
0.46
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-125 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Speed Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT
3.33 0.50
2.84 0.43
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
Std.
–1
0.77 2.52
0.66 2.15
0.05 2.47
0.04 2.10
2.57 1.80
2.19 1.53
2.95 3.25
2.51 2.77
4.58 3.81
3.90 3.24
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-126 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT
0.50 2.46
0.43 2.09
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
Std.
–1
0.70 2.41
0.60 2.05
0.05 0.78
0.04 0.66
1.76 2.89
1.49 2.46
3.22 4.47
2.74 3.80
3.77 0.73
3.21 0.62
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-127 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT
0.50 2.12
0.43 1.80
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
Std.
–1
0.70 2.08
0.60 1.77
0.05 0.77
0.04 0.65
1.53 2.51
1.31 2.14
2.90 4.13
2.47 3.51
3.55 0.73
3.02 0.62
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-76
Revision 9
ProASIC3L Low Power Flash FPGAs
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 2-128 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
25 mA3
–0.3 VREF – 0.05 VREF + 0.05
3.6
0.4
–
25 25
268
181
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-13 • AC Loading
Table 2-129 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Revision 9
2-77
ProASIC3L DC and Switching Characteristics
Timing Characteristics
Table 2-130 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.87
1.59
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
3.85
3.27
tZHS
3.88
3.30
Units
ns
Std.
–1
2.12
1.80
1.83
1.56
1.87
1.59
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-131 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Applicable to Pro I/Os
Speed
Grade
tDOUT
0.77
tDP
1.87
1.59
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
3.85
3.27
tZHS
3.88
3.30
Units
ns
Std.
2.12
1.80
1.83
1.56
1.87
1.59
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-78
Revision 9
ProASIC3L Low Power Flash FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V
Table 2-132 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
25 mA3
–0.3 VREF – 0.05 VREF + 0.05
2.7
0.4
–
25 25
169
124
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-14 • AC Loading
Table 2-133 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Revision 9
2-79
ProASIC3L DC and Switching Characteristics
Timing Characteristics
Table 2-134 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.92
1.63
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
3.96
3.37
tZHS
3.93
3.34
Units
ns
Std.
–1
2.05
1.75
1.95
1.66
1.92
1.63
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-135 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.92
1.63
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
3.96
3.37
tZHS
3.93
3.34
Units
ns
Std.
2.05
1.75
1.95
1.66
1.92
1.63
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-80
Revision 9
ProASIC3L Low Power Flash FPGAs
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V
Table 2-136 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
35 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.6
–
35 35
268
181
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-15 • AC Loading
Table 2-137 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
10
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Timing Characteristics
Table 2-138 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.85
1.57
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
3.90
3.31
tZHS
3.86
3.29
Units
ns
Std.
2.12
1.80
1.88
1.60
1.85
1.57
–1
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-139 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.0 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.85
1.57
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
3.90
3.31
tZHS
3.86
3.29
Units
ns
Std.
2.12
1.80
1.88
1.60
1.85
1.57
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-81
ProASIC3L DC and Switching Characteristics
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-140 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA1
mA mA mA1
µA2 µA2
33 mA
–0.3 VREF – 0.1 VREF + 0.1
2.7
0.6
–
33 33
169
124
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-16 • AC Loading
Table 2-141 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
10
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
2-82
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
Table 2-142 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.0 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.99
1.69
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
4.03
3.43
tZHS
3.90
3.32
Units
ns
Std.
–1
2.05
1.75
2.02
1.72
1.89
1.61
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-15 on page 2-12 for derating
values.
Table 2-143 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.0 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.99
1.69
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
4.03
3.43
tZHS
3.90
3.32
Units
ns
Std.
2.05
1.75
2.02
1.72
1.89
1.61
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-15 on page 2-12 for derating
values.
Revision 9
2-83
ProASIC3L DC and Switching Characteristics
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-144 • Minimum and Maximum DC Input and Output Levels
HSTL
Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA1
mA mA mA1
µA2 µA2
8 mA
–0.3 VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4
8
8
32
39
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
V
TT
HSTL
Class I
50
Test Point
20 pF
Figure 2-17 • AC Loading
Table 2-145 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input Low (V)
Input High (V)
(V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
20
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
2-84
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
Table 2-146 • HSTL Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
2.86
2.43
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
4.93
4.19
tZHS
4.84
4.12
Units
ns
Std.
–1
2.50
2.12
2.91
2.48
2.83
2.41
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-147 • HSTL Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
2.86
2.43
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
4.93
4.19
tZHS
4.84
4.12
Units
ns
Std.
2.50
2.12
2.91
2.48
2.83
2.41
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-85
ProASIC3L DC and Switching Characteristics
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-148 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max. Max.
Min.
V
Max.
Max.
V
V
mA mA mA1
mA1 µA2 µA2
15 mA3
–0.3 VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4 15 15
66
55
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
HSTL
Class II
25
Test Point
20 pF
Figure 2-18 • AC Loading
Table 2-149 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
20
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
2-86
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
Table 2-150 • HSTL Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
2.72
2.32
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
4.78
4.07
tZHS
4.45
3.79
Units
ns
Std.
–1
2.50
2.12
2.77
2.36
2.44
2.08
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-151 • HSTL Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 1.4 V VREF = 0.75 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
2.72
2.32
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
4.78
4.07
tZHS
4.45
3.79
Units
ns
Std.
2.50
2.12
2.77
2.36
2.44
2.08
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-87
ProASIC3L DC and Switching Characteristics
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-152 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class
I
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA1
mA1 µA2 µA2
15 mA
–0.3 VREF – 0.2 VREF + 0.2
2.7
0.54 VCCI – 0.62 15 15
83
87
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class I
50
Test Point
25
30 pF
Figure 2-19 • AC Loading
Table 2-153 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.25
1.25
1.25
30
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
2-88
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
Table 2-154 • SSTL2 Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Applicable to Pro I/Os
Speed
Grade
tDOUT
0.59
tDP
1.91
1.63
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
1.95
1.66
tZHS
1.66
1.41
Units
ns
Std.
–1
1.89
1.61
1.95
1.66
1.66
1.41
0.50
0.33
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-155 • SSTL2 Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.91
1.63
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
1.95
1.66
tZHS
1.66
1.41
Units
ns
Std.
1.89
1.61
1.95
1.66
1.66
1.41
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-89
ProASIC3L DC and Switching Characteristics
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-156 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max. Max.
Min.
V
Max.
Max.
V
V
mA mA mA1
mA1 µA2 µA2
18 mA
–0.3 VREF – 0.2 VREF + 0.2 2.7
0.35
VCCI – 0.43 18 18
169
124
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class II
25
Test Point
25
30 pF
Figure 2-20 • AC Loading
Table 2-157 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
1.25
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.25
1.25
30
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Timing Characteristics
Table 2-158 • SSTL2 Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.95
1.66
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
1.99
1.69
tZHS
1.59
1.36
Units
Std.
1.89
1.61
1.99
1.69
1.59
1.36
ns
ns
–1
0.50
0.33
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-159 • SSTL2 Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 2.3 V VREF = 1.25 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.95
1.66
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
1.99
1.69
tZHS
1.59
1.36
Units
ns
Std.
1.89
1.61
1.99
1.69
1.59
1.36
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-90
Revision 9
ProASIC3L Low Power Flash FPGAs
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-160 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA1
mA1 µA2 µA2
14 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.7
VCCI – 1.1 14 14
51
54
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class I
50
Test Point
25
30 pF
Figure 2-21 • AC Loading
Table 2-161 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
1.485
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.5
1.5
30
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Timing Characteristics
Table 2-162 • SSTL3 Class I – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
2.08
1.77
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
2.11
1.80
tZHS
1.65
1.41
Units
Std.
1.81
1.54
2.11
1.80
1.65
1.41
ns
ns
–1
0.50
0.33
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-163 • SSTL3 Class I – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
2.08
1.77
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
2.11
1.80
tZHS
1.65
1.41
Units
ns
Std.
1.81
1.54
2.11
1.80
1.65
1.41
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-91
ProASIC3L DC and Switching Characteristics
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-164 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA1
mA1 µA2 µA2
21 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.5
VCCI – 0.9 21 21
103
109
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class II
25
Test Point
25
30 pF
Figure 2-22 • AC Loading
Table 2-165 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
1.485
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.5
1.5
30
* Measuring point = Vtrip. See Table 2-15 on page 2-12 for a complete table of trip points.
Timing Characteristics
Table 2-166 • SSTL3 Class II – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.59
tDP
1.86
1.58
tDIN
0.04
0.03
tPY
tEOUT
0.38
tZL
tZH
tLZ
tHZ
tZLS
1.89
1.61
tZHS
1.50
1.28
Units
Std.
1.81
1.54
1.89
1.61
1.50
1.28
ns
ns
–1
0.50
0.33
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-167 • SSTL3 Class II – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
Speed
Grade
tDOUT
0.77
tDP
1.86
1.58
tDIN
0.05
0.04
tPY
tEOUT
0.50
tZL
tZH
tLZ
tHZ
tZLS
1.89
1.61
tZHS
1.50
1.28
Units
ns
Std.
1.81
1.54
1.89
1.61
1.50
1.28
–1
0.66
0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-92
Revision 9
ProASIC3L Low Power Flash FPGAs
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the
user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
N
P
N
165 Ω
165 Ω
Z0 = 50 Ω
140 Ω
Z0 = 50 Ω
INBUF_LVDS
+
–
100 Ω
Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation
Revision 9
2-93
ProASIC3L DC and Switching Characteristics
Table 2-168 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
2.5
Max.
2.625
1.25
1.6
Units
V
Output Low Voltage
VOL
1.075
1.425
0.91
0.91
V
Output High Voltage
VOH
1.25
0.65
0.65
0
V
4
Output Lower Current
Output High Current
IOL
1.16
1.16
2.925
10
mA
mA
V
4
IOH
Input Voltage
VI
3
Input High Leakage Current
Input Low Leakage Current
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
IIH
µA
µA
mV
V
3
IIL
10
VODIFF
VOCM
VICM
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
V
VIDIFF
mV
Notes:
1. ± 5%
2. Differential input voltage = ±350 mV.
3. Currents are measured at 85°C junction temperature.
4.
I
/I is defined by V
/(Resistor Network).
OL OH
ODIFF
Table 2-169 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.075
1.325
Cross point
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
2-94
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-170 • LVDS – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/O Banks
Speed Grade
tDOUT
0.59
tDP
1.65
1.40
tDIN
0.04
0.03
tPY
Units
ns
Std.
–1
2.18
1.85
0.50
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-171 • LVDS – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.54
tDP
1.65
1.40
tDIN
0.04
0.03
tPY
Units
ns
Std.
–1
1.44
1.23
0.46
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-172 • LVDS – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Pro I/O Banks
Speed Grade
tDOUT
0.77
tDP
1.68
1.43
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
2.18
1.85
0.66
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-173 • LVDS – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.70
tDP
1.65
1.40
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.44
1.23
0.60
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-95
ProASIC3L DC and Switching Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A
sample application is given in Figure 2-24. The input and output buffer delays are available in the LVDS
section in Table 2-168 on page 2-94.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and
RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
2-96
Revision 9
ProASIC3L Low Power Flash FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
N
OUTBUF_LVPECL
100 Ω
100 Ω
Z0 = 50 Ω
187 W
INBUF_LVPECL
+
–
100 Ω
Z0 = 50 Ω
N
Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-174 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
3.3
Min.
Max.
Units
V
3.0
3.6
VOL
Output Low Voltage
0.96
1.8
1.27
2.11
3.3
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.9
V
VOH
Output High Voltage
V
VIL, VIH
VODIFF
VOCM
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
0
V
0.625
1.762
1.01
300
0.97 0.625
1.98 1.762
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
V
V
VICM
2.57
1.01
300
V
VIDIFF
mV
Table 2-175 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.64
1.94
Cross point
* Measuring point = Vtrip. See Table 2-26 on page 2-25 for a complete table of trip points.
Revision 9
2-97
ProASIC3L DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-176 • LVPECL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Speed Grade
tDOUT
0.59
tDP
1.64
1.40
tDIN
0.04
0.03
tPY
Units
ns
Std.
–1
1.97
1.67
0.50
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-177 • LVPECL – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.54
tDP
1.62
1.38
tDIN
0.04
0.03
tPY
Units
ns
Std.
–1
1.26
1.08
0.46
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-178 • LVPECL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Pro I/O Banks
Speed Grade
tDOUT
0.77
tDP
1.62
1.37
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.97
1.67
0.66
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-179 • LVPECL – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.70
tDP
1.62
1.38
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.26
1.08
0.60
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-98
Revision 9
ProASIC3L Low Power Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
DFN1E1P1
DFN1E1P1
G
E
E
EOUT
B
A
H
I
PRE
J
D
Q
DFN1E1P1
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
INBUF
INBUF
CLKBUF
Postive-Edge Triggered
Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Revision 9
2-99
ProASIC3L DC and Switching Characteristics
Table 2-180 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
G, H
tOHE
G, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
J, H
tOESUE
tOEHE
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
K, H
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
* See Figure 2-26 on page 2-99 for more information.
2-100
Revision 9
ProASIC3L Low Power Flash FPGAs
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
AA
DD
CLR
LL
HH
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Revision 9
2-101
ProASIC3L DC and Switching Characteristics
Table 2-181 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
II, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
* See Figure 2-27 on page 2-101 for more information.
2-102
Revision 9
ProASIC3L Low Power Flash FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
Data
tIHD
50%
50%
1
0
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-28 • Input Register Timing Diagram
Revision 9
2-103
ProASIC3L DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-182 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
–1 Std. Units
0.24 0.29 ns
0.27 0.31 ns
0.00 0.00 ns
0.38 0.45 ns
0.00 0.00 ns
0.46 0.54 ns
0.46 0.54 ns
0.00 0.00 ns
0.23 0.27 ns
0.00 0.00 ns
0.23 0.27 ns
0.19 0.22 ns
0.19 0.22 ns
0.31 0.36 ns
0.28 0.32 ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-183 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tICLKQ
Description
Clock-to-Q of the Input Data Register
–1 Std. Units
0.32 0.37 ns
0.35 0.41 ns
0.00 0.00 ns
0.50 0.58 ns
0.00 0.00 ns
0.60 0.71 ns
0.60 0.71 ns
0.00 0.00 ns
0.30 0.35 ns
0.00 0.00 ns
0.30 0.35 ns
0.19 0.22 ns
0.19 0.22 ns
0.31 0.36 ns
0.28 0.32 ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-104
Revision 9
ProASIC3L Low Power Flash FPGAs
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
tOREMPRE
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOHE
50%
50%
tOSUE
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-29 • Output Register Timing Diagram
Revision 9
2-105
ProASIC3L DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-184 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–1 Std. Units
Clock-to-Q of the Output Data Register
0.60 0.71
0.32 0.37
0.00 0.00
0.45 0.53
0.00 0.00
0.82 0.96
0.82 0.96
0.00 0.00
0.23 0.27
0.00 0.00
0.23 0.27
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-185 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
–1 Std. Units
0.78 0.92
0.42 0.49
0.00 0.00
0.58 0.69
0.00 0.00
1.07 1.26
1.07 1.26
0.00 0.00
0.30 0.35
0.00 0.00
0.30 0.35
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-106
Revision 9
ProASIC3L Low Power Flash FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD OEHD
t
50% 50%
1
0
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
50%
tOERECPRE
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
EOUT
Figure 2-30 • Output Enable Register Timing Diagram
Revision 9
2-107
ProASIC3L DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-186 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
–1 Std. Units
Clock-to-Q of the Output Enable Register
0.45 0.53
0.32 0.37
0.00 0.00
0.44 0.52
0.00 0.00
0.68 0.80
0.68 0.80
0.00 0.00
0.23 0.27
0.00 0.00
0.23 0.27
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
1.2 V DC Core Voltage
Table 2-187 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tOECLKQ
tOESUD
Description
Clock-to-Q of the Output Enable Register
–1 Std. Units
0.59 0.70
0.42 0.49
0.00 0.00
0.58 0.68
0.00 0.00
0.89 1.04
0.89 1.04
0.00 0.00
0.30 0.35
0.00 0.00
0.30 0.35
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-108
Revision 9
ProASIC3L Low Power Flash FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-31 • Input DDR Timing Model
Table 2-188 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
Revision 9
2-109
ProASIC3L DC and Switching Characteristics
CLK
t
t
DDRISUD
DDRIHD
Data
CLR
1
2
3
4
5
6
7
8
9
t
DDRIRECCLR
t
DDRIREMCLR
t
DDRICLKQ1
t
t
DDRICLR2Q1
Out_QF
Out_QR
6
2
4
t
DDRICLKQ2
DDRICLR2Q2
7
3
5
Figure 2-32 • Input DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-189 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
Description
–1
Std. Units
Clock-to-Out Out_QR for Input DDR
0.28 0.33
0.40 0.47
0.29 0.34
0.25 0.29
0.00 0.00
0.00 0.00
0.47 0.55
0.58 0.68
0.00 0.00
0.23 0.27
0.18 0.22
0.31 0.36
0.28 0.32
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
ns
tDDRISUD2
Data Setup for Input DDR (rise)
ns
tDDRIHD1
Data Hold for Input DDR (fall)
ns
tDDRIHD2
Data Hold for Input DDR (rise)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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ProASIC3L Low Power Flash FPGAs
1.2 V DC Core Voltage
Table 2-190 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out Out_QR for Input DDR
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD1
–1
Std. Units
0.43 0.37
0.61 0.52
0.44 0.38
0.39 0.33
0.00 0.00
0.00 0.00
0.73 0.62
0.89 0.76
0.00 0.00
0.35 0.30
0.22 0.19
0.36 0.31
0.32 0.28
TBD TBD
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
ns
tDDRISUD2
Data Setup for Input DDR (rise)
ns
tDDRIHD1
Data Hold for Input DDR (fall)
ns
tDDRIHD2
Data Hold for Input DDR (rise)
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-111
ProASIC3L DC and Switching Characteristics
Output DDR Module
Output DDR
A
B
Data_F
(from core)
X
X
FF1
Out
0
1
CLK
E
X
CLKBUF
C
X
OUTBUF
D
Data_R
(from core)
X
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-33 • Output DDR Timing Model
Table 2-191 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
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ProASIC3L Low Power Flash FPGAs
CLK
tDDROHD2
tDDROSUD2
3
4
9
5
Data_F
1
2
tDDROHD1
tDDROREMCLR
Data_R 6
CLR
7
8
10
11
tDDRORECCLR
tDDROREMCLR
tDDROCLKQ
tDDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-34 • Output DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-192 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDRISUD1
Description
–1
Std. Units
Clock-to-Out of DDR for Output DDR
0.72 0.84
0.39 0.45
0.39 0.45
0.00 0.00
0.00 0.00
0.82 0.96
0.00 0.00
0.23 0.27
0.19 0.22
0.31 0.36
0.28 0.32
ns
ns
Data_F Data Setup for Output DDR
tDDROSUD2
tDDROHD1
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
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ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-193 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDRISUD1
–1
Std. Units
1.10 0.94
0.59 0.50
0.59 0.50
0.00 0.00
0.00 0.00
1.26 1.07
0.00 0.00
0.35 0.30
0.22 0.19
0.36 0.31
0.32 0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data_F Data Setup for Output DDR
tDDROSUD2
tDDROHD1
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
tDDROHD2
Data_R Data Hold for Output DDR
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
TBD TBD MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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ProASIC3L Low Power Flash FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the IGLOO,® Fusion,
and ProASIC3 Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-35 • Sample of Combinatorial Cells
Revision 9
2-115
ProASIC3L DC and Switching Characteristics
tPD
A
B
NAND2 or
Any Combinatorial
Logic
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)
)
where edges are applicable for the particular
combinatorial cell
VCC
50%
50%
A, B, C
GND
50%
VCC
50%
OUT
OUT
GND
VCC
tPD
tPD
(RR)
(FF)
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-36 • Timing Model and Waveforms
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Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-194 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y =!A
Parameter
tPD
–1
Std.
0.48
0.57
0.57
0.58
0.58
0.88
0.84
1.05
0.61
0.67
Units
ns
0.41
0.48
0.48
0.50
0.50
0.75
0.71
0.89
0.52
0.57
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y =!(A · B)
tPD
ns
Y = A + B
tPD
ns
NOR2
Y =!(A + B)
Y = A ⊕ B
Y = MAJ(A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
1.2 V DC Core Voltage
Table 2-195 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
–1
Std.
0.63
0.74
0.74
0.76
0.76
1.16
1.09
1.37
0.79
0.88
Units
ns
0.54
0.63
0.63
0.65
0.65
0.98
0.93
1.17
0.68
0.75
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A , B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
Revision 9
2-117
ProASIC3L DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3
Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-37 • Sample of Sequential Cells
2-118
Revision 9
ProASIC3L Low Power Flash FPGAs
t
t
CKMPWH CKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
HD
t
SUD
50%
50%
Data
EN
0
50%
t
t
RECPRE
WPRE
t
REMPRE
t
HE
50%
50%
50%
t
PRE
CLR
Out
SUE
t
t
t
REMCLR
RECCLR
WCLR
50%
50%
50%
t
PRE2Q
t
CLR2Q
50%
50%
50%
t
CLKQ
Figure 2-38 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-196 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–1
Std. Units
Clock-to-Q of the Core Register
0.56 0.66
0.44 0.51
0.00 0.00
0.46 0.55
0.00 0.00
0.41 0.48
0.41 0.48
0.00 0.00
0.23 0.27
0.00 0.00
0.23 0.27
0.30 0.34
0.30 0.34
0.56 0.64
0.56 0.64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
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ProASIC3L DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-197 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
–1
Std. Units
Clock-to-Q of the Core Register
0.73 0.86
0.57 0.67
0.00 0.00
0.61 0.71
0.00 0.00
0.53 0.63
0.53 0.63
0.00 0.00
0.30 0.35
0.00 0.00
0.30 0.35
0.30 0.34
0.30 0.34
0.56 0.64
0.56 0.64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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Revision 9
ProASIC3L Low Power Flash FPGAs
Global Resource Characteristics
A3P250L Clock Tree Topology
Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-39 is driven by a CCC located on the west side of the A3P250L device.
It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-39 • Example of Global Tree Use in an A3P250L Device for Clock Routing
Revision 9
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ProASIC3L DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-126. Table 2-198 to Table 2-204 on page 2-125
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
Timing Characteristics
Table 2-198 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.82 1.06 0.96 1.25
0.80 1.09 0.94 1.28
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.29
0.34
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Table 2-199 • A3P250L Global Resource – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.40 1.68 1.64 1.97
1.38 1.71 1.62 2.01
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.33
0.39
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
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Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-200 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.90 1.14 1.06 1.34
0.89 1.17 1.04 1.38
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.28
0.33
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Table 2-201 • A3P600L Global Resource – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.48 1.76 1.74 2.07
1.47 1.80 1.72 2.11
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.33
0.39
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Revision 9
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ProASIC3L DC and Switching Characteristics
Table 2-202 • A3P1000L Global Resource – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.02 1.26 1.20 1.48
1.01 1.29 1.18 1.52
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.28
0.33
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Table 2-203 • A3P1000L Global Resource – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.61 1.89 1.89 2.22
1.60 1.92 1.88 2.26
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.33
0.39
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
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Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-204 • A3PE3000L Global Resource – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.53 1.75 1.79 2.06
1.51 1.77 1.78 2.08
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.26
0.30
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Table 2-205 • A3PE3000L Global Resource – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.52 1.94 1.78 2.28
1.49 1.96 1.76 2.30
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
ns
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.47
0.55
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Revision 9
2-125
ProASIC3L DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-206 • ProASIC3LP CCC/PLL Specification
CCC/PLL Operating at 1.2 V
Parameter
Min.
1.5
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL 4
0.75
250
270
32
100
1
MHz
ns
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global External 3 Global
Network FB Used Networks
Used
0.50%
1.00%
2.50%
Used
0.70%
1.20%
2.75%
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.75%
1.50%
3.75%
100 MHz to 250 MHz
Acquisition Time
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter
LockControl = 0
2
ns
ns
%
LockControl = 1
1
Output Duty Cycle
48.5
1.2
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
ns
ns
ns
0.025
3.1
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings.
2. T = 25°C, V = 1.2 V
J
CC
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-126
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-207 • ProASIC3LP CCC/PLL Specification
CCC/PLL Operating at 1.5 V
Parameter
Min.
1.5
Typ.
Max.
350
350
110
Units
MHz
MHz
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Serial Clock (SCLK) for Dynamic PLL 4
0.75
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
160
ps
ns
32
1.5
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.50%
1.00%
1.75%
2.50%
0.70%
1.20%
2.00
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
5.60%
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter
LockControl = 0
1.6
0.8
ns
ns
%
LockControl = 1
Output Duty Cycle
48.5
0.6
51.5
5.56
5.56
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
ns
ns
ns
0.025
2.2
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings.
2. T = 25°C, VCC = 1.5 V
J
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-40 • Peak-to-Peak Jitter Definition
Revision 9
2-127
ProASIC3L DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-41 • RAM Models
2-128
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
tBKS
tBKH
BLK_B
WEN_B
DO
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 2-42 • RAM Read for Pass-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
tBKS
tBKH
BLK_B
WEN_B
DO
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 2-43 • RAM Read for Pipelined Output
Revision 9
2-129
ProASIC3L DC and Switching Characteristics
tCYC
tCKH
tCKL
CLK
ADD
BLK_B
WEN_B
DI
tAS
tAH
A0
tBKS
A1
A2
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 2-44 • RAM Write, Output Retained (WMODE = 0)
tCYC
tCKH
tCKL
CLK
ADD
tAS tAH
A0
tBKS
A1
A2
tBKH
BLK_B
WEN_B
DI
tENS
tDS tDH
DI1
DI0
DI2
DO
Dn
DI0
DI1
(pass-through)
DO
DI0
Dn
DI1
(pipelined)
Figure 2-45 • RAM Write, Output as Write Data (WMODE = 1)
2-130
Revision 9
ProASIC3L Low Power Flash FPGAs
CLK1
ADD1
DI1
tAS tAH
A0
tDS tDH
A1
D2
A3
D3
D1
tCCKH
CLK2
WEN_B1
WEN_B2
tAS tAH
A0
A0
D0
A4
D4
ADD2
DI2
tCKQ1
DO2
Dn
Dn
D0
(pass-through)
tCKQ2
DO2
(pipelined)
D0
Figure 2-46 • Write Access after Write onto Same Address
Revision 9
2-131
ProASIC3L DC and Switching Characteristics
CLK1
ADD1
t
t
t
AS AH
A
A
A
3
0
2
t
DS DH
D
D
D
DI1
0
2
3
t
WRO
CLK2
WEN_B1
WEN_B2
ADD2
t
t
AS AH
A
A
A
4
0
1
t
CKQ1
DO2
D
D
D
D
n
0
1
(pass-through)
t
CKQ2
DO2
(pipelined)
D
n
0
Figure 2-47 • Read Access after Write onto Same Address
2-132
Revision 9
ProASIC3L Low Power Flash FPGAs
CLK1
tAS
tAH
A0
A1
A0
ADD1
WEN_B1
tCKQ1
tCKQ1
DO1
(pass-through)
D
D
D
1
n
0
tCKQ2
DO1
(pipelined)
D
D
0
n
tCCKH
CLK2
ADD2
tAS
tAH
A1
A0
D1
A3
D3
D2
DI2
WEN_B2
Figure 2-48 • Write Access after Read onto Same Address
tCYC
tCKH
tCKL
CLK
RESET_B
DO
tRSTBQ
Dm
Dn
Figure 2-49 • RAM Reset
Revision 9
2-133
ProASIC3L DC and Switching Characteristics
Timing Characteristics
Table 2-208 • RAM4K9 – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Unit
s
Parameter
tAS
Description
–1 Std.
Address setup time
0.25 0.30 ns
0.00 0.00 ns
0.15 0.17 ns
0.10 0.12 ns
0.24 0.28 ns
0.02 0.02 ns
0.19 0.22 ns
0.00 0.00 ns
1.82 2.14 ns
2.40 2.83 ns
0.91 1.07 ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
tDH
Input data (DI) hold time
tCKQ1
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
tCKQ2
tWRO
Address collision clk-to-clk delay for reliable read access after write on same TBD TBD ns
address
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same TBD TBD ns
address
tRSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
0.94 1.11 ns
0.94 1.11 ns
0.29 0.34 ns
1.53 1.80 ns
0.55 0.64 ns
5.10 5.87 ns
196 170 MHz
tREMRSTB RESET_B removal
tRECRSTB RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-134
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-209 • RAM4K9 – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Unit
Parameter
tAS
Description
–1 Std.
s
Address setup time
0.33 0.39 ns
0.00 0.00 ns
0.19 0.22 ns
0.13 0.15 ns
0.31 0.36 ns
0.02 0.03 ns
0.24 0.29 ns
0.00 0.00 ns
2.38 2.80 ns
3.14 3.69 ns
1.19 1.40 ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
tDH
tCKQ1
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
tCKQ2
tWRO
Address collision clk-to-clk delay for reliable read access after write on same TBD TBD ns
address
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same TBD TBD ns
address
tRSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
1.23 1.45 ns
1.23 1.45 ns
0.38 0.45 ns
2.00 2.35 ns
0.63 0.72 ns
5.75 6.61 ns
174 151 MHz
tREMRSTB RESET_B removal
tRECRSTB RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-135
ProASIC3L DC and Switching Characteristics
Table 2-210 • RAM512X18 – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Unit
s
Parameter
tAS
Description
–1 Std.
Address setup time
0.25 0.30 ns
0.00 0.00 ns
0.09 0.11 ns
0.06 0.07 ns
0.19 0.22 ns
0.00 0.00 ns
2.20 2.59 ns
0.91 1.07 ns
tAH
Address hold time
tENS
REN_B, WEN_B setup time
tENH
tDS
REN_B, WEN_B hold time
Input data (DI) setup time
tDH
Input data (DI) hold time
tCKQ1
tCKQ2
tWRO
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same TBD TBD ns
address
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same TBD TBD ns
address
tRSTBQ
RESET_B Low to data out Low on DO (flow through)
RESET_B Low to data out Low on DO (pipelined)
0.94 1.11 ns
0.94 1.11 ns
0.29 0.34 ns
1.53 1.80 ns
0.55 0.64 ns
5.10 5.87 ns
196 170 MHz
tREMRSTB RESET_B removal
tRECRSTB RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2-136
Revision 9
ProASIC3L Low Power Flash FPGAs
Table 2-211 • RAM512X18 – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Unit
Parameter
tAS
Description
–1 Std.
s
Address setup time
0.33 0.39 ns
0.00 0.00 ns
0.12 0.14 ns
0.08 0.09 ns
0.24 0.29 ns
0.00 0.00 ns
2.88 3.39 ns
1.19 1.40 ns
tAH
Address hold time
tENS
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
tWRO
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same TBD TBD ns
address
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same TBD TBD ns
address
tRSTBQ
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
1.23 1.45 ns
1.23 1.45 ns
0.38 0.45 ns
2.00 2.35 ns
0.63 0.72 ns
5.75 6.61 ns
174 151 MHz
tREMRSTB RESET_B removal
tRECRSTB RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Revision 9
2-137
ProASIC3L DC and Switching Characteristics
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-50 • FIFO Model
2-138
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
tRSTFG
EMPTY
AEMPTY
FULL
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
MATCH (A0)
(Address Counter)
Figure 2-51 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Revision 9
2-139
ProASIC3L DC and Switching Characteristics
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-54 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-55 • FIFO FULL Flag and AFULL Flag Deassertion
2-140
Revision 9
ProASIC3L Low Power Flash FPGAs
Timing Characteristics
Table 2-212 • FIFO – Applies to 1.5 V DC Core Voltage
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–1
Std. Units
REN_B, WEN_B Setup Time
1.40 1.65
0.02 0.02
0.40 0.47
0.00 0.00
0.19 0.22
0.00 0.00
2.40 2.83
0.91 1.07
1.75 2.06
1.66 1.96
6.31 7.42
1.73 2.03
6.25 7.35
0.94 1.11
0.94 1.11
0.29 0.34
1.53 1.80
0.55 0.64
5.10 5.87
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tENH
REN_B, WEN_B Hold Time
tBKS
BLK_B Setup Time
tBKH
BLK_B Hold Time
tDS
Input Data (DI) Setup Time
tDH
Input Data (DI) Hold Time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost Empty/Full Flag Valid
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
196 170 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
Revision 9
2-141
ProASIC3L DC and Switching Characteristics
Table 2-213 • FIFO – Applies to 1.2 V DC Core Voltage
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
REN_B, WEN_B Setup Time
–1
Std. Units
1.84 2.16
0.02 0.03
0.40 0.47
0.00 0.00
0.24 0.29
0.00 0.00
3.14 3.69
1.19 1.40
2.29 2.69
2.18 2.56
8.25 9.70
2.26 2.65
8.17 9.60
1.23 1.45
1.23 1.45
0.38 0.45
2.00 2.35
0.63 0.72
5.75 6.61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tENH
REN_B, WEN_B Hold Time
tBKS
BLK_B Setup Time
tBKH
BLK_B Hold Time
tDS
Input Data (DI) Setup Time
tDH
Input Data (DI) Hold Time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost Empty/Full Flag Valid
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
174 151 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
2-142
Revision 9
ProASIC3L Low Power Flash FPGAs
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
tCKQ2
D1
D0
Data
Figure 2-56 • Timing Diagram
Timing Characteristics
Table 2-214 • Embedded FlashROM Access Time – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
–1
0.54
0.00
16.55
15
Std.
0.64
0.00
19.46
15
Units
ns
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
Table 2-215 • Embedded FlashROM Access Time– Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tSU
Description
Address Setup Time
–1
0.71
0.00
21.64
15
Std.
0.83
0.00
25.44
15
Units
ns
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
Revision 9
2-143
ProASIC3L DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-18 for more details.
Timing Characteristics
Table 2-216 • JTAG 1532 – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
–1
Std.
0.67
1.33
0.67
1.33
6.67
26.67
21.00
0.00
0.27
TBD
Units
ns
0.57
1.13
0.57
1.13
5.67
22.67
24.00
0.00
0.23
TBD
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
Table 2-217 • JTAG 1532 – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDISU
Description
Test Data Input Setup Time
–1
Std.
0.88
1.76
0.88
1.76
7.06
29.41
17.00
0.53
0.00
TBD
Units
ns
0.75
1.50
0.75
1.50
6.00
25.00
20.00
0.45
0.00
TBD
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for
derating values.
2-144
Revision 9
ProASIC3L Low Power Flash FPGAs
3 – Package Pin Assignments
100-Pin VQFP
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 9
3-1
Package Pin Assignments
100-Pin VQFP
Pin Number A3P250L Function
100-Pin VQFP
100-Pin VQFP
Pin Number A3P250L Function
Pin Number A3P250L Function
1
GND
GAA2/IO118UDB3
IO118VDB3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41PDB1
VMV1
2
3
VCCIB2
GNDQ
4
GAB2/IO117UDB3
IO117VDB3
IO77RSB2
IO74RSB2
IO71RSB2
GDC2/IO63RSB2
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO29RSB0
5
6
GAC2/IO116UDB3
IO116VDB3
7
8
IO112PSB3
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
TCK
IO27RSB0
TDI
IO25RSB0
GFA0/IO108NPB3
VCCPLF
TMS
IO23RSB0
VMV2
IO21RSB0
GFA1/IO108PPB3
GFA2/IO107PSB3
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB3
TDO
IO15RSB0
GFC2/IO105PSB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO60USB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO52NDB1
GCB2/IO52PDB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
VCCIB1
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GNDQ
GEA2/IO97RSB2
FF/GEB2/IO96RSB2
GEC2/IO95RSB2
IO93RSB2
VMV0
IO92RSB2
IO91RSB2
GND
IO90RSB2
VCC
IO88RSB2
IO43NDB1
GBC2/IO43PDB1
GBB2/IO42PSB1
IO41NDB1
IO86RSB2
IO85RSB2
IO84RSB2
3-2
Revision 9
ProASIC3L Low Power Flash FPGAs
208-Pin PQFP
208
1
208-Pin PQFP
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 9
3-3
Package Pin Assignments
208-Pin PQFP
Pin Number A3PL250 Function
208-Pin PQFP
208-Pin PQFP
Pin Number A3PL250 Function
Pin Number A3PL250 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO104PDB3
IO104NDB3
IO103PSB3
VCCIB3
73
74
IO83RSB2
IO82RSB2
IO81RSB2
IO80RSB2
IO79RSB2
IO78RSB2
IO77RSB2
IO76RSB2
GND
2
GAA2/IO118UDB3
IO118VDB3
3
75
4
GAB2/IO117UDB3
IO117VDB3
76
5
GND
77
6
GAC2/IO116UDB3
IO116VDB3
IO101PDB3
IO101NDB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEB1/IO99PDB3
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
78
7
79
8
IO115UDB3
IO115VDB3
80
9
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO114UDB3
IO114VDB3
82
IO75RSB2
IO74RSB2
IO73RSB2
IO72RSB2
IO71RSB2
IO70RSB2
VCC
83
IO113PDB3
84
IO113NDB3
IO112PDB3
85
86
IO112NDB3
VCC
GNDQ
87
GND
88
GND
NC
89
VCCIB2
VCCIB3
NC
90
IO69RSB2
IO68RSB2
IO67RSB2
IO66RSB2
IO65RSB2
IO64RSB2
GDC2/IO63RSB2
GND
IO111PDB3
GEA2/IO97RSB2
FF/GEB2/IO96RSB2
GEC2/IO95RSB2
IO94RSB2
IO93RSB2
IO92RSB2
IO91RSB2
VCCIB2
91
IO111NDB3
92
GFC1/IO110PDB3
GFC0/IO110NDB3
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
93
94
95
96
97
GFA0/IO108NPB3
VCCPLF
98
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
IO90RSB2
IO89RSB2
GND
99
GFA1/IO108PPB3
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO107PDB3
IO107NDB3
GFB2/IO106PDB3
IO106NDB3
GFC2/IO105PDB3
IO105NDB3
NC
IO88RSB2
IO87RSB2
IO86RSB2
IO85RSB2
IO84RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
NC
VCCIB2
TDO
3-4
Revision 9
ProASIC3L Low Power Flash FPGAs
208-Pin PQFP
208-Pin PQFP
208-Pin PQFP
Pin Number A3PL250 Function
Pin Number A3PL250 Function
Pin Number A3PL250 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO45PDB1
IO44NDB1
IO44PDB1
IO43NDB1
GBC2/IO43PDB1
IO42NDB1
GBB2/IO42PDB1
IO41NDB1
GBA2/IO41PDB1
VMV1
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
VCCIB0
GDA0/IO60VDB1
GDA1/IO60UDB1
GDB0/IO59VDB1
GDB1/IO59UDB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO57VDB1
VCC
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
IO10RSB0
GND
IO57UDB1
IO56NDB1
GNDQ
IO56PDB1
GND
IO55RSB1
NC
GND
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GND
VCCIB1
NC
IO09RSB0
IO08RSB0
IO07RSB0
IO06RSB0
VCCIB0
NC
VCC
IO53NDB1
GBC1/IO36RSB0
GBC0/IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
IO30RSB0
VCCIB0
GCC2/IO53PDB1
GCB2/IO52PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO51PSB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCB0/IO49NDB1
GCB1/IO49PDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
IO47NDB1
VCC
IO29RSB0
IO28RSB0
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
GND
VMV0
IO47PDB1
VCCIB1
GND
VCC
IO46RSB1
IO23RSB0
IO22RSB0
IO45NDB1
Revision 9
3-5
Package Pin Assignments
208-Pin PQFP
Pin Number A3PL600 Function
208-Pin PQFP
208-Pin PQFP
Pin Number A3PL600 Function
Pin Number A3PL600 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
IO152PDB3
IO152NDB3
IO150PSB3
VCCIB3
72
73
VCCIB2
IO120RSB2
IO119RSB2
IO118RSB2
IO117RSB2
IO116RSB2
IO115RSB2
IO114RSB2
IO112RSB2
GND
2
GAA2/IO174PDB3
IO174NDB3
GAB2/IO173PDB3
IO173NDB3
GAC2/IO172PDB3
IO172NDB3
IO171PDB3
IO171NDB3
IO170PDB3
3
74
4
75
5
GND
76
6
IO147PDB3
IO147NDB3
GEC1/IO146PDB3
GEC0/IO146NDB3
GEB1/IO145PDB3
GEB0/IO145NDB3
GEA1/IO144PDB3
GEA0/IO144NDB3
VMV3
77
7
78
8
79
9
80
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
81
IO170NDB3
IO169PDB3
82
IO111RSB2
IO110RSB2
IO109RSB2
IO108RSB2
IO107RSB2
IO106RSB2
VCC
83
IO169NDB3
IO168PDB3
84
85
IO168NDB3
VCC
GNDQ
86
GND
87
GND
VMV2
88
VCCIB3
GEA2/IO143RSB2
89
VCCIB2
IO166PDB3
FF/GEB2/IO142RSB
2
90
IO104RSB2
IO102RSB2
IO100RSB2
IO98RSB2
IO96RSB2
IO92RSB2
GDC2/IO91RSB2
GND
IO166NDB3
GFC1/IO164PDB3
GFC0/IO164NDB3
GFB1/IO163PDB3
GFB0/IO163NDB3
VCOMPLF
91
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
GEC2/IO141RSB2
IO140RSB2
IO139RSB2
IO138RSB2
IO137RSB2
IO136RSB2
VCCIB2
92
93
94
95
96
GFA0/IO162NPB3
VCCPLF
97
98
GDB2/IO90RSB2
GDA2/IO89RSB2
GNDQ
IO135RSB2
IO133RSB2
GND
GFA1/IO162PPB3
GND
99
100
101
102
103
104
105
106
107
GFA2/IO161PDB3
IO161NDB3
GFB2/IO160PDB3
IO160NDB3
GFC2/IO159PDB3
IO159NDB3
VCC
TCK
IO131RSB2
IO129RSB2
IO127RSB2
IO125RSB2
IO123RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
GNDQ
3-6
Revision 9
ProASIC3L Low Power Flash FPGAs
208-Pin PQFP
208-Pin PQFP
208-Pin PQFP
Pin Number A3PL600 Function
Pin Number A3PL600 Function
Pin Number A3PL600 Function
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
TDO
TRST
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
IO64NDB1
IO64PDB1
IO63NDB1
IO63PDB1
IO62NDB1
GBC2/IO62PDB1
IO61NDB1
GBB2/IO61PDB1
IO60NDB1
GBA2/IO60PDB1
VMV1
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO28RSB0
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
VCCIB0
VJTAG
GDA0/IO88NDB1
GDA1/IO88PDB1
GDB0/IO87NDB1
GDB1/IO87PDB1
GDC0/IO86NDB1
GDC1/IO86PDB1
IO84NDB1
VCC
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO14RSB0
IO12RSB0
GND
IO84PDB1
IO82NDB1
GNDQ
IO82PDB1
GND
IO81PSB1
VMV0
GND
GBA1/IO59RSB0
GBA0/IO58RSB0
GBB1/IO57RSB0
GBB0/IO56RSB0
GND
VCCIB1
IO77NDB1
IO10RSB0
IO09RSB0
IO08RSB0
IO07RSB0
VCCIB0
IO77PDB1
NC
IO74NDB1
GBC1/IO55RSB0
GBC0/IO54RSB0
IO52RSB0
IO50RSB0
IO48RSB0
IO46RSB0
IO44RSB0
VCCIB0
GCC2/IO74PDB1
GCB2/IO73PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO72PSB1
GCA1/IO71PDB1
GCA0/IO71NDB1
GCB0/IO70NDB1
GCB1/IO70PDB1
GCC0/IO69NDB1
GCC1/IO69PDB1
IO67NDB1
VCC
IO36RSB0
IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
GND
VMV0
IO67PDB1
VCCIB1
GND
VCC
IO65PSB1
IO29RSB0
Revision 9
3-7
Package Pin Assignments
208-Pin PQFP
Pin Number APL1000 Function
208-Pin PQFP
208-Pin PQFP
Pin Number APL1000 Function
Pin Number APL1000 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
IO199PDB3
IO199NDB3
IO197PSB3
VCCIB3
72
73
VCCIB2
IO162RSB2
IO160RSB2
IO158RSB2
IO156RSB2
IO154RSB2
IO152RSB2
IO150RSB2
IO148RSB2
GND
2
GAA2/IO225PDB3
IO225NDB3
GAB2/IO224PDB3
IO224NDB3
GAC2/IO223PDB3
IO223NDB3
IO222PDB3
IO222NDB3
IO220PDB3
3
74
4
75
5
GND
76
6
IO191PDB3
IO191NDB3
GEC1/IO190PDB3
GEC0/IO190NDB3
GEB1/IO189PDB3
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
VMV3
77
7
78
8
79
9
80
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
81
IO220NDB3
IO218PDB3
82
IO143RSB2
IO141RSB2
IO139RSB2
IO137RSB2
IO135RSB2
IO133RSB2
VCC
83
IO218NDB3
IO216PDB3
84
85
IO216NDB3
VCC
GNDQ
86
GND
87
GND
VMV2
88
VCCIB3
GEA2/IO187RSB2
89
VCCIB2
IO212PDB3
FF/GEB2/IO186RSB
2
90
IO128RSB2
IO126RSB2
IO124RSB2
IO122RSB2
IO120RSB2
IO118RSB2
GDC2/IO116RSB2
GND
IO212NDB3
GFC1/IO209PDB3
GFC0/IO209NDB3
GFB1/IO208PDB3
GFB0/IO208NDB3
VCOMPLF
91
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
GEC2/IO185RSB2
IO184RSB2
IO183RSB2
IO182RSB2
IO181RSB2
IO180RSB2
VCCIB2
92
93
94
95
96
GFA0/IO207NPB3
VCCPLF
97
98
GDB2/IO115RSB2
GDA2/IO114RSB2
GNDQ
IO178RSB2
IO176RSB2
GND
GFA1/IO207PPB3
GND
99
100
101
102
103
104
105
106
107
GFA2/IO206PDB3
IO206NDB3
GFB2/IO205PDB3
IO205NDB3
GFC2/IO204PDB3
IO204NDB3
VCC
TCK
IO174RSB2
IO172RSB2
IO170RSB2
IO168RSB2
IO166RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
GNDQ
3-8
Revision 9
ProASIC3L Low Power Flash FPGAs
208-Pin PQFP
208-Pin PQFP
208-Pin PQFP
Pin Number APL1000 Function
Pin Number APL1000 Function
Pin Number APL1000 Function
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
TDO
TRST
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
IO84NDB1
IO84PDB1
IO82NDB1
IO82PDB1
IO80NDB1
GBC2/IO80PDB1
IO79NDB1
GBB2/IO79PDB1
IO78NDB1
GBA2/IO78PDB1
VMV1
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO35RSB0
IO33RSB0
IO31RSB0
IO29RSB0
IO27RSB0
IO25RSB0
VCCIB0
VJTAG
GDA0/IO113NDB1
GDA1/IO113PDB1
GDB0/IO112NDB1
GDB1/IO112PDB1
GDC0/IO111NDB1
GDC1/IO111PDB1
IO109NDB1
IO109PDB1
IO106NDB1
IO106PDB1
IO104PSB1
GND
VCC
IO22RSB0
IO20RSB0
IO18RSB0
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
GND
GNDQ
GND
VMV0
GBA1/IO77RSB0
GBA0/IO76RSB0
GBB1/IO75RSB0
GBB0/IO74RSB0
GND
VCCIB1
IO99NDB1
IO12RSB0
IO11RSB0
IO10RSB0
IO09RSB0
VCCIB0
IO99PDB1
NC
IO96NDB1
GBC1/IO73RSB0
GBC0/IO72RSB0
IO70RSB0
IO67RSB0
IO63RSB0
IO60RSB0
IO57RSB0
VCCIB0
GCC2/IO96PDB1
GCB2/IO95PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO94PSB1
GCA1/IO93PDB1
GCA0/IO93NDB1
GCB0/IO92NDB1
GCB1/IO92PDB1
GCC0/IO91NDB1
GCC1/IO91PDB1
IO88NDB1
VCC
IO54RSB0
IO51RSB0
IO48RSB0
IO45RSB0
IO42RSB0
IO40RSB0
GND
VMV0
IO88PDB1
VCCIB1
GND
VCC
IO86PSB1
IO38RSB0
Revision 9
3-9
Package Pin Assignments
208-Pin PQFP
208-Pin PQFP
A3PE3000L
208-Pin PQFP
A3PE3000L
Pin
Number
A3PE3000L
Function
Pin
Number
Pin
Number
Function
Function
IO208PDB5V1
VCC
1
GND
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
VCC
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
2
GNDQ
IO252PDB6V2
IO252NDB6V2
IO248PSB6V1
VCCIB6
3
VMV7
VCCIB5
4
GAB2/IO308PSB7V4
GAA2/IO309PDB7V4
IO309NDB7V4
GAC2/IO307PDB7V4
IO307NDB7V4
IO303PDB7V3
IO303NDB7V3
IO299PDB7V3
IO299NDB7V3
IO295PDB7V2
IO295NDB7V2
IO291PSB7V2
VCC
IO202NDB5V1
IO202PDB5V1
IO198NDB5V0
IO198PDB5V0
IO197NDB5V0
IO197PDB5V0
IO194NDB5V0
IO194PDB5V0
GND
5
6
GND
7
IO244PDB6V1
IO244NDB6V1
GEC1/IO236PDB6V0
GEC0/IO236NDB6V0
GEB1/IO235PPB6V0
GEA1/IO234PPB6V0
GEB0/IO235NPB6V0
GEA0/IO234NPB6V0
VMV6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO184NDB4V3
IO184PDB4V3
IO180NDB4V3
IO180PDB4V3
IO176NDB4V2
IO176PDB4V2
VCC
GNDQ
GND
GND
VCCIB7
VMV5
IO285PDB7V1
IO285NDB7V1
IO279PSB7V0
GFC1/IO275PSB7V0
GFB1/IO274PDB7V0
GFB0/IO274NDB7V0
VCOMPLF
GNDQ
IO233NDB5V4
GEA2/IO233PDB5V4
IO232NDB5V4
VCCIB4
IO170NDB4V2
IO170PDB4V2
IO166NDB4V1
IO166PDB4V1
IO156NDB4V0
GDC2/IO156PDB4V0
IO154NPB4V0
GND
FF/GEB2/IO232PDB5
V4
59
60
61
62
62
63
64
65
66
67
68
69
IO231NDB5V4
GEC2/IO231PDB5V4
IO230PSB5V4
VCCIB5
GFA0/IO273NPB6V4
VCCPLF
GFA1/IO273PPB6V4
GND
VCCIB5
GDB2/IO155PSB4V0
GDA2/IO154PPB4V0
GNDQ
IO218NDB5V3
IO218PDB5V3
GND
GFA2/IO272PDB6V4
IO272NDB6V4
GFB2/IO271PPB6V4
GFC2/IO270PPB6V4
IO271NPB6V4
IO270NPB6V4
VCC
TCK
IO214PSB5V2
IO212NDB5V2
IO212PDB5V2
IO208NDB5V1
TDI
TMS
VMV4
GND
3-10
Revision 9
ProASIC3L Low Power Flash FPGAs
208-Pin PQFP
A3PE3000L
208-Pin PQFP
A3PE3000L
208-Pin PQFP
Pin
Number
Pin
Number
Pin
Number
A3PE3000L
Function
Function
Function
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
VPUMP
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
171
172
173
174
175
176
VCC
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO40PDB0V4
GND
GNDQ
IO99NDB2V2
IO99PDB2V2
IO96NDB2V1
IO96PDB2V1
IO91NDB2V1
IO91PDB2V1
IO88NDB2V0
IO88PDB2V0
GBC2/IO84PSB2V0
GBA2/IO82PSB2V0
GBB2/IO83PSB2V0
VMV2
TDO
IO40NDB0V4
IO37PDB0V4
IO37NDB0V4
IO35PDB0V4
IO35NDB0V4
IO32PDB0V3
IO32NDB0V3
VCCIB0
TRST
VJTAG
VMV3
GDA0/IO153NPB3V4
GDB0/IO152NPB3V4
GDA1/IO153PPB3V4
GDB1/IO152PPB3V4
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
IO134NDB3V2
IO134PDB3V2
IO132NDB3V2
IO132PDB3V2
GND
VCC
IO28PDB0V3
IO28NDB0V3
IO24PDB0V2
IO24NDB0V2
IO21PSB0V2
IO16PDB0V1
IO16NDB0V1
GND
GNDQ
GND
VMV1
GNDQ
VCCIB3
GBA1/IO81PDB1V4
GBA0/IO81NDB1V4
GBB1/IO80PDB1V4
GND
GCC2/IO117PSB3V0
GCB2/IO116PSB3V0
NC
IO11PDB0V1
IO11NDB0V1
IO08PDB0V0
IO08NDB0V0
VCCIB0
IO115NDB3V0
GCA2/IO115PDB3V0
GCA1/IO114PPB3V0
GND
GBB0/IO80NDB1V4
GBC1/IO79PDB1V4
GBC0/IO79NDB1V4
IO74PDB1V4
IO74NDB1V4
IO70PDB1V3
IO70NDB1V3
VCCIB1
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
VCCPLC
GCA0/IO114NPB3V0
VCOMPLC
GCB0/IO113NDB2V3
GCB1/IO113PDB2V3
GCC1/IO112PSB2V3
IO110NDB2V3
IO110PDB2V3
IO106PSB2V3
VCCIB2
VCC
VCC
IO56PSB1V1
IO55PDB1V1
IO55NDB1V1
IO54PDB1V1
IO54NDB1V1
VMV0
GND
Revision 9
3-11
Package Pin Assignments
144-Pin FBGA
A1 Ball Pad Corner
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
3-12
Revision 9
ProASIC3L Low Power Flash FPGAs
144-Pin FBGA
144-Pin FBGA
144-Pin FBGA
Pin Number A3P250L Function
Pin Number A3P250L Function
Pin Number A3P250L Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO112NDB3
IO112PDB3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO108PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
IO116VDB3
VCCPLF
A4
GAA2/IO118UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO42PDB1
IO42NDB1
GFA0/IO108NPB3
GND
A5
A6
GND
GND
A7
IO29RSB0
GND
A8
VCC
GDC1/IO58UPB1
IO53NDB1
GCC2/IO53PDB1
IO52NDB1
GCB2/IO52PDB1
VCC
A9
IO33RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
IO43NPB1
GCB1/IO49PPB1
VCC
GAB2/IO117UDB3
GND
B2
E2
GFC0/IO110NDB3
GFC1/IO110PDB3
VCCIB3
GFB2/IO106PDB3
GFC2/IO105PSB3
GEC1/IO100PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO118VPB3
B6
IO19RSB0
E6
VCCIB0
IO79RSB2
B7
IO22RSB0
E7
VCCIB0
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
VCCIB1
GDB2/IO62RSB2
GDC0/IO58VPB1
VCCIB1
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO50NDB1
IO51NDB1
IO54PSB1
VMV1
VCC
IO117VDB3
GFA2/IO107PPB3
GAC2/IO116UDB3
VCC
GFB0/IO109NPB3
VCOMPLF
GEB1/IO99PDB3
IO106NDB3
VCCIB3
F2
J2
F3
GFB1/IO109PPB3
IO107NPB3
GND
J3
F4
J4
GEC0/IO100NDB3
IO88RSB2
IO12RSB0
F5
J5
IO17RSB0
F6
GND
J6
IO81RSB2
IO24RSB0
F7
GND
J7
VCC
IO31RSB0
F8
GCC0/IO48NDB1
GCB0/IO49NPB1
GND
J8
TCK
IO34RSB0
F9
J9
GDA2/IO61RSB2
TDO
GBA2/IO41PDB1
IO41NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO50PDB1
GCA2/IO51PDB1
GDA1/IO60UDB1
GDB1/IO59UDB1
GBC2/IO43PPB1
Revision 9
3-13
Package Pin Assignments
144-Pin FBGA
Pin Number A3P250L Function
K1
K2
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
GEA2/IO97RSB2
IO90RSB2
IO84RSB2
GND
K3
K4
K5
K6
K7
K8
IO66RSB2
GDC2/IO63RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO60VDB1
GDB0/IO59VDB1
GND
L2
VMV3
L3
FF/GEB2/IO96RSB2
IO91RSB2
VCCIB2
L4
L5
L6
IO82RSB2
IO80RSB2
IO72RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO95RSB2
IO92RSB2
IO89RSB2
IO87RSB2
IO85RSB2
IO78RSB2
IO76RSB2
TDI
VCCIB2
VPUMP
GNDQ
3-14
Revision 9
ProASIC3L Low Power Flash FPGAs
144-Pin FBGA
144-Pin FBGA
144-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
Pin Number A3P600L Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO169PDB3
IO169NDB3
IO172NDB3
GAA2/IO174PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO54RSB0
GBC1/IO55RSB0
GBB2/IO61PDB1
IO61NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO162PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO162NPB3
GND
A5
A6
GND
GND
A7
IO34RSB0
GND
A8
VCC
GDC1/IO86PPB1
IO74NDB1
A9
IO50RSB0
A10
A11
A12
B1
GBA0/IO58RSB0
GBA1/IO59RSB0
GNDQ
GCC2/IO74PDB1
IO73NDB1
IO62NPB1
GCB1/IO70PPB1
VCC
GCB2/IO73PDB1
VCC
GAB2/IO173PDB3
GND
B2
E2
GFC0/IO164NDB3
GFC1/IO164PDB3
VCCIB3
GFB2/IO160PDB3
GFC2/IO159PSB3
GEC1/IO146PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO174NPB3
VCCIB0
B6
IO19RSB0
E6
IO80PDB1
B7
IO31RSB0
E7
VCCIB0
IO80NDB1
B8
IO39RSB0
E8
GCC1/IO69PDB1
VCCIB1
GDB2/IO90RSB2
GDC0/IO86NPB1
VCCIB1
B9
GBB0/IO56RSB0
GBB1/IO57RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO71NDB1
IO72NDB1
IO84PSB1
VMV1
VCC
IO173NDB3
GFA2/IO161PPB3
GAC2/IO172PDB3
VCC
GFB0/IO163NPB3
VCOMPLF
GEB1/IO145PDB3
IO160NDB3
VCCIB3
F2
J2
F3
GFB1/IO163PPB3
IO161NPB3
GND
J3
F4
J4
GEC0/IO146NDB3
IO129RSB2
IO131RSB2
VCC
IO16RSB0
F5
J5
IO25RSB0
F6
GND
J6
IO28RSB0
F7
GND
J7
IO42RSB0
F8
GCC0/IO69NDB1
GCB0/IO70NPB1
GND
J8
TCK
IO45RSB0
F9
J9
GDA2/IO89RSB2
TDO
GBA2/IO60PDB1
IO60NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO71PDB1
GCA2/IO72PDB1
GDA1/IO88PDB1
GDB1/IO87PDB1
GBC2/IO62PPB1
Revision 9
3-15
Package Pin Assignments
144-Pin FBGA
Pin Number A3P600L Function
144-Pin FBGA
Pin Number A3P600L Function
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
GEB0/IO145NDB3
GEA1/IO144PDB3
GEA0/IO144NDB3
GEA2/IO143RSB2
IO119RSB2
M11
M12
VPUMP
GNDQ
IO111RSB2
GND
IO94RSB2
GDC2/IO91RSB2
GND
GDA0/IO88NDB1
GDB0/IO87NDB1
GND
L2
VMV3
L3
FF/GEB2/IO142RSB
2
L4
L5
IO136RSB2
VCCIB2
L6
IO115RSB2
IO103RSB2
IO97RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
VJTAG
VMV2
TRST
GNDQ
GEC2/IO141RSB2
IO138RSB2
IO123RSB2
IO126RSB2
IO134RSB2
IO108RSB2
IO99RSB2
TDI
VCCIB2
3-16
Revision 9
ProASIC3L Low Power Flash FPGAs
144-Pin FBGA
144-Pin FBGA
144-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
Pin Number A3P1000L Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO213PDB3
IO213NDB3
IO223NDB3
GAA2/IO225PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO72RSB0
GBC1/IO73RSB0
GBB2/IO79PDB1
IO79NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO207PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO207NPB3
GND
A5
A6
GND
GND
A7
IO44RSB0
GND
A8
VCC
GDC1/IO111PPB1
IO96NDB1
A9
IO69RSB0
A10
A11
A12
B1
GBA0/IO76RSB0
GBA1/IO77RSB0
GNDQ
GCC2/IO96PDB1
IO95NDB1
IO80NPB1
GCB1/IO92PPB1
VCC
GCB2/IO95PDB1
VCC
GAB2/IO224PDB3
GND
B2
E2
GFC0/IO209NDB3
GFC1/IO209PDB3
VCCIB3
GFB2/IO205PDB3
GFC2/IO204PSB3
GEC1/IO190PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO225NPB3
VCCIB0
B6
IO26RSB0
E6
IO105PDB1
IO105NDB1
GDB2/IO115RSB2
GDC0/IO111NPB1
VCCIB1
B7
IO35RSB0
E7
VCCIB0
B8
IO60RSB0
E8
GCC1/IO91PDB1
VCCIB1
B9
GBB0/IO74RSB0
GBB1/IO75RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO93NDB1
IO94NDB1
IO101PSB1
VCC
VMV1
IO224NDB3
GFA2/IO206PPB3
GAC2/IO223PDB3
VCC
GFB0/IO208NPB3
VCOMPLF
GEB1/IO189PDB3
IO205NDB3
VCCIB3
F2
J2
F3
GFB1/IO208PPB3
IO206NPB3
GND
J3
F4
J4
GEC0/IO190NDB3
IO160RSB2
IO157RSB2
VCC
IO16RSB0
F5
J5
IO29RSB0
F6
GND
J6
IO32RSB0
F7
GND
J7
IO63RSB0
F8
GCC0/IO91NDB1
GCB0/IO92NPB1
GND
J8
TCK
IO66RSB0
F9
J9
GDA2/IO114RSB2
TDO
GBA2/IO78PDB1
IO78NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO93PDB1
GCA2/IO94PDB1
GDA1/IO113PDB1
GDB1/IO112PDB1
GBC2/IO80PPB1
Revision 9
3-17
Package Pin Assignments
144-Pin FBGA
Pin Number A3P1000L Function
144-Pin FBGA
Pin Number A3P1000L Function
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
GEA2/IO187RSB2
IO169RSB2
M11
M12
VPUMP
GNDQ
IO152RSB2
GND
IO117RSB2
GDC2/IO116RSB2
GND
GDA0/IO113NDB1
GDB0/IO112NDB1
GND
L2
VMV3
L3
FF/GEB2/IO186RSB
2
L4
L5
IO172RSB2
VCCIB2
L6
IO153RSB2
IO144RSB2
IO140RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
VJTAG
VMV2
TRST
GNDQ
GEC2/IO185RSB2
IO173RSB2
IO168RSB2
IO161RSB2
IO156RSB2
IO145RSB2
IO141RSB2
TDI
VCCIB2
3-18
Revision 9
ProASIC3L Low Power Flash FPGAs
256-Pin FBGA
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 9
3-19
Package Pin Assignments
256-Pin FBGA
Pin Number A3P250L Function
256-Pin FBGA
256-Pin FBGA
Pin Number A3P250L Function
Pin Number A3P250L Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO07RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO13RSB0
IO17RSB0
IO22RSB0
IO27RSB0
IO31RSB0
GBC0/IO35RSB0
IO34RSB0
NC
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO24RSB0
VCCIB0
VCCIB0
VMV1
A3
C7
A4
C8
A5
C9
GBC2/IO43PDB1
IO46RSB1
NC
A6
IO10RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO11RSB0
A8
IO15RSB0
IO45PDB1
IO113NDB3
IO112PPB3
NC
A9
IO20RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO25RSB0
F2
IO29RSB0
IO42NPB1
IO44PDB1
IO114VDB3
IO114UDB3
GAC2/IO116UDB3
NC
F3
IO33RSB0
F4
IO115VDB3
VCCIB3
GND
GBB1/IO38RSB0
GBA0/IO39RSB0
GBA1/IO40RSB0
GND
F5
D2
F6
D3
F7
VCC
D4
F8
VCC
GAB2/IO117UDB3
GAA2/IO118UDB3
NC
D5
GNDQ
F9
VCC
B2
D6
IO08RSB0
IO14RSB0
IO18RSB0
IO23RSB0
IO28RSB0
IO32RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO06RSB0
D8
VCCIB1
IO43NDB1
NC
B5
D9
B6
IO09RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO12RSB0
IO47PPB1
IO45NDB1
IO111NDB3
IO111PDB3
IO112NPB3
GFC1/IO110PPB3
VCCIB3
VCC
B8
IO16RSB0
B9
IO21RSB0
NC
B10
B11
B12
B13
B14
B15
B16
C1
IO26RSB0
GBB2/IO42PPB1
NC
G2
IO30RSB0
G3
GBC1/IO36RSB0
GBB0/IO37RSB0
NC
IO44NDB1
IO113PDB3
NC
G4
G5
E2
G6
GBA2/IO41PDB1
IO41NDB1
E3
IO116VDB3
IO115UDB3
VMV0
G7
GND
E4
G8
GND
IO117VDB3
IO118VDB3
NC
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
NC
E8
IO19RSB0
VCCIB1
3-20
Revision 9
ProASIC3L Low Power Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number A3P250L Function
Pin Number A3P250L Function
Pin Number A3P250L Function
G13
G14
G15
G16
H1
GCC1/IO48PPB1
IO47NPB1
IO54PDB1
IO54NDB1
GFB0/IO109NPB3
GFA0/IO108NDB3
GFB1/IO109PPB3
VCOMPLF
GFC0/IO110NPB3
VCC
K1
K2
GFC2/IO105PDB3
IO107NPB3
IO104PPB3
NC
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
K3
VCCIB2
K4
NC
K5
VCCIB3
VCC
IO74RSB2
VCCIB2
H2
K6
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
K9
GND
NC
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO59UPB1
GDC1/IO58UDB1
IO56NDB1
IO103NDB3
IO101PPB3
GEC1/IO100PPB3
NC
H7
GND
VCC
H8
GND
VCCIB1
IO52NPB1
IO55RSB1
IO53NPB1
IO51NDB1
IO105NDB3
IO104NPB3
NC
H9
GND
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO48NPB1
GCB1/IO49PPB1
GCA0/IO50NPB1
NC
N4
N5
GNDQ
L2
N6
GEA2/IO97RSB2
IO86RSB2
IO82RSB2
IO75RSB2
IO69RSB2
IO64RSB2
GNDQ
L3
N7
GCB0/IO49NPB1
GFA2/IO107PPB3
GFA1/IO108PDB3
VCCPLF
L4
IO102RSB3
VCCIB3
GND
N8
L5
N9
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO106NDB3
GFB2/IO106PDB3
VCC
L8
VCC
J5
L9
VCC
NC
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO58VDB1
GDA1/IO60UDB1
GEB1/IO99PDB3
GEB0/IO99NDB3
NC
J8
GND
VCCIB1
GDB0/IO59VPB1
IO57VDB1
IO57UDB1
IO56PDB1
IO103PDB3
NC
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO52PPB1
GCA1/IO50PPB1
GCC2/IO53PPB1
NC
P4
NC
P5
IO92RSB2
IO89RSB2
IO85RSB2
IO81RSB2
P6
IO101NPB3
GEC0/IO100NPB3
P7
GCA2/IO51PDB1
P8
Revision 9
3-21
Package Pin Assignments
256-Pin FBGA
Pin Number A3P250L Function
256-Pin FBGA
Pin Number A3P250L Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO76RSB2
IO71RSB2
IO66RSB2
NC
T13
T14
T15
T16
IO67RSB2
GDA2/IO61RSB2
TMS
GND
TCK
VPUMP
TRST
GDA0/IO60VDB1
GEA1/IO98PDB3
GEA0/IO98NDB3
NC
R2
R3
R4
GEC2/IO95RSB2
IO91RSB2
IO88RSB2
IO84RSB2
IO80RSB2
IO77RSB2
IO72RSB2
IO68RSB2
IO65RSB2
GDB2/IO62RSB2
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
NC
TDO
GND
T2
IO94RSB2
FF/GEB2/IO96RSB2
IO93RSB2
IO90RSB2
IO87RSB2
IO83RSB2
IO79RSB2
IO78RSB2
IO73RSB2
IO70RSB2
GDC2/IO63RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
3-22
Revision 9
ProASIC3L Low Power Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
Pin Number A3P600L Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO11RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO31RSB0
VCCIB0
A3
C7
VCCIB0
A4
C8
VMV1
A5
C9
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
IO66PDB1
IO166NDB3
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
A6
IO16RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO18RSB0
A8
IO28RSB0
A9
IO34RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO37RSB0
F2
IO41RSB0
IO61NPB1
IO63PDB1
IO171NDB3
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
F3
IO43RSB0
F4
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
D5
F9
VCC
B2
D6
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO45RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO13RSB0
D8
VCCIB1
B5
D9
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
B6
IO14RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO21RSB0
B8
IO27RSB0
B9
IO32RSB0
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
B10
B11
B12
B13
B14
B15
B16
C1
IO38RSB0
G2
IO42RSB0
G3
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
G4
G5
E2
G6
VCC
GBA2/IO60PDB1
IO60NDB1
E3
G7
GND
E4
G8
GND
IO173NDB3
IO174NDB3
VMV3
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
IO07RSB0
E8
IO25RSB0
VCCIB1
Revision 9
3-23
Package Pin Assignments
256-Pin FBGA
Pin Number A3P600L Function
256-Pin FBGA
256-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
G13
G14
G15
G16
H1
GCC1/IO69PPB1
IO65NPB1
K1
K2
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
IO75PDB1
K3
VCCIB2
IO75NDB1
K4
IO117RSB2
IO110RSB2
VCCIB2
GFB0/IO163NPB3
GFA0/IO162NDB3
GFB1/IO163PPB3
VCOMPLF
K5
H2
K6
VCC
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
GFC0/IO164NPB3
VCC
K9
GND
IO94RSB2
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO87PPB1
GDC1/IO86PDB1
IO84NDB1
H7
GND
VCC
H8
GND
VCCIB1
H9
GND
IO73NPB1
IO80NPB1
IO74NPB1
IO72NDB1
IO159NDB3
IO156NPB3
IO151PPB3
IO158PSB3
VCCIB3
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
N4
N5
L2
N6
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
L3
N7
GCB0/IO70NPB1
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO160NDB3
GFB2/IO160PDB3
VCC
L8
VCC
GNDQ
J5
L9
VCC
IO92RSB2
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO86NDB1
GDA1/IO88PDB1
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
J8
GND
VCCIB1
J9
GND
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
P4
IO138RSB2
IO136RSB2
IO131RSB2
IO124RSB2
IO119RSB2
P5
P6
P7
GCA2/IO72PDB1
P8
3-24
Revision 9
ProASIC3L Low Power Flash FPGAs
256-Pin FBGA
256-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO107RSB2
IO104RSB2
IO97RSB2
VMV1
T12
T13
T14
T15
T16
GDC2/IO91RSB2
IO93RSB2
GDA2/IO89RSB2
TMS
TCK
GND
VPUMP
TRST
GDA0/IO88NDB1
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO96RSB2
GDB2/IO90RSB2
TDI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO137RSB2
T3
FF/GEB2/IO142RSB
2
T4
T5
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
T6
T7
T8
T9
T10
T11
Revision 9
3-25
Package Pin Assignments
256-Pin FBGA
Pin Number A3P1000L Function
256-Pin FBGA
256-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO47RSB0
VCCIB0
A3
C7
VCCIB0
A4
C8
VMV1
A5
C9
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
A6
IO22RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO28RSB0
A8
IO35RSB0
A9
IO45RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO50RSB0
F2
IO55RSB0
IO78NDB1
IO81NDB1
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
F3
IO61RSB0
F4
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
D5
F9
VCC
B2
D6
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO17RSB0
D8
VCCIB1
B5
D9
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
IO210PSB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
B6
IO21RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO27RSB0
B8
IO34RSB0
B9
IO44RSB0
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NSB1
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
B10
B11
B12
B13
B14
B15
B16
C1
IO51RSB0
G2
IO57RSB0
G3
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
G4
G5
E2
G6
VCC
GBA2/IO78PDB1
IO81PDB1
E3
G7
GND
E4
G8
GND
IO224NDB3
IO225NDB3
VMV3
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
IO11RSB0
E8
IO38RSB0
VCCIB1
3-26
Revision 9
ProASIC3L Low Power Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
Pin Number A3P1000L Function
G13
G14
G15
G16
H1
GCC1/IO91PPB1
IO90NPB1
K1
K2
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
IO88PDB1
K3
VCCIB2
IO88NDB1
K4
IO147RSB2
IO136RSB2
VCCIB2
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
K5
H2
K6
VCC
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
GFC0/IO209NPB3
VCC
K9
GND
IO110NDB1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
IO194PSB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
GND
VCC
H8
GND
VCCIB1
H9
GND
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
N4
N5
L2
N6
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
L3
N7
GCB0/IO92NPB1
GFA2/IO206PSB3
GFA1/IO207PDB3
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO205NDB3
GFB2/IO205PDB3
VCC
L8
VCC
J5
L9
VCC
IO110PDB1
VJTAG
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
J7
GND
GND
GDC0/IO111NDB1
GDA1/IO113PDB1
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
J8
GND
VCCIB1
J9
GND
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
IO197NSB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PSB1
P4
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
P5
P6
P7
P8
Revision 9
3-27
Package Pin Assignments
256-Pin FBGA
Pin Number A3P1000L Function
256-Pin FBGA
Pin Number A3P1000L Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
T12
T13
T14
T15
T16
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
TCK
GND
VPUMP
TRST
GDA0/IO113NDB1
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO183RSB2
T3
FF/GEB2/IO186RSB
2
T4
T5
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
T6
T7
T8
T9
T10
T11
3-28
Revision 9
ProASIC3L Low Power Flash FPGAs
324-Pin FBGA
A1 Ball Pad Corner
1
9
7
6
4
3
2
18 17 16 15 14 13 12 11 10
8
5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 9
3-29
Package Pin Assignments
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
Pin Number
Function
Pin Number
B18
C1
Function
Pin Number
D17
D18
E1
Function
A1
GND
IO88PDB2V0
VCCIB2
A2
IO08NDB0V0
IO08PDB0V0
IO10NDB0V1
IO10PDB0V1
IO12PDB0V1
GND
IO305NDB7V3
IO308NDB7V4
GAA2/IO309PPB7V4
GAA1/IO00PPB0V0
VMV0
IO90PDB2V1
IO303NDB7V3
GNDQ
A3
C2
A4
C3
E2
A5
C4
E2
GNDQ
A6
C5
E3
VMV7
A7
C6
IO14NDB0V1
E3
VMV7
A8
IO32NDB0V3
IO32PDB0V3
IO42PPB1V0
IO52NPB1V1
GND
C7
IO18PDB0V2
E4
IO307NPB7V4
VCCPLA
A9
C8
IO40NDB0V4
E5
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
C9
IO40PDB0V4
E6
GAB0/IO01NPB0V0
VCCIB0
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
IO44PDB1V0
E7
IO56NDB1V1
E8
GND
IO66NDB1V3
IO72NDB1V3
IO72PDB1V3
IO74NDB1V4
IO74PDB1V4
GND
IO64NDB1V2
E9
IO28NDB0V3
IO48PDB1V0
GND
IO64PDB1V2
E10
E11
E12
E13
E14
E15
E16
E16
E17
E17
E18
F1
VMV1
GBC0/IO79NDB1V4
GBC1/IO79PDB1V4
GBB2/IO83PPB2V0
IO88NDB2V0
VCCIB1
IO60NPB1V2
VCCPLB
IO305PDB7V3
GAB2/IO308PDB7V4
GAA0/IO00NPB0V0
VCCIB0
IO82NDB2V0
VMV2
B2
IO303PDB7V3
VCCIB7
B3
D2
VMV2
B4
D3
GAC2/IO307PPB7V4
IO309NPB7V4
GAB1/IO01PPB0V0
IO14PDB0V1
GNDQ
B5
GNDQ
D4
GNDQ
B6
IO12NDB0V1
IO18NDB0V2
VCCIB0
D5
IO90NDB2V1
IO299NDB7V3
IO299PDB7V3
IO295PDB7V2
IO295NDB7V2
VCOMPLA
IO291PPB7V2
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO26PDB0V3
IO34PDB0V4
IO58NDB1V2
B7
D6
B8
D7
IO24NDB0V2
F2
B9
IO42NPB1V0
IO44NDB1V0
VCCIB1
D8
IO24PDB0V2
F3
B10
B11
B12
B13
B14
B15
B16
B17
D9
IO28PDB0V3
F4
D10
D11
D12
D13
D14
D15
D16
IO48NDB1V0
F5
IO52PPB1V1
IO66PDB1V3
GNDQ
IO56PDB1V1
F6
IO60PPB1V2
F7
GBB0/IO80NDB1V4
GBB1/IO80PDB1V4
GBA2/IO82PDB2V0
IO83NPB2V0
F8
VCCIB1
F9
GBA0/IO81NDB1V4
GBA1/IO81PDB1V4
F10
F11
3-30
Revision 9
ProASIC3L Low Power Flash FPGAs
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
Pin Number
F12
F13
F14
F15
F16
F17
F18
G1
Function
IO58PDB1V2
IO94PPB2V1
VCOMPLB
GBC2/IO84PDB2V0
IO84NDB2V0
IO92NDB2V1
IO92PDB2V1
GND
Pin Number
H11
H12
H13
H14
H15
H16
H17
H18
J1
Function
Pin Number
Function
VCC
K10
K11
K12
K13
K14
K15
K16
K17
K18
L1
GND
VCC
GND
IO98NDB2V2
GND
IO115NDB3V0
GCB2/IO116PDB3V0
IO116NDB3V0
GCC2/IO117PDB3V0
VCCPLC
GCB1/IO113PDB2V3
GCC1/IO112PPB2V3
VCCIB2
IO108PDB2V3
IO267NDB6V4
GFA0/IO273NDB6V4
VCOMPLF
IO124NPB3V1
IO120PPB3V0
IO263NDB6V3
VCCIB6
G2
IO287PDB7V1
IO287NDB7V1
IO283PPB7V1
VCCIB7
G3
J2
G4
J3
L2
G5
J4
GFA2/IO272PDB6V4
GFB0/IO274NPB7V0
GFC0/IO275NDB7V0
GFC1/IO275PDB7V0
GND
L3
IO259PDB6V3
IO259NDB6V3
GND
G6
IO279PDB7V0
IO291NPB7V2
VCC
J5
L4
G7
J6
L5
G8
J7
L6
IO270NPB6V4
VCC
G9
IO26NDB0V3
IO34NDB0V4
VCC
J8
L7
G10
G11
G12
G13
G14
G15
G16
G17
G18
H1
J9
GND
L8
VCC
J10
J11
J12
J13
J14
J15
J16
J17
J18
K1
GND
L9
GND
IO94NPB2V1
IO98PDB2V2
VCCIB2
GND
L10
L11
L12
L13
L14
L15
L16
L17
L18
M1
M2
M3
M4
M5
M6
M7
M8
GND
GCA2/IO115PDB3V0
GCA1/IO114PDB3V0
GCA0/IO114NDB3V0
GCB0/IO113NDB2V3
VCOMPLC
VCC
VCC
GCC0/IO112NPB2V3
IO104PDB2V2
IO104NDB2V2
GND
IO132PDB3V2
GND
IO117NDB3V0
IO128NPB3V1
VCCIB3
IO120NPB3V0
IO108NDB2V3
IO263PDB6V3
GFA1/IO273PDB6V4
VCCPLF
IO267PDB6V4
VCCIB7
H2
IO124PPB3V1
GND
H3
IO283NPB7V1
GFB1/IO274PPB7V0
GND
K2
H4
K3
IO255PDB6V2
IO255NDB6V2
IO251PPB6V2
VCCIB6
H5
K4
IO272NDB6V4
GFC2/IO270PPB6V4
GFB2/IO271PDB6V4
IO271NDB6V4
GND
H6
IO279NDB7V0
VCC
K5
H7
K6
H8
VCC
K7
GEB0/IO235NDB6V0
GEB1/IO235PDB6V0
VCC
H9
GND
K8
H10
GND
K9
GND
Revision 9
3-31
Package Pin Assignments
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
324-Pin FBGA
A3PE3000L
Pin Number
Function
IO192PPB4V4
IO154NPB4V0
VCC
Pin Number
Function
IO214PDB5V2
VCCIB5
Pin Number
Function
IO231NPB5V4
VMV5
M9
P6
T4
M10
M11
M12
M13
M14
M15
M16
M17
M18
N1
P7
T5
P8
GND
T6
IO208NDB5V1
IO202NDB5V1
IO194NDB5V0
IO186NDB4V4
IO178NDB4V3
IO166NPB4V1
IO164NDB4V1
IO156NDB4V0
VMV4
GDA0/IO153NPB3V4
IO132NDB3V2
VCCIB3
P9
IO174NDB4V2
IO170NDB4V2
GND
T7
P10
P11
P12
P13
P14
P15
P16
P17
P18
R1
T8
T9
IO134NDB3V2
IO134PDB3V2
IO128PPB3V1
GND
VCCIB4
T10
T11
T12
T13
T14
T15
T16
T16
T17
T18
U1
IO155NPB4V0
VCCPLD
VJTAG
IO247NDB6V1
IO247PDB6V1
IO251NPB6V2
GEC0/IO236NDB6V0
VCOMPLE
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
IO142PDB3V3
IO245NDB6V1
VCCIB6
N2
TDI
N3
GNDQ
N4
GNDQ
N5
R2
TDO
N6
IO212NDB5V2
IO212PDB5V2
IO192NPB4V4
IO174PDB4V2
IO170PDB4V2
GDA2/IO154PPB4V0
GDB2/IO155PPB4V0
GDA1/IO153PPB3V4
VCOMPLD
R3
GEA1/IO234PPB6V0
IO232NDB5V4
IO146PDB3V4
IO241NDB6V0
GEA2/IO233PPB5V4
GEC2/IO231PPB5V4
VCCIB5
N7
R4
N8
R5
FF/GEB2/IO232PDB5
V4
U2
N9
U3
R6
R7
IO214NDB5V2
IO202PDB5V1
IO194PDB5V0
IO186PDB4V4
IO178PDB4V3
IO168NSB4V1
IO164PDB4V1
GDC2/IO156PDB4V0
TCK
N10
N11
N12
N13
N14
N15
N16
N17
N18
P1
U4
U5
GNDQ
R8
U6
IO208PDB5V1
IO198PPB5V0
VCCIB5
R9
U7
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
U8
GDB0/IO152NDB3V4
GDB1/IO152PDB3V4
IO138NDB3V3
IO138PDB3V3
IO245PDB6V1
GNDQ
U9
IO182NPB4V3
IO180NPB4V3
VCCIB4
U10
U11
U12
U13
U14
U15
U16
U17
U17
U18
IO166PPB4V1
IO162PDB4V1
GNDQ
VPUMP
TRST
P2
VCCIB3
P2
GNDQ
VCCIB4
IO142NDB3V3
IO241PDB6V0
GEA0/IO234NPB6V0
IO233NPB5V4
P3
VMV6
TMS
P3
VMV6
VMV3
T2
P4
GEC1/IO236PDB6V0
VCCPLE
VMV3
T3
P5
IO146NDB3V4
3-32
Revision 9
ProASIC3L Low Power Flash FPGAs
324-Pin FBGA
A3PE3000L
Pin Number
Function
V1
GND
V2
IO218NDB5V3
IO218PDB5V3
IO206NDB5V1
IO206PDB5V1
IO198NPB5V0
GND
V3
V4
V5
V6
V7
V8
IO190NDB4V4
IO190PDB4V4
IO182PPB4V3
IO180PPB4V3
GND
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
IO162NDB4V1
IO160NDB4V0
IO160PDB4V0
IO158NDB4V0
IO158PDB4V0
GND
Revision 9
3-33
Package Pin Assignments
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
3-34
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
Pin Number A3P600L Function
A1
A2
GND
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
IO101RSB2
NC
B7
B8
IO12RSB0
NC
A3
VCCIB0
NC
B9
NC
A4
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO17RSB0
NC
A5
NC
NC
A6
IO09RSB0
IO15RSB0
NC
NC
NC
A7
VCCIB1
GND
IO36RSB0
NC
A8
A9
NC
GND
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
IO22RSB0
IO23RSB0
IO29RSB0
IO35RSB0
NC
AB2
GND
IO47RSB0
IO49RSB0
NC
AB3
VCCIB2
NC
AB4
AB5
NC
NC
AB6
IO130RSB2
IO128RSB2
IO122RSB2
IO116RSB2
NC
NC
NC
AB7
VCCIB1
GND
VCCIB3
NC
IO46RSB0
IO48RSB0
NC
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
NC
C3
NC
VCCIB0
GND
IO113RSB2
IO112RSB2
NC
C4
NC
C5
GND
NC
GND
C6
GND
NC
C7
NC
VCCIB3
NC
IO100RSB2
IO95RSB2
NC
C8
VCC
VCC
NC
C9
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
NC
NC
NC
IO135RSB2
IO133RSB2
NC
VCCIB2
GND
NC
NC
GND
VCC
VCC
NC
NC
GND
NC
B2
VCCIB3
NC
NC
B3
NC
NC
B4
NC
GND
NC
NC
B5
NC
NC
B6
IO08RSB0
NC
Revision 9
3-35
Package Pin Assignments
484-Pin FBGA
Pin Number A3P600L Function
484-Pin FBGA
484-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
C21
C22
D1
NC
VCCIB1
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO38RSB0
IO42RSB0
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
GBA2/IO60PDB1
IO60NDB1
GND
G5
G6
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
NC
G7
D2
NC
G8
D3
NC
G9
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO45RSB0
GNDQ
D4
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO11RSB0
IO16RSB0
IO18RSB0
IO28RSB0
IO34RSB0
IO37RSB0
IO41RSB0
IO43RSB0
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
D6
D7
NC
D8
NC
D9
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
NC
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
NC
F3
NC
F4
IO173NDB3
IO174NDB3
VMV3
F5
F6
F7
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
NC
F8
NC
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
NC
H5
NC
H6
NC
H7
E2
NC
H8
E3
GND
H9
VCCIB0
E4
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
IO61NPB1
IO63PDB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO25RSB0
IO31RSB0
VCCIB0
E6
E7
GAB1/IO03RSB0
IO13RSB0
IO14RSB0
IO21RSB0
IO27RSB0
IO32RSB0
NC
E8
NC
VCCIB0
E9
IO170NDB3
IO170PDB3
NC
VMV1
E10
E11
E12
G2
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
G3
G4
IO171NDB3
3-36
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
Pin Number A3P600L Function
H19
H20
H21
H22
J1
IO66PDB1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO158NPB3
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
NC
GND
M5
NC
VCC
M6
NC
VvB1
M7
IO160NDB3
GFB2/IO160PDB3
VCC
J2
NC
GCC1/IO69PPB1
IO65NPB1
IO75PDB1
IO75NDB1
NC
M8
J3
NC
M9
J4
IO166NDB3
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
IO76NDB1
IO76PDB1
NC
GND
J8
VCC
J9
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
GCA2/IO72PDB1
IO79PPB1
IO78PPB1
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO155PDB3
NC
VCC
L3
VCC
L4
GFB0/IO163NPB3
GFA0/IO162NDB3
GFB1/IO163PPB3
VCOMPLF
GFC0/IO164NPB3
VCC
VCC
L5
GND
L6
VCCIB1
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
NC
L7
L8
L9
IO154NDB3
IO154PDB3
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
IO68PDB1
IO68NDB1
IO157PDB3
IO157NDB3
NC
GND
N5
VCC
N6
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
GCB0/IO70NPB1
IO77PDB1
IO77NDB1
IO78NPB1
NC
N7
K2
N8
K3
N9
VCC
K4
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
VCC
N10
N11
N12
N13
N14
N15
N16
GND
K5
GND
K6
GND
K7
GND
K8
VCC
K9
VCCIB1
K10
GND
M2
IO155NDB3
IO73NPB1
Revision 9
3-37
Package Pin Assignments
484-Pin FBGA
Pin Number A3P600L Function
484-Pin FBGA
484-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
N17
N18
N19
N20
N21
N22
P1
IO80NPB1
IO74NPB1
IO72NDB1
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB2
VCCIB2
U1
U2
IO149PDB3
IO149NDB3
NC
IO117RSB2
IO110RSB2
VCCIB2
U3
U4
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
IO79NPB1
NC
U5
VCCIB2
U6
NC
VMV2
U7
IO138RSB2
IO136RSB2
IO131RSB2
IO124RSB2
IO119RSB2
IO107RSB2
IO104RSB2
IO97RSB2
VMV1
P2
IO153PDB3
IO153NDB3
IO159NDB3
IO156NPB3
IO151PPB3
IO158PPB3
VCCIB3
GND
IO94RSB2
GDB1/IO87PPB1
GDC1/IO86PDB1
IO84NDB1
VCC
U8
P3
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO81NDB1
IO82PDB1
IO152PDB3
IO152NDB3
NC
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
TRST
VCC
T5
GDA0/IO88NDB1
NC
GND
T6
VCCIB1
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
NC
T7
IO83NDB1
NC
T8
T9
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
GNDQ
NC
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO81PDB1
NC
V5
V6
NC
V7
R2
NC
IO92RSB2
VJTAG
V8
R3
VCC
V9
R4
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
VMV3
GDC0/IO86NDB1
GDA1/IO88PDB1
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO83PDB1
IO82NDB1
R8
3-38
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
484-Pin FBGA
Pin Number A3P600L Function
Pin Number A3P600L Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO96RSB2
Y6
NC
NC
GDB2/IO90RSB2
Y7
TDI
GNDQ
TDO
Y8
VCC
VCC
NC
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
GND
NC
NC
NC
NC
NC
NC
VCC
VCC
NC
W2
IO148PDB3
NC
W3
W4
GND
NC
W5
IO137RSB2
GND
NC
W6
FF/GEB2/IO142RSB
2
NC
W7
W8
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
GDC2/IO91RSB2
IO93RSB2
GDA2/IO89RSB2
TMS
NC
VCCIB1
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB3
Y2
IO148NDB3
NC
Y3
Y4
NC
Y5
GND
Revision 9
3-39
Package Pin Assignments
484-Pin FBGA
Pin Number A3P1000L Function
484-Pin FBGA
484-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
B7
B8
IO15RSB0
IO19RSB0
IO24RSB0
IO31RSB0
IO39RSB0
IO48RSB0
IO54RSB0
IO58RSB0
IO63RSB0
IO66RSB0
IO68RSB0
IO70RSB0
NC
GND
IO122RSB2
IO119RSB2
IO117RSB2
NC
A3
VCCIB0
B9
A4
IO07RSB0
IO09RSB0
IO13RSB0
IO18RSB0
IO20RSB0
IO26RSB0
IO32RSB0
IO40RSB0
IO41RSB0
IO53RSB0
IO59RSB0
IO64RSB0
IO65RSB0
IO67RSB0
IO69RSB0
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
A6
NC
A7
VCCIB1
A8
GND
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
AB3
VCCIB2
AB4
IO180RSB2
IO176RSB2
IO173RSB2
IO167RSB2
IO162RSB2
IO156RSB2
IO150RSB2
IO145RSB2
IO144RSB2
IO132RSB2
IO127RSB2
IO126RSB2
IO123RSB2
IO121RSB2
IO118RSB2
NC
AB5
AB6
NC
AB7
VCCIB1
GND
AB8
AB9
VCCIB3
IO220PDB3
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
C3
VCCIB0
C4
NC
GND
C5
GND
GND
C6
IO10RSB0
IO14RSB0
VCC
GND
C7
VCCIB3
C8
NC
C9
VCC
IO181RSB2
IO178RSB2
IO175RSB2
IO169RSB2
IO166RSB2
IO160RSB2
IO152RSB2
IO146RSB2
IO139RSB2
IO133RSB2
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO30RSB0
IO37RSB0
IO43RSB0
NC
VCCIB2
GND
GND
VCC
GND
VCC
B2
VCCIB3
NC
B3
NC
NC
B4
IO06RSB0
IO08RSB0
IO12RSB0
GND
B5
NC
B6
NC
3-40
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
Pin Number A3P1000L Function
C21
C22
D1
NC
VCCIB1
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO51RSB0
IO57RSB0
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
GBA2/IO78PDB1
IO81PDB1
GND
G5
G6
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
IO219PDB3
IO220NDB3
NC
G7
D2
G8
D3
G9
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
D4
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
IO22RSB0
IO28RSB0
IO35RSB0
IO45RSB0
IO50RSB0
IO55RSB0
IO61RSB0
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
D6
D7
NC
D8
IO84PDB1
NC
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
IO215PDB3
IO215NDB3
IO224NDB3
IO225NDB3
VMV3
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NPB1
IO85PDB1
IO85NDB1
NC
F3
F4
F5
F6
F7
IO11RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
F8
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
NC
H5
NC
H6
IO219NDB3
NC
H7
E2
H8
E3
GND
H9
VCCIB0
E4
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
IO78NDB1
IO81NDB1
IO82PPB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO38RSB0
IO47RSB0
VCCIB0
E6
E7
GAB1/IO03RSB0
IO17RSB0
IO21RSB0
IO27RSB0
IO34RSB0
IO44RSB0
E8
IO84NDB1
IO214NDB3
IO214PDB3
NC
VCCIB0
E9
VMV1
E10
E11
E12
G2
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
G3
G4
IO222NDB3
Revision 9
3-41
Package Pin Assignments
484-Pin FBGA
Pin Number A3P1000L Function
484-Pin FBGA
484-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
H19
H20
H21
H22
J1
IO87PDB1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO206NDB3
GFA2/IO206PDB3
GFA1/IO207PDB3
VCCPLF
NC
GND
M5
NC
VCC
M6
IO212NDB3
IO212PDB3
NC
VCCIB1
M7
IO205NDB3
GFB2/IO205PDB3
VCC
J2
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
IO88NDB1
IO94NPB1
IO98NDB1
IO98PDB1
NC
M8
J3
M9
J4
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PPB1
IO101PPB1
IO99PPB1
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO200PDB3
IO210NPB3
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
VCC
L3
VCC
L4
VCC
L5
GND
L6
VCCIB1
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
NC
L7
L8
L9
IO201NDB3
IO201PDB3
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
IO89PDB1
IO89NDB1
IO211PDB3
IO211NDB3
NC
GND
N5
VCC
N6
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
IO97PDB1
IO97NDB1
IO99NPB1
NC
N7
K2
N8
K3
N9
VCC
K4
IO210PPB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
VCC
N10
N11
N12
N13
N14
N15
N16
GND
K5
GND
K6
GND
K7
GND
K8
VCC
K9
VCCIB1
K10
GND
M2
IO200NDB3
IO95NPB1
3-42
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number A3P1000L Function
Pin Number A3P1000L Function
Pin Number A3P1000L Function
N17
N18
N19
N20
N21
N22
P1
IO100NPB1
IO102NDB1
IO102PDB1
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB2
VCCIB2
U1
U2
IO195PDB3
IO195NDB3
IO194NPB3
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
IO147RSB2
IO136RSB2
VCCIB2
U3
U4
IO101NPB1
IO103PDB1
NC
U5
VCCIB2
U6
VMV2
U7
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
P2
IO199PDB3
IO199NDB3
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
IO110NDB1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
VCC
U8
P3
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO104NDB1
IO105PDB1
IO198PDB3
IO198NDB3
NC
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
IO194PPB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
TRST
VCC
T5
GDA0/IO113NDB1
NC
GND
T6
VCCIB1
T7
IO108NDB1
IO109PDB1
NC
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
NC
T8
T9
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO104PDB1
IO103NDB1
NC
V5
V6
V7
R2
IO197PPB3
VCC
IO110PDB1
VJTAG
V8
R3
V9
R4
IO197NPB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
GDC0/IO111NDB1
GDA1/IO113PDB1
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO108PDB1
IO105NDB1
R8
Revision 9
3-43
Package Pin Assignments
484-Pin FBGA
Pin Number A3P1000L Function
484-Pin FBGA
Pin Number A3P1000L Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO125RSB2
GDB2/IO115RSB2
TDI
Y6
IO177RSB2
IO174RSB2
VCC
Y7
Y8
GNDQ
Y9
VCC
TDO
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO154RSB2
IO148RSB2
IO140RSB2
NC
GND
NC
IO109NDB1
NC
VCC
W2
IO191PDB3
NC
VCC
W3
NC
W4
GND
NC
W5
IO183RSB2
GND
W6
FF/GEB2/IO186RSB
2
NC
NC
W7
W8
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
NC
VCCIB1
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB3
Y2
IO191NDB3
NC
Y3
Y4
IO182RSB2
GND
Y5
3-44
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
Pin Number
Function
Pin Number
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
Function
IO170NDB4V2
IO170PDB4V2
IO166NDB4V1
IO166PDB4V1
IO160NDB4V0
IO160PDB4V0
IO158NPB4V0
VCCIB3
Pin Number
Function
IO08PDB0V0
IO14NDB0V1
IO14PDB0V1
IO18NDB0V2
IO24NDB0V2
IO34PDB0V4
IO40PDB0V4
IO46NDB1V0
IO54NDB1V1
IO62NDB1V2
IO62PDB1V2
IO68NDB1V3
IO68PDB1V3
IO72PDB1V3
IO74PDB1V4
IO76NPB1V4
VCCIB2
A1
GND
B5
B6
A2
GND
A3
VCCIB0
B7
A4
IO10NDB0V1
IO10PDB0V1
IO16NDB0V1
IO16PDB0V1
IO18PDB0V2
IO24PDB0V2
IO28NDB0V3
IO28PDB0V3
IO46PDB1V0
IO54PDB1V1
IO56NDB1V1
IO56PDB1V1
IO64NDB1V2
IO64PDB1V2
IO72NDB1V3
IO74NDB1V4
VCCIB1
B8
A5
B9
A6
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A7
A8
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
GND
AB2
GND
AB3
VCCIB5
AB4
IO216NDB5V2
IO216PDB5V2
IO210NDB5V2
IO210PDB5V2
IO208NDB5V1
IO208PDB5V1
IO197NDB5V0
IO197PDB5V0
IO174NDB4V2
IO174PDB4V2
IO172NDB4V2
IO172PDB4V2
IO168NDB4V1
IO168PDB4V1
IO162NDB4V1
IO162PDB4V1
VCCIB4
AB5
AB6
AB7
AB8
AB9
GND
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
VCCIB7
C2
IO303PDB7V3
IO305PDB7V3
IO06NPB0V0
GND
GND
C3
GND
C4
GND
C5
VCCIB6
C6
IO12NDB0V1
IO12PDB0V1
VCC
IO228PDB5V4
IO224PDB5V3
IO218NDB5V3
IO218PDB5V3
IO212NDB5V2
IO212PDB5V2
IO198PDB5V0
IO198NDB5V0
IO188PPB4V4
IO180NDB4V3
IO180PDB4V3
C7
C8
C9
VCC
C10
C11
C12
C13
C14
C15
C16
C17
IO34NDB0V4
IO40NDB0V4
IO48NDB1V0
IO48PDB1V0
VCC
GND
GND
GND
B2
VCCIB7
VCC
B3
IO06PPB0V0
IO08NDB0V0
IO70NDB1V3
IO70PDB1V3
B4
Revision 9
3-45
Package Pin Assignments
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
Pin Number
C18
C19
C20
C21
C22
D1
Function
Pin Number
Function
IO22NDB0V2
IO30NDB0V3
IO38PDB0V4
IO44NDB1V0
IO58NDB1V2
IO58PDB1V2
GBC1/IO79PDB1V4
GBB0/IO80NDB1V4
GNDQ
Pin Number
F22
G1
Function
IO98NDB2V2
IO289NDB7V1
IO289PDB7V1
IO291PPB7V2
IO295PDB7V2
IO297PDB7V2
GAC2/IO307PDB7V4
VCOMPLA
GND
E9
IO76PPB1V4
IO88NDB2V0
IO94PPB2V1
VCCIB2
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
G2
G3
G4
IO293PDB7V2
IO303NDB7V3
IO305NDB7V3
GND
G5
D2
G6
D3
G7
D4
G8
GNDQ
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO20PDB0V2
IO22PDB0V2
IO30PDB0V3
IO38NDB0V4
IO52NDB1V1
IO52PDB1V1
IO66NDB1V3
IO66PDB1V3
GBB1/IO80PDB1V4
GBA0/IO81NDB1V4
GBA1/IO81PDB1V4
GND
GBA2/IO82PDB2V0
IO86NDB2V0
GND
G9
IO26NDB0V3
IO26PDB0V3
IO36PDB0V4
IO42PDB1V0
IO50PDB1V1
IO60NDB1V2
GNDQ
D6
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D7
D8
IO90NDB2V1
IO98PDB2V2
IO299NPB7V3
IO301NDB7V3
IO301PDB7V3
IO308NDB7V4
IO309NDB7V4
VMV7
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
F3
VCOMPLB
F4
GBB2/IO83PDB2V0
IO92PDB2V1
IO92NDB2V1
IO102PDB2V2
IO102NDB2V2
IO105NDB2V2
IO286PSB7V1
IO291NPB7V2
VCC
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO32NDB0V3
IO32PDB0V3
IO44PDB1V0
IO50NDB1V1
IO60PDB1V2
GBC0/IO79NDB1V4
VCCPLB
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
IO88PDB2V0
IO90PDB2V1
IO94NPB2V1
IO293NDB7V2
IO299PPB7V3
GND
H2
H3
H4
IO295NDB7V2
IO297NDB7V2
IO307NDB7V4
IO287PDB7V1
VMV0
H5
E2
H6
E3
H7
E4
GAB2/IO308PDB7V4
GAA2/IO309PDB7V4
GNDQ
VMV2
H8
E5
IO82NDB2V0
IO86PDB2V0
IO96PDB2V1
IO96NDB2V1
H9
VCCIB0
E6
H10
H11
H12
VCCIB0
E7
GAB1/IO01PDB0V0
IO20NDB0V2
IO36NDB0V4
IO42NDB1V0
E8
3-46
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
Pin Number
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
Function
Pin Number
Function
IO279NDB7V0
IO283NDB7V1
IO281NDB7V0
GFC1/IO275PPB7V0
VCCIB7
Pin Number
Function
GCA0/IO114NPB3V0
VCOMPLC
VCCIB1
K4
L17
L18
L19
L20
L21
L22
M1
VCCIB1
K5
VMV1
K6
GCB0/IO113NPB2V3
IO110PPB2V3
IO111NDB2V3
IO111PDB2V3
GNDQ
GBC2/IO84PDB2V0
IO83NDB2V0
IO100NDB2V2
IO100PDB2V2
VCC
K7
K8
K9
VCC
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M2
IO255NPB6V2
IO272NDB6V4
GFA2/IO272PDB6V4
GFA1/IO273PDB6V4
VCCPLF
VMV2
GND
M3
IO105PDB2V2
IO285NDB7V1
IO285PDB7V1
VMV7
GND
M4
VCC
M5
J2
VCCIB2
M6
J3
GCC1/IO112PPB2V3
IO108NDB2V3
IO108PDB2V3
IO110NPB2V3
IO106NPB2V3
IO109NDB2V3
IO107NDB2V3
IO257PSB6V2
IO276PDB7V0
IO276NDB7V0
GFB0/IO274NPB7V0
GFA0/IO273NDB6V4
GFB1/IO274PPB7V0
VCOMPLF
M7
IO271NDB6V4
GFB2/IO271PDB6V4
VCC
J4
IO279PDB7V0
IO283PDB7V1
IO281PDB7V0
IO287NDB7V1
VCCIB7
M8
J5
M9
J6
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J7
GND
J8
GND
J9
GND
GND
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
VCC
VCC
L2
GCB2/IO116PPB3V0
GCA1/IO114PPB3V0
GCC2/IO117PPB3V0
VCCPLC
VCC
L3
VCC
L4
GND
L5
VCCIB2
L6
GCA2/IO115PDB3V0
IO115NDB3V0
IO126PDB3V1
IO124PSB3V1
IO255PPB6V2
IO253NDB6V2
VMV6
IO84NDB2V0
IO104NDB2V2
IO104PDB2V2
IO106PPB2V3
GNDQ
L7
L8
GFC0/IO275NPB7V0
VCC
L9
L10
L11
L12
L13
L14
L15
L16
GND
GND
N2
IO109PDB2V3
IO107PDB2V3
IO277NDB7V0
IO277PDB7V0
GNDQ
GND
N3
GND
N4
GFC2/IO270PPB6V4
IO261PPB6V3
IO263PDB6V3
IO263NDB6V3
VCC
N5
K2
GCC0/IO112NPB2V3
GCB1/IO113PPB2V3
N6
K3
N7
Revision 9
3-47
Package Pin Assignments
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
Pin Number
Function
Pin Number
P21
P22
R1
Function
IO130PDB3V2
IO128NDB3V1
IO247NDB6V1
IO245PDB6V1
VCC
Pin Number
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
Function
IO194NDB5V0
IO186NDB4V4
IO186PDB4V4
GNDQ
N8
VCCIB6
N9
VCC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
GND
R2
GND
R3
VCOMPLD
GND
R4
IO249NPB6V1
IO251NDB6V2
IO251PDB6V2
GEC0/IO236NPB6V0
VMV5
VJTAG
VCC
R5
GDC0/IO151NDB3V4
GDA1/IO153PDB3V4
IO144PDB3V3
IO140PDB3V3
IO134NDB3V2
IO240PPB6V0
IO238PDB6V0
IO238NDB6V0
GEB1/IO235PDB6V0
GEB0/IO235NDB6V0
VMV6
VCCIB3
R6
IO116NPB3V0
IO132NPB3V2
IO117NPB3V0
IO132PPB3V2
GNDQ
R7
R8
R9
VCCIB5
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
IO196NDB5V0
IO196PDB5V0
VCCIB4
U2
IO126NDB3V1
IO128PDB3V1
IO247PDB6V1
IO253PDB6V2
IO270NPB6V4
IO261NPB6V3
IO249PPB6V1
IO259PDB6V3
IO259NDB6V3
VCCIB6
U3
U4
VCCIB4
U5
P2
VMV3
U6
P3
VCCPLD
U7
VCCPLE
P4
GDB1/IO152PPB3V4
GDC1/IO151PDB3V4
IO138NDB3V3
VCC
U8
IO233NPB5V4
IO222PPB5V3
IO206PDB5V1
IO202PDB5V1
IO194PDB5V0
IO176NDB4V2
IO176PDB4V2
VMV4
P5
U9
P6
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P7
P8
IO130NDB3V2
IO134PDB3V2
IO243PPB6V1
IO245NDB6V1
IO243NPB6V1
IO241PDB6V0
IO241NDB6V0
GEC1/IO236PPB6V0
VCOMPLE
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
VCC
VCC
T2
VCC
T3
TCK
VCC
T4
VPUMP
GND
T5
TRST
VCCIB3
T6
GDA0/IO153NDB3V4
IO144NDB3V3
IO140NDB3V3
IO142PDB3V3
IO239PDB6V0
IO240NPB6V0
GDB0/IO152NPB3V4
IO136NDB3V2
IO136PDB3V2
IO138PDB3V3
VMV3
T7
T8
GNDQ
T9
GEA2/IO233PPB5V4
IO206NDB5V1
IO202NDB5V1
T10
T11
V2
3-48
Revision 9
ProASIC3L Low Power Flash FPGAs
484-Pin FBGA
A3PE3000L
484-Pin FBGA
A3PE3000L
Pin Number
Function
Pin Number
W15
W16
W17
W18
W19
W20
W21
W22
Y1
Function
GDC2/IO156PDB4V0
IO154NDB4V0
GDA2/IO154PDB4V0
TMS
V3
GND
V4
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
GNDQ
V5
V6
V7
GEC2/IO231PDB5V4
IO222NPB5V3
IO204NDB5V1
IO204PDB5V1
IO195NDB5V0
IO195PDB5V0
IO178NDB4V3
IO178PDB4V3
IO155NDB4V0
GDB2/IO155PDB4V0
TDI
GND
V8
IO150NDB3V4
IO146NDB3V4
IO148PPB3V4
VCCIB6
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
Y2
IO237NDB6V0
IO228NDB5V4
IO224NDB5V3
GND
Y3
Y4
Y5
Y6
IO220NDB5V3
IO220PDB5V3
VCC
Y7
GNDQ
Y8
TDO
Y9
VCC
GND
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO200PDB5V0
IO192PDB4V4
IO188NPB4V4
IO187PSB4V4
VCC
IO146PDB3V4
IO142NDB3V3
IO239NDB6V0
IO237PDB6V0
IO230PSB5V4
GND
W2
W3
VCC
W4
IO164NDB4V1
IO164PDB4V1
GND
W5
IO232NDB5V4
W6
FF/GEB2/IO232PDB5
V4
IO158PPB4V0
IO150PDB3V4
IO148NPB3V4
VCCIB3
W7
W8
IO231NDB5V4
IO214NDB5V2
IO214PDB5V2
IO200NDB5V0
IO192NDB4V4
IO184NDB4V3
IO184PDB4V3
IO156NDB4V0
W9
W10
W11
W12
W13
W14
Revision 9
3-49
Package Pin Assignments
896-Pin FBGA
A1 Ball Pad Corner
30 29 28 27 26 2524 23 22 21 20 1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Note: This is the bottom view.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
3-50
Revision 9
ProASIC3L Low Power Flash FPGAs
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
A2
A3
GND
GND
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
GEB1/IO235PPB6V0
VCC
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
IO198PDB5V0
IO192NDB4V4
IO192PDB4V4
IO178NDB4V3
IO178PDB4V3
IO174NDB4V2
IO162NPB4V1
VCC
A4
IO14NPB0V1
GND
IO226PPB5V4
VCCIB5
A5
A6
IO07NPB0V0
GND
VCCIB5
A7
VCCIB5
A8
IO09NDB0V1
IO17NDB0V2
IO17PDB0V2
IO21NDB0V2
IO21PDB0V2
IO33NDB0V4
IO33PDB0V4
IO35NDB0V4
IO35PDB0V4
IO41NDB1V0
IO43NDB1V0
IO43PDB1V0
IO45NDB1V0
IO45PDB1V0
IO57NDB1V2
IO57PDB1V2
GND
VCCIB5
A9
VCCIB4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
VCCIB4
VCCPLD
VCCIB4
VCCIB3
VCCIB4
IO150PDB3V4
IO148PDB3V4
IO147NDB3V4
IO145PDB3V3
IO143PDB3V3
IO137PDB3V2
IO254PDB6V2
IO254NDB6V2
IO240PDB6V0
GEC1/IO236PDB6V0
IO237PDB6V0
IO237NDB6V0
VCOMPLE
IO174PDB4V2
VCC
IO142NPB3V3
IO144NDB3V3
IO144PDB3V3
IO146NDB3V4
IO146PDB3V4
IO147PDB3V4
IO139NDB3V3
IO139PDB3V3
IO133NDB3V2
IO256NDB6V2
IO244PDB6V1
IO244NDB6V1
IO241PDB6V0
IO241NDB6V0
IO243NPB6V1
VCCIB6
AC2
AC3
AC4
AC5
AC6
AC7
IO69PPB1V3
GND
AB2
AC8
GND
AB3
AC9
IO226NPB5V4
IO222NDB5V3
IO216NPB5V2
IO210NPB5V2
IO204NDB5V1
IO204PDB5V1
IO194NDB5V0
IO188NDB4V4
IO188PDB4V4
IO182PPB4V3
IO170NPB4V2
IO164NDB4V1
GBC1/IO79PPB1V4
GND
AB4
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AB5
GND
AB6
IO256PDB6V2
IO248PDB6V1
IO248NDB6V1
IO246NDB6V1
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
IO243PPB6V1
IO245NDB6V1
AB7
AB8
VCCPLE
AB9
VCC
AB10
AB11
AB12
AB13
AB14
IO222PDB5V3
IO218PPB5V3
IO206NDB5V1
IO206PDB5V1
IO198NDB5V0
Revision 9
3-51
Package Pin Assignments
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
IO164PDB4V1
IO162PPB4V1
GND
AD26
AD27
AD28
AD29
AD30
AE1
VCCIB3
GDA0/IO153NDB3V4
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
GND
AE30
AF1
IO149PDB3V4
GND
AF2
IO238PPB6V0
VCCIB6
VCOMPLD
AF3
IO150NDB3V4
IO148NDB3V4
GDA1/IO153PDB3V4
IO145NDB3V3
IO143NDB3V3
IO137NDB3V2
GND
AF4
IO220NPB5V3
VCC
IO242PPB6V1
VCC
AF5
AE2
AF6
IO228NDB5V4
VCCIB5
AE3
IO239PDB6V0
IO239NDB6V0
VMV6
AF7
AE4
AF8
IO230PDB5V4
IO229NDB5V4
IO229PDB5V4
IO214PPB5V2
IO208NDB5V1
IO208PDB5V1
IO200PDB5V0
IO196NDB5V0
IO186NDB4V4
IO186PDB4V4
IO180NDB4V3
IO180PDB4V3
IO168NDB4V1
IO168PDB4V1
IO160NDB4V0
IO158NPB4V0
VCCIB4
AE5
AF9
AE5
VMV6
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF29
AF30
AG1
AD2
IO242NPB6V1
IO240NDB6V0
GEC0/IO236NDB6V0
VCCIB6
AE6
GND
AD3
AE7
GNDQ
AD4
AE8
IO230NDB5V4
IO224NPB5V3
IO214NPB5V2
IO212NDB5V2
IO212PDB5V2
IO202NPB5V1
IO200NDB5V0
IO196PDB5V0
IO190NDB4V4
IO184PDB4V3
IO184NDB4V3
IO172PDB4V2
IO172NDB4V2
IO166NDB4V1
IO160PDB4V0
GNDQ
AD5
AE9
AD6
GNDQ
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE28
AE29
AD6
GNDQ
AD7
VCC
AD8
VMV5
AD9
VCCIB5
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
IO224PPB5V3
IO218NPB5V3
IO216PPB5V2
IO210PPB5V2
IO202PPB5V1
IO194PDB5V0
IO190PDB4V4
IO182NPB4V3
IO176NDB4V2
IO176PDB4V2
IO170PPB4V2
IO166PDB4V1
VCCIB4
IO154NPB4V0
VCC
TDO
VCCIB3
VMV4
GNDQ
GND
GNDQ
GDB0/IO152NDB3V4
GDB1/IO152PDB3V4
VMV3
GND
IO238NPB6V0
VCC
TCK
AG2
VCC
VMV3
AG3
IO232NPB5V4
GND
TRST
VCC
AG4
3-52
Revision 9
ProASIC3L Low Power Flash FPGAs
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
AG5
AG6
IO220PPB5V3
IO228PDB5V4
IO231NDB5V4
GEC2/IO231PDB5V4
IO225NPB5V3
IO223NPB5V3
IO221PDB5V3
IO221NDB5V3
IO205NPB5V1
IO199NDB5V0
IO199PDB5V0
IO187NDB4V4
IO187PDB4V4
IO181NDB4V3
IO171PPB4V2
IO165NPB4V1
IO161NPB4V0
IO159NDB4V0
IO159PDB4V0
IO158PPB4V0
GDB2/IO155PDB4V0
GDA2/IO154PPB4V0
GND
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AJ1
IO225PPB5V3
IO223PPB5V3
IO211NDB5V2
IO211PDB5V2
IO205PPB5V1
IO195NDB5V0
IO185NDB4V3
IO185PDB4V3
IO181PDB4V3
IO177NDB4V2
IO171NPB4V2
IO165PPB4V1
IO161PPB4V0
IO157NDB4V0
IO157PDB4V0
IO155NDB4V0
VCCIB4
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK2
IO183NDB4V3
IO183PDB4V3
IO179NPB4V3
IO177PDB4V2
IO173NDB4V2
IO173PDB4V2
IO163NDB4V1
IO163PDB4V1
IO167NPB4V1
VCC
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
IO156NPB4V0
VCC
TMS
GND
GND
GND
AK3
GND
TDI
AK4
IO217PPB5V2
GND
VCC
AK5
VPUMP
AK6
IO215PPB5V2
GND
GND
AK7
GND
AK8
IO207NDB5V1
IO207PDB5V1
IO201NDB5V0
IO201PDB5V0
IO193NDB4V4
IO193PDB4V4
IO197PDB5V0
IO191NDB4V4
IO191PDB4V4
IO189NDB4V4
IO189PDB4V4
IO179PPB4V3
IO175NDB4V2
IO175PDB4V2
IO169NDB4V1
AJ2
GND
AK9
VJTAG
AJ3
GEA2/IO233PPB5V4
VCC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
VCC
AJ4
IO149NDB3V4
GND
AJ5
IO217NPB5V2
VCC
AJ6
AH2
IO233NPB5V4
VCC
AJ7
IO215NPB5V2
IO213NDB5V2
IO213PDB5V2
IO209NDB5V1
IO209PDB5V1
IO203NDB5V1
IO203PDB5V1
IO197NDB5V0
IO195PDB5V0
AH3
AJ8
AH4
FF/GEB2/IO232PPB5
V4
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AH5
AH6
AH7
AH8
AH9
VCCIB5
IO219NDB5V3
IO219PDB5V3
IO227NDB5V4
IO227PDB5V4
Revision 9
3-53
Package Pin Assignments
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
AK23
AK24
AK25
AK26
AK27
AK28
AK29
B1
IO169PDB4V1
GND
B30
C1
GND
GND
D6
D7
GAC1/IO02PDB0V0
IO06NPB0V0
GAB0/IO01NDB0V0
IO05NDB0V0
IO11NDB0V1
IO11PDB0V1
IO23NDB0V2
IO23PDB0V2
IO27PDB0V3
IO40PDB0V4
IO47NDB1V0
IO47PDB1V0
IO55NPB1V1
IO65NDB1V3
IO65PDB1V3
IO71NDB1V3
IO71PDB1V3
IO73NDB1V4
IO73PDB1V4
IO74NDB1V4
GBB0/IO80NPB1V4
GND
IO167PPB4V1
GND
C2
IO309NPB7V4
VCC
D8
C3
D9
GDC2/IO156PPB4V0
GND
C4
GAA0/IO00NPB0V0
VCCIB0
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
E1
C5
GND
C6
IO03PDB0V0
IO03NDB0V0
GAB1/IO01PDB0V0
IO05PDB0V0
IO15NPB0V1
IO25NDB0V3
IO25PDB0V3
IO31NPB0V3
IO27NDB0V3
IO39NDB0V4
IO39PDB0V4
IO55PPB1V1
IO51PDB1V1
IO59NDB1V2
IO63NDB1V2
IO63PDB1V2
IO67NDB1V3
IO67PDB1V3
IO75NDB1V4
IO75PDB1V4
VCCIB1
GND
C7
B2
GND
C8
B3
GAA2/IO309PPB7V4
VCC
C9
B4
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
B5
IO14PPB0V1
VCC
B6
B7
IO07PPB0V0
IO09PDB0V1
IO15PPB0V1
IO19NDB0V2
IO19PDB0V2
IO29NDB0V3
IO29PDB0V3
IO31PPB0V3
IO37NDB0V4
IO37PDB0V4
IO41PDB1V0
IO51NDB1V1
IO59PDB1V2
IO53PDB1V1
IO53NDB1V1
IO61NDB1V2
IO61PDB1V2
IO69NPB1V3
VCC
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
GBA0/IO81NPB1V4
VCC
GBA2/IO82PPB2V0
GND
E2
IO303NPB7V3
VCCIB7
IO64PPB1V2
VCC
E3
E4
IO305PPB7V3
VCC
GBA1/IO81PPB1V4
GND
E5
E6
GAC0/IO02NDB0V0
VCCIB0
IO303PPB7V3
VCC
E7
GBC0/IO79NPB1V4
VCC
D2
E8
IO06PPB0V0
IO24NDB0V2
IO24PDB0V2
IO13NDB0V1
D3
IO305NPB7V3
GND
E9
IO64NPB1V2
GND
D4
E10
E11
D5
GAA1/IO00PPB0V0
3-54
Revision 9
ProASIC3L Low Power Flash FPGAs
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
F1
IO13PDB0V1
IO34NDB0V4
IO34PDB0V4
IO40NDB0V4
IO49NDB1V1
IO49PDB1V1
IO50PDB1V1
IO58PDB1V2
IO60NDB1V2
IO77PDB1V4
IO68NDB1V3
IO68PDB1V3
VCCIB1
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F26
F27
F28
F29
F30
G1
IO48PDB1V0
IO50NDB1V1
IO58NDB1V2
IO60PDB1V2
IO77NDB1V4
IO72NDB1V3
IO72PDB1V3
GNDQ
G21
G22
G23
G24
G25
G25
G26
G27
G28
G29
G30
H1
IO66PDB1V3
VCCIB1
VMV1
VCC
GNDQ
GNDQ
VCCIB2
IO86NDB2V0
IO92NDB2V1
IO100PPB2V2
GND
GND
VMV2
VMV2
IO86PDB2V0
IO92PDB2V1
VCC
IO294PDB7V2
IO294NDB7V2
IO300NDB7V3
IO300PDB7V3
IO295PDB7V2
IO299PDB7V3
VCOMPLA
GND
H2
IO74PDB1V4
VCC
H3
IO100NPB2V2
GND
H4
GBB1/IO80PPB1V4
VCCIB2
H5
G2
IO296NPB7V2
IO306NDB7V4
IO297NDB7V2
VCCIB7
H6
IO82NPB2V0
GND
G3
H7
G4
H8
IO296PPB7V2
VCC
G5
H9
IO08NDB0V0
IO08PDB0V0
IO18PDB0V2
IO26NPB0V3
IO28NDB0V3
IO28PDB0V3
IO38PPB0V4
IO42NDB1V0
IO52NDB1V1
IO52PDB1V1
IO62NDB1V2
IO62PDB1V2
IO70NDB1V3
IO70PDB1V3
GND
F2
G6
GNDQ
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
F3
IO306PDB7V4
IO297PDB7V2
VMV7
G6
GNDQ
F4
G7
VCC
F5
G8
VMV0
F5
VMV7
G9
VCCIB0
F6
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
IO10NDB0V1
IO16NDB0V1
IO22PDB0V2
IO26PPB0V3
IO38NPB0V4
IO36NDB0V4
IO46NDB1V0
IO46PDB1V0
IO56NDB1V1
IO56PDB1V1
IO66NDB1V3
F7
GNDQ
F8
IO12NDB0V1
IO12PDB0V1
IO10PDB0V1
IO16PDB0V1
IO22NDB0V2
IO30NDB0V3
IO30PDB0V3
IO36PDB0V4
IO48NDB1V0
F9
F10
F11
F12
F13
F14
F15
F16
VCOMPLB
GBC2/IO84PDB2V0
Revision 9
3-55
Package Pin Assignments
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
H26
H27
H28
H29
H30
J1
IO84NDB2V0
IO96PDB2V1
IO96NDB2V1
IO89PDB2V0
IO89NDB2V0
IO290NDB7V2
IO290PDB7V2
IO302NDB7V3
IO302PDB7V3
IO295NDB7V2
IO299NDB7V3
VCCIB7
K2
K3
IO288PDB7V1
IO304NDB7V3
IO304PDB7V3
GAB2/IO308PDB7V4
IO308NDB7V4
IO301PDB7V3
IO301NDB7V3
GAC2/IO307PPB7V4
VCC
L8
L9
IO293PDB7V2
IO293NDB7V2
IO307NPB7V4
VCC
K4
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
M1
K5
K6
VCC
K7
VCC
J2
K8
VCC
J3
K9
VCC
J4
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
L1
VCC
J5
IO04PPB0V0
VCCIB0
VCC
J6
VCC
J7
VCCIB0
VCC
J8
VCCPLA
VCCIB0
VCC
J9
VCC
VCCIB0
IO78NPB1V4
IO104NPB2V2
IO98NDB2V2
IO98PDB2V2
IO87PDB2V0
IO87NDB2V0
IO97PDB2V1
IO101PDB2V2
IO103PDB2V2
IO119NDB3V0
IO282NDB7V1
IO282PDB7V1
IO292NDB7V2
IO292PDB7V2
IO283NDB7V1
IO285PDB7V1
IO287PDB7V1
IO289PDB7V1
IO289NDB7V1
VCCIB7
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
IO04NPB0V0
IO18NDB0V2
IO20NDB0V2
IO20PDB0V2
IO32NDB0V3
IO32PDB0V3
IO42PDB1V0
IO44NDB1V0
IO44PDB1V0
IO54NDB1V1
IO54PDB1V1
IO76NPB1V4
VCC
VCCIB1
VCCIB1
VCCIB1
VCCIB1
IO76PPB1V4
VCC
IO78PPB1V4
IO88NDB2V0
IO88PDB2V0
IO94PDB2V1
IO94NDB2V1
IO85PDB2V0
IO85NDB2V0
IO93PDB2V1
IO93NDB2V1
IO286NDB7V1
IO286PDB7V1
IO298NDB7V3
IO298PDB7V3
IO283PDB7V1
IO291NDB7V2
IO291PDB7V2
M2
M3
M4
VCCPLB
M5
VCCIB2
M6
IO90PDB2V1
IO90NDB2V1
GBB2/IO83PDB2V0
IO83NDB2V0
IO91PDB2V1
IO91NDB2V1
IO288NDB7V1
M7
L2
M8
L3
M9
L4
M10
M11
M12
M13
L5
VCC
L6
GND
L7
GND
3-56
Revision 9
ProASIC3L Low Power Flash FPGAs
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
N1
GND
GND
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
P1
VCC
VCCIB2
P26
P27
P28
P29
P30
R1
IO111NPB2V3
IO105PDB2V2
IO105NDB2V2
GCC2/IO117PDB3V0
IO117NDB3V0
GFC2/IO270PDB6V4
GFB1/IO274PPB7V0
VCOMPLF
GND
IO106NDB2V3
IO106PDB2V3
IO108PDB2V3
IO108NDB2V3
IO95NDB2V1
IO99NDB2V2
IO99PDB2V2
IO107PDB2V3
IO107NDB2V3
IO276NDB7V0
IO278NDB7V0
IO280NDB7V0
IO284NDB7V1
IO279NDB7V0
GFC1/IO275PDB7V0
GFC0/IO275NDB7V0
IO277PDB7V0
IO277NDB7V0
VCCIB7
GND
GND
GND
VCC
R2
VCCIB2
R3
NC
R4
GFA0/IO273NDB6V4
GFB0/IO274NPB7V0
IO271NDB6V4
GFB2/IO271PDB6V4
IO269PDB6V4
IO269NDB6V4
VCCIB7
IO104PPB2V2
IO102PDB2V2
IO102NDB2V2
IO95PDB2V1
IO97NDB2V1
IO101NDB2V2
IO103NDB2V2
IO119PDB3V0
IO276PDB7V0
IO278PDB7V0
IO280PDB7V0
IO284PDB7V1
IO279PDB7V0
IO285NDB7V1
IO287NDB7V1
IO281NDB7V0
IO281PDB7V0
VCCIB7
R5
R6
R7
P2
R8
P3
R9
P4
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
T1
P5
VCC
P6
GND
P7
GND
N2
P8
GND
N3
P9
GND
N4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
GND
N5
VCC
GND
N6
GND
GND
N7
GND
GND
N8
GND
VCC
N9
GND
VCCIB2
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
GND
GCC0/IO112NDB2V3
GCB2/IO116PDB3V0
IO118PDB3V0
IO111PPB2V3
IO122PPB3V1
GCA0/IO114NPB3V0
VCOMPLC
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
VCCIB2
GND
GCC1/IO112PDB2V3
IO110PDB2V3
IO110NDB2V3
IO109PPB2V3
GND
GCB1/IO113PPB2V3
IO115NPB3V0
IO270NDB6V4
GND
GND
Revision 9
3-57
Package Pin Assignments
896-Pin FBGA
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function Pin Number A3PE3000L Function
T2
T3
VCCPLF
GFA2/IO272PPB6V4
GFA1/IO273PDB6V4
IO272NPB6V4
IO267NDB6V4
IO267PDB6V4
IO265PDB6V3
IO263PDB6V3
VCCIB6
U8
U9
IO265NDB6V3
IO263NDB6V3
VCCIB6
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
W1
GND
GND
T4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
V1
GND
T5
VCC
GND
T6
GND
GND
T7
GND
GND
T8
GND
VCC
T9
GND
VCCIB3
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
U1
GND
IO120NDB3V0
IO128NDB3V1
IO132PDB3V2
IO130PPB3V2
IO126NDB3V1
IO129NDB3V1
IO127NDB3V1
IO125NDB3V1
IO123PDB3V1
IO266NDB6V4
IO262NDB6V3
IO260NDB6V3
IO252NDB6V2
IO251NDB6V2
IO251PDB6V2
IO255NDB6V2
IO249PPB6V1
IO253PDB6V2
VCCIB6
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
VCCIB3
GND
IO120PDB3V0
IO128PDB3V1
IO124PDB3V1
IO124NDB3V1
IO126PDB3V1
IO129PDB3V1
IO127PDB3V1
IO125PDB3V1
IO121NDB3V0
IO268NDB6V4
IO262PDB6V3
IO260PDB6V3
IO252PDB6V2
IO257NPB6V2
IO261NPB6V3
IO255PDB6V2
IO259PDB6V3
IO259NDB6V3
VCCIB6
GND
GND
GND
VCC
W2
VCCIB3
W3
IO109NPB2V3
IO116NDB3V0
IO118NDB3V0
IO122NPB3V1
GCA1/IO114PPB3V0
GCB0/IO113NPB2V3
GCA2/IO115PPB3V0
VCCPLC
W4
W5
W6
W7
V2
W8
V3
W9
V4
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
V5
VCC
IO121PDB3V0
IO268PDB6V4
IO264NDB6V3
IO264PDB6V3
IO258PDB6V3
IO258NDB6V3
IO257PPB6V2
IO261PPB6V3
V6
GND
V7
GND
U2
V8
GND
U3
V9
GND
U4
V10
V11
V12
V13
GND
U5
VCC
GND
U6
GND
GND
U7
GND
GND
3-58
Revision 9
ProASIC3L Low Power Flash FPGAs
896-Pin FBGA
896-Pin FBGA
Pin Number A3PE3000L Function Pin Number A3PE3000L Function
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
Y1
VCC
VCCIB3
Y26
Y27
Y28
Y29
Y30
IO136PPB3V2
IO141NDB3V3
IO135NDB3V2
IO131NDB3V2
IO133PDB3V2
IO134PDB3V2
IO138PDB3V3
IO132NDB3V2
IO136NPB3V2
IO130NPB3V2
IO141PDB3V3
IO135PDB3V2
IO131PDB3V2
IO123NDB3V1
IO266PDB6V4
IO250PDB6V2
IO250NDB6V2
IO246PDB6V1
IO247NDB6V1
IO247PDB6V1
IO249NPB6V1
IO245PDB6V1
IO253NDB6V2
GEB0/IO235NPB6V0
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
IO142PPB3V3
IO134NDB3V2
IO138NDB3V3
IO140NDB3V3
IO140PDB3V3
Revision 9
3-59
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3L datasheet.
Revision
Changes
Page
July 2010
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The "ProASIC3L Device Status" table on page III indicates the status for each
device in the device family.
N/A
Revision 9 (Feb 2009) The "I/Os Per Package 1" table was revised to change the number of differential
II
I/O pairs for A3PE3000L from 300 to 310.
Product Brief v1.3
Table 2 • ProASIC3L FPGAs Package Sizes Dimensions is new.
II
I
Revision 8 (Feb 2009) The "Advanced and Pro (Professional) I/Os" section was revised to add two
bullets regarding wide range power supply voltage support.
Product Brief v1.2
3.0 V wide range was added to the list of supported voltages in the "I/Os with
Advanced I/O Standards" section. The "Wide Range I/O Support" section is new.
1-7
2-2
Revision 7 (Aug 2008) 3.0
V
LVCMOS wide range support data was added to Table 2-2
•
Recommended Operating Conditions 1.
DC and Switching
Characteristics
Advance v0.6
3.3 V LVCMOS wide range support data was added to Table 2-22 • Summary of 2-22 to
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings to Table 2-24 • Summary of
Maximum and Minimum DC Input and Output Levels Applicable to Commercial
and Industrial Conditions—Software Default Settings.
2-23
3.3 V LVCMOS wide range support data was added to Table 2-26 • Summary of
AC Memory Points.
2-25
2-39
2-40
2-7
3.3 V LVCMOS wide range support text was added to the "3.3 V LVTTL / 3.3 V
LVCMOS" section.
Table 2-48 • Minimum and Maximum DC Input and Output Levels for LVCMOS
3.3 V Wide Range is new.
Revision 6 (Aug 2008) Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated to add several new rows of values.
DC and Switching
Characteristics
Advance v0.5
Table 2-7
• Quiescent Supply Current (IDD) Characteristics, ProASIC3L 2-7 to 2-8
Flash*Freeze Mode* through Table 2-10 • Quiescent Supply Current (IDD), No
ProASIC3L Flash*Freeze Mode1 were updated to add 1.5 V core voltage.
Table 2-18 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3L Devices at 1.5 V VCC is new.
2-14
2-14
Table 2-19 • Different Components Contributing to the Static Power Consumption
in ProASIC3L Devices was updated to add the static PLL contribution at 1.5 V
core operation.
Timing tables were updated to include tables for 1.5 V core voltage.
N/A
Revision 9
4-1
Datasheet Information
Revision
Changes
Page
Revision 6 (cont’d)
Table 2-206 • ProASIC3LP CCC/PLL Specification was updated for core voltage
1.2 V and Table 2-207 • ProASIC3LP CCC/PLL Specification for 1.5 V is new.
2-126,
2-127
Revision 5 (Jul 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
N/A
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.4
Revision 4 (Jun 2008) Tables have been updated to include the LVCMOS 1.2 V I/O set.
N/A
DC and Switching
Characteristics
Advance v0.3
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
Power data table has been updated to match SmartPower data rather then
simulation values.
Table 2-1 • Absolute Maximum Ratings was updated to add VMV to the VCCI
parameter row and to remove the word "output" from the parameter description
for VCCI. Table note 3 was added.
2-1
2-2
Table 2-2 • Recommended Operating Conditions 1 was updated to add table note
references and rearrange the order of notes. VMV was added to the VCCI
parameter row. A new row was added for VCC, 1.5 V DC core supply voltage.
The table note stating that 1.5 V data will be released at a later date is new. The
table note on VMV pins is new.
Table 2-4 • Overshoot and Undershoot Limits 1. The title was revised to remove
"as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO
density over cycles." Table note 3 was revised to remove "refers only to
overshoot/undershoot limits for simultaneous switching I/Os."
2-3
EQ 2 was updated. The temperature was changed to 100°C, and therefore the
end result changed.
2-6
2-7
The table notes for Table 2-7 • Quiescent Supply Current (IDD) Characteristics,
ProASIC3L Flash*Freeze Mode* and Table 2-8 • Quiescent Supply Current (IDD
)
Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)* were updated to remove
VMV and include PDC6 and PDC7. The table note for Table 2-7 • Quiescent
Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* was
updated to include VJTAG.
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode
(VCC, VCCI = 0 V) is new.
2-7
2-8
Note 2 of Table 2-10 • Quiescent Supply Current (IDD), No ProASIC3L
Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to
include PDC6 and PDC7
.
Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
2-9
Settings through Table 2-16 • Summary of I/O Output Buffer Power (per pin) – through
Default I/O Software Settings 1were updated to change PDC2 to PDC6 and PDC3 to
2-12
PDC7. The table notes were updated to reflect that power was measured on VCCI
.
The subtitle of the table was changed from "Applicable to Advanced I/O Banks" to
"Applicable to Pro I/O Banks."
The word "input" in the titles of Table 2-14 • Summary of I/O Output Buffer Power 2-11, 2-12
(per pin) – Default I/O Software Settings 1 and Table 2-15 • Summary of I/O
Output Buffer Power (per pin) – Default I/O Software Settings 1, was changed to
"output."
4-2
Revision 9
ProASIC3L Low Power Flash FPGAs
Revision
Changes
The value of CLOAD for single-ended 3.3 V PCI was changed to 10 from 5 in
Page
Revision 4 (cont’d)
2-11
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software through
Settings 1 through Table 2-16 • Summary of I/O Output Buffer Power (per pin) –
Default I/O Software Settings 1.
2-12
The last section of Table 2-17 • Different Components Contributing to Dynamic
Power Consumption in ProASIC3L Devices at 1.2 V VCC was made into a new
table: Table 2-18 • Different Components Contributing to Dynamic Power
Consumption in ProASIC3L Devices at 1.5 V VCC. The table numbers
referenced for device-specific dynamic power for PAC9 and PAC10 were changed
2-13
in Table 2-17
• Different Components Contributing to Dynamic Power
Consumption in ProASIC3L Devices at 1.2 V VCC. The definition of PDC5 was
updated and parameters PDC6 and PDC7 were added to Table 2-19 • Different
Components Contributing to the Static Power Consumption in ProASIC3L
Devices.
The "Total Static Power Consumption—PSTAT" section was updated to revise the
2-15
calculation of PSTAT, including PDC6 and PDC7
.
Footnote 1 was updated to include information about PAC13
.
2-16
2-37
Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for
Schmitt Mode Input Buffers was updated to include the hysteresis value for 1.2 V
LVCMOS.
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-71
N/A
Revision 3 (Apr 2008) The product brief was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
Product Brief v1.0
Packaging v1.1
The "324-Pin FBGA" package diagram was replaced.
3-29
Revision 2 (Apr 2008) Reference to M1A3P250L was removed from Table 1 • ProASIC3 Low-Power I, II, III, IV
Product Family, the "I/Os Per Package 1" table, the "ProASIC3L Ordering
Information" section, and the "Temperature Grade Offerings" table. The table
note regarding M1A3P250L was removed from the "I/Os Per Package 1" table.
Product Brief rev. 1
Revision 1 (Feb 2008) The "PLL Behavior at Brownout Condition" section is new.
2-4
DC and Switching Table 2-198 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage, 2-122 –
Characteristics
Advance v0.2
Table 2-200 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage,
Table 2-202 • A3P1000L Global Resource – Applies to 1.5 V DC Core Voltage,
and Table 2-204 • A3PE3000L Global Resource – Applies to 1.5 V DC Core
2-125
Voltage were updated with values for tRCKL, tRCKH, and tRCKSW
.
The worst-case commercial conditions were added to Table 2-215 • Embedded
FlashROM Access Time– Applies to 1.2 V DC Core Voltage.
2-143
2-13
Table 2-17 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3L Devices at 1.2 V VCC was updated to revise the value for PAC14
and add parameters PDC1 through PDC5 to the table.
Revision 9
4-3
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "ProASIC3L Device Status" table on page III, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any Actel product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications.
A
reliability report covering all of Actel’s products is available on the Actel website at
http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification
and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability
information.
4-4
Revision 9
Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of
system and power management solutions. Power Matters. Learn more at www.actel.com.
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
Phone 650.318.4200
Fax 650.318.4600
River Court,Meadows Business Park EXOS Ebisu Buillding 4F
Room 2107, China Resources Building
26 Harbour Road
Wanchai, Hong Kong
Phone +852 2185 6460
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Phone +81.03.3445.7671
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http://jp.actel.com
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Fax +44 (0) 1276 607 540
www.actel.com.cn
© Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are
trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners.
51700100-9/2.09
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