ACE25QC200GLFMUH [ACE]
2M BIT SPI NOR FLASH;
| 型号： | ACE25QC200GLFMUH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | 2M BIT SPI NOR FLASH |
| 文件： | 总64页 (文件大小：2572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE25QC200GL
2M BIT SPI NOR FLASH
Description
The ACE25QC200GL is 2M-bit Serial Peripheral Interface (SPI) Flash memory, designed for using in a
wide variety of high-volume consumer based applications in which program code is shadowed from Flash
memory into embedded or external RAM for execution. The flexible erase architecture of the device, with
its page erase granularity it is ideal for data storage as well, eliminating the need for additional data storage
devices.
The erase block sizes of the device have been optimized to meet the needs of today's code and data
storage applications. By optimizing the size of the erase blocks, the memory space can be used much
more efficiently. Because certain code modules and data storage segments must reside by themselves in
their own erase regions, the wasted and unused memory space that occurs with large sectored and large
block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows
additional code routines and data storage segments to be added while still maintaining the same overall
device density.
The device uses a single low voltage power supply, ranging from 1.65 Volt to 2.0 Volt, and supports JEDEC
standard manufacturer and device ID, a 128-bit Unique Serial Number and three 256-bytes Security
Registers.
Features
Serial Peripheral Interface (SPI)
Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD
Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD
Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
Software Reset
Read
Normal Read Data: 33MHz clock rate
others Read Data: 85MHz clock rate
Program
Serial-input Page Program up to 256bytes
Dual-input Page Program up to 256bytes
Quad-input Page Program up to 256bytes
Program Suspend and Resume
Erase
Page erase (256-byte)
Block erase (64/32 KB)
Sector erase (4 KB)
Chip erase
Erase Suspend and Resume
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Program/Erase Speed
Page Program time: 2ms typical
Page Erase time: 8ms typical
Sector/Block Erase time: 8ms typical
Chip Erase time: 8ms typical
Flexible Architecture
Sector of 4K-byte
Block of 32/64K-byte
Low Power Consumption
3mA maximum active current
0.6uA maximum power down current
Software/Hardware Write Protection
3x512-Byte Security Registers with OTP Lock
Enable/Disable protection with WP Pin
Write protect all/portion of memory via software protect
Top or Bottom, Sector or Block selection
Single Supply Voltage
Full voltage range: 1.65~2.0V
Temperature Range
Industrial (-40℃ to +85℃)
Cycling Endurance/Data Retention
Typical 100k Program-Erase cycles on any sector
Typical 20-year data retention
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Packaging Type
SOP-8
SOP-8L
TSSOP-8
USON3*2-8
Ordering information
ACE25QC200GL XXX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
TM: TSSOP-8
UA8: USON3*2-8
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or
VOL, see DC Electrical Characteristics). These signals are described next.
Table1. Signal Names
Pin No
Pin Name
I/O
Function
1
/CS
I
Chip Select
Serial Output for single bit data Instructions. IO1 for Dual or Quad
Instructions.
2
SO (IO1)
I/O
Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.
3
/WP (IO2)
I/O The signal has an internal pull-up resistor and may be left unconnected in
the host system if not used for Quad Instructions.
Ground
4
5
6
VSS
SI (IO0)
SCLK
Serial Input for single bit data Instructions. IO0 for Dual or Quad
I/O
Instructions.
I
Serial Clock
Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in
7
8
/HOLD (IO3) I/O Quad-I/O mode. The signal has an internal pull-up resistor and may be
left unconnected in the host system if not used for Quad Instructions.
VCC
Core and I/O Power Supply
Chip Select (/CS)
The chip select signal indicates when an instruction for the device is in process and the other signals are
relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected
and all input signals are ignored and all output signals are high impedance. Unless an internal Program,
Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power
mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After
Power Up, a falling edge on /CS is required prior to the start of any instruction.
Serial Clock (SCLK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or
data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of
SCLK.
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ACE25QC200GL
2M BIT SPI NOR FLASH
Serial Input (SI)/IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and
data to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 an input and output during Dual and Quad SPI mode for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK).
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 an input and output during Dual and Quad SPI mode for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK).
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status
Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status
Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the
memory area that are protected by the Block Protect, BP4, BP3 bits in the status registers, are also
hardware protected against data modification while /WP remains Low. The /WP function is not available
when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1).
The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and
data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data
(on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and
may be left unconnected in the host system if not used for Quad mode.
HOLD (/HOLD)/IO3
The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
When QE=0, the IO3 pin can be configured either as a /HOLD pin. When QE=1, the /HOLD function is not
available.
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ACE25QC200GL
2M BIT SPI NOR FLASH
The HOLD function is replaced by IO3 for input and output during Quad mode for receiving addresses, and
data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data
(on the falling edge of SCK).
VCC Power Supply
VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and
erase.
VSS Ground
VSS is the reference for the VCC supply voltage.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Block/Sector Architecture
Table2. ACE25QC200GL Block/Sector Addresses
Memory
Sector
Block(64k byte) Block(32k byte)
Density
Sector No.
Sector 0
Address range
Size(KB)
4
000000h-000FFFh
Half block 0
Block 0
:
:
4
4
:
:
Sector 7
Sector 8
:
007000h-007FFFh
008000h-008FFFh
:
Half block 1
Sector 15
Sector 16
:
4
4
:
00F000h-00FFFFh
010000h-010FFFh
:
Half block 2
Block 1
Sector 23
Sector 24
:
4
4
:
017000h-017FFFh
018000h-018FFFh
:
Half block 3
Sector 31
Sector 32
:
4
4
:
01F000h-01FFFFh
020000h-020FFFh
:
2Mbit
Half block 4
Block 2
Sector 39
Sector 40
:
4
4
:
027000h-027FFFh
028000h-028FFFh
:
Half block 5
Sector 47
Sector 48
:
4
4
:
02F000h-02FFFFh
030000h-030FFFh
:
Half block 6
Block 3
Sector 55
Sector 56
:
4
4
:
037000h-037FFFh
038000h-038FFFh
:
Half block 7
Sector 63
4
03F000h-03FFFFh
Notes:
1. Block = Uniform Block, and the size is 64K bytes.
2. Half block = Half Uniform Block, and the size is 32k bytes.
3. Sector = Uniform Sector, and the size is 4K bytes.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Function Descriptions
Standard SPI Instructions
The ACE25QC200GL features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported.
Dual SPI Instructions
The ACE25QC200GL supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O
Fast Read” (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the
device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins
become bidirectional I/O pins: IO0 and IO1
Quad SPI Instructions
The ACE25QC200GL supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read”, (6Bh, EBh,) instructions. These instructions allow data to be transferred to or from the device
at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions
require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set to 1.
All of the above three SPI mode (Standard SPI, Dual SPI and Quad SPI) have input bits (including
instructions, addresses, data, M7~M0, W6~W4 etc.) latched on the rising edge of SCLK and output bits
shifted out on the falling edge of SCLK.
Operation Features
Supply Voltage
(A) Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the
specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage,
it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to
100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of
the transmission of the instruction and, for a Write instruction, until the completion of the internal write
cycle (tW).
(B) Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the
Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected until a falling
edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have
been High, prior to going Low to start the first operation.
(C) Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on
reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC
has reached the power on reset threshold voltage.
When VCC has passed the POR threshold, the device is reset.
(D) Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any instruction
sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to
follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal
Write cycle in progress).
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the
device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
Hold Condition
The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if /CS drives high
during HOLD operation, it will reset the internal logic of the device to Standby Mode. To re-start
communication with chip, the /HOLD must be at high and the /CS must be at low.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Figure1. Hold condition activation
Status Register
Status Register Table
Table3. The Status and Control Bits
SR2
S15
S14
S13
LB3
0
S12
LB2
0
S11
LB1
0
S10
SUS2
n/a
S9
QE
0
S8
SRP1
0
SUS1
n/a
CMP
0
Default value Note1
SR1
S7
SRP0
0
S6
BP4
0
S5
BP3
0
S4
S3
S2
S1
S0
WIP
n/a
BP2
0
BP1
0
BP0
0
WEL
n/a
Default value Note1
Notes:
1. The default value is set by Manufacturer during wafer sort, Marked as Default in following text
The status and control bits of the Status Register are as follows:
(A) WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program / erase / write status
register progress. When WIP bit is set to 1, means that the device is busy in program / erase / write
status register progress, when WIP bit is cleared to 0, means that the device is not in program / erase /
write status register progress.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
(B) WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When WEL bit is set
to 1 the internal Write Enable Latch is set, when WEL bit is cleared to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or Erase instruction is accepted.
(C) BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with the Write
Status Register instruction. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory (as defined in Table 4 and Table 5) are became protected against Page Program,
Page Erase, Sector Erase and Block Erase instructions. The Block Protect (BP4, BP3, BP2, BP1, BP0)
bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase
instruction is executed. If the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1 and BP0) bits are 1and CMP=1.
(D) RP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status
register. The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable protection.
Table4. ACE25QC200GL Status Register protect table
SRP1 SRP0
/WP
Status Register
Description
The Status Register can be written to after a Write
Enable instruction, WEL=1.(Factory Default)
/WP=0, the Status Register locked and cannot be
written.
0
0
0
1
0
1
1
0
1
X
Software Protected
0
1
Hardware Protected
/WP=1, the Status Register is unlocked and can be
written to after a Write Enable instruction, WEL=1.
Status Register is protected and cannot be written to
again until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot
be written to.
Hardware Unprotected
Power Supply
Lock-Down(1)
X
X
One Time Program(2)
1
Notes:
1.
2.
When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
The One time Program feature is available upon special order.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
(E) QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad SPI
operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE
bit is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during
standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground).
(F) LB3/LB2/LB1 bit
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB is 0, the security
registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One
Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently
(LB3-1 corresponds to S13-11).
(G) SUS1, SUS2 bit
The SUS1 and SUS2 bit are read only bits in the status register2 (S15 and S10) that are set to 1 after
executing a Program/Erase Suspend (75H) instruction (The Erase Suspend will set SUS1 to 1. The
Program Suspend will set the SUS2 to 1). The SUS bits are cleared to 0 by Program/Erase Resume
(7AH) instruction. Software reset (66H/99H) instruction as well as a power-down, power-up cycle.
(H) Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register. It is used in
conjunction with BP4, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection.
Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Status Register Memory Protection
Protect Table
Table5. ACE25QC200GL Status Register Memory Protection (CMP=0)
Status Register(1)
ACE25QC200GL (2M-BIT) Memory Protection(3)
Protected
Protected
Density
NONE
64KB
128KB
256KB
64KB
128KB
256KB
512KB
4KB
Protected
Portion(2)
NONE
BP4 BP3 BP2 BP1 BP0
Protected Addresses
Block(S)
X
X
0
0
0
1
1
1
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
1
1
X
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
X
1
0
1
X
0
1
0
1
X
0
1
NONE
NONE
0
7
070000h – 07FFFFh
060000h – 07FFFFh
040000h – 07FFFFh
000000h – 00FFFFh
000000h – 01FFFFh
000000h – 03FFFFh
000000h – 07FFFFh
07F000h – 07FFFFh
07E000h – 07FFFFh
07C000h – 07FFFFh
078000h – 07FFFFh
078000h – 07FFFFh
000000h – 000FFFh
000000h – 001FFFh
000000h – 003FFFh
000000h – 007FFFh
000000h – 007FFFh
000000h – 07FFFFh
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/8
Lower 1/4
Lower 1/2
ALL
0
6 and 7
0
4 to 7
0
0
0
0 to 1
0
0 to 3
0
0 to 7
1
7
U - 1/128
U - 1/64
U - 1/32
U - 1/16
U - 1/16
L - 1/128
L - 1/64
L - 1/32
L - 1/16
L - 1/16
ALL
1
7
8KB
1
7
16KB
32KB
32KB
4KB
1
7
1
7
1
0
1
0
8KB
1
0
0
16KB
32KB
32KB
512KB
1
1
1
0
0 to 7
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program instruction specifies a memory region that contains protected data portion, this
instruction will be ignored.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Table6. ACE25QC200GL Status Register Memory Protection (CMP=1)
Status Register(1)
ACE25QC200GL (2M-BIT) Memory Protection(3)
Protected
Block(S)
0 to 7
Protected
Density
512KB
448KB
384KB
256KB
448KB
384KB
256KB
NONE
508KB
504KB
496KB
480KB
480KB
508KB
504KB
496KB
480KB
480KB
NONE
Protected
Portion(2)
All
BP4 BP3 BP2 BP1 BP0
Protected Addresses
X
X
0
0
0
1
1
1
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
1
1
X
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
X
1
0
1
X
0
1
0
1
X
0
1
000000h – 07FFFFh
000000h – 06FFFFh
000000h – 05FFFFh
000000h – 03FFFFh
010000h – 07FFFFh
020000h – 07FFFFh
040000h – 07FFFFh
NONE
0
0 to 6
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
NONE
0
0 and 5
0 to 3
0
0
1 to 7
0
2 to 7
0
4 to 7
0
NONE
0 to 7
1
000000h –07EFFFh
000000h – 07DFFFh
000000h – 07BFFFh
000000h – 077FFFh
000000h – 077FFFh
001000h – 07FFFFh
002000h – 07FFFFh
004000h – 07FFFFh
008000h – 07FFFFh
008000h – 07FFFFh
NONE
L - 127/128
L - 63/64
L - 31/32
L - 15/16
L - 15/16
U - 127/128
U- 63/64
U- 31/32
U- 15/16
U - 15/16
NONE
1
0 to 7
1
0 to 7
1
0 to 7
1
0 to 7
1
0 to 7
1
0 to 7
1
0 to 7
1
0 to 7
1
1
0 to 7
NONE
Notes:
1.
2.
3.
X = don’t care
L = Lower; U = Upper
If any Erase or Program instruction specifies a memory region that contains protected data portion, this
instruction will be ignored.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Device Identification
Three legacy Instructions (9Fh/90h/ABh) and two new Instructions (92h/94h) in Dual/Quad SPI mode are
supported to access device identification that can indicate the manufacturer, device type, and capacity
(density). The returned data bytes provide the information as shown in the below table.
Table7. ACE25QC200GL ID Definition table
Operation Code
9Fh
M7-M0
68
ID15-ID8
60
ID7-ID0
13
90h/92h/94h
ABh
68
12
12
Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant
bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be
shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table 8, every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
For the instruction of Read, Fast Read, Read Status Register-1, Read Status Register-2 or Release from
Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out
sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out.
For the instruction of Page Program, Page Erase, Sector Erase, Block Erase, Chip Erase, Write Status
Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at
a byte boundary, otherwise the instruction is rejected, and is not executed. That is
/CS must drive high when the number of clock pulses after /CS being driven low is an exact multiple of
eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not
be reset.
Table8. Instruction Set Table
Instruction Name
Write Enable
Volatile SR Write
Enable
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
06h
50h
04h
05h
Write Disable
Read Status
Register-1
(S7-S0)(2)
S7-S0
(continuous)
Write Status
Register(4)
01h
S15-S8
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Instruction
Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Read Status
Register-2
Active Status
Interrupt
(continuous
)
(S15-S8)(2)
35h
25h
C7h/60h
75h
Chip Erase
Program/Erase
Suspend
Program/Erase
Resume
7Ah
B9h
ABh
ABH
Deep
Power-down
Release
(ID7-ID0)(2
Dummy
Dummy
Dummy
Dummy
Dummy
00/01h
(continuous)
(continuous)
)
Power-down / ID
Release
Power-down
(ID7-ID0)(
(MF7-MF0
)/
Manufacturer/De
vice ID
/
2) (MF7-M
90h
F0)(2)
(ID7-ID0)
(ID7-ID0)(
(MF7-MF0 (ID15-ID8
Read JEDEC ID
9Fh
4Bh
(continuous)
(ID127-ID0)
2)
)
)
Read Unique ID
Number
Dummy
Dummy
Dummy
A7-A0
Dummy
Dummy
Enable Reset
Reset Device
Read Serial
Flash
66h
99h
5Ah
A23-A16
A15-A8
(D7-D0)
Discoverable
Parameter
Normal Read
Data
(continuous)
(Next
Byte)
03h
0Bh
3Bh
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
Dummy
Dummy
(continuous)
(continuous)
(continuous)
Fast Read
(D7-D0)
Dual Output Fast
read
(D7-D0)(7)
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Instruction
Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Dual I/O Fast
A7-A0
M7-M0(6)
BBh
A23-A8(6)
(D7-D0)
(continuous)
read
Quad Output
Fast read
Quad I/O Fast
read
6Bh
EBh
02h
A2h
A23-A16
A15-A8
Dummy
A15-A8
A15-A8
A7-A0
Dummy
(D7-D0)(9)
(continuous)
(continuous)
A23-A0
M7-M0(8)
(D7-D0)(10)
A7-A0
(Next
Byte)
(Next
Byte)
(Next
Byte)
(D7-D0)(3)
(D7-D0)(3)
(D7-D0)(3)
Page Program
A23-A16
A23-A16
Dual Page
Program
A7-A0
Quad Page
Program
32h
81h/DBh
20h
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Page Erase
Sector Erase
(4KB)
Block Erase
(32KB)
52h
D8h
44h
42h
48h
77h
92h
94h
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(5)
Block Erase
(64KB)
Erase Security
Registers
A23-A16(5) A15-A8(5) A7-A0
A23-A16(5) A15-A8(5) A7-A0
A23-A16(5) A15-A8(5) A7-A0
W6-W4
Program Security
Registers
(5)
(5)
D7-D0
Next Byte
D7-D0
Read Security
Registers
Dummy
Set Burst With
Wrap
(6)
A7-A0
Mftr./Device ID
Dual I/O
(M7-M0)
(D7-D0)
A23-A8(6)
(continuous)
(continuous)
M7-M0
(M7-M0)
(D7-D0)(10)
Mftr./Device ID
Quad I/O
A23-A0
M7-M0(8)
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Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate
data output from the device.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the
instruction.
3. At least one byte of data input is required for Page Program, Dual Page Program, Quad Page
Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data
are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously
sent data.
4. Write Status Register (01h) can also be used to write Status Register-1&2, see section Write Status
Register (01h).
5. Security Register Address:
Security Register 1
Security Register 2
Security Register 3
A23-16 = 00h
A23-16 = 00h
A23-16 = 00h
A15-9 = 0001000
A15-9 = 0010000
A15-9 = 0011000
A8-0 = byte address
A8-0 = byte address
A8-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
9. Quad SPI data output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
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Configuration and Status Instructions
Write Enable (06H)
The Write Enable instruction (Figure 2.) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Dual Page Program, Quad Page Program, Page
Erase, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security
Registers instruction. The Write Enable instruction is entered by driving
/CS low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge of SCLK, and then
driving /CS high.
Figure2. Write Enable Instruction for SPI Mode
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in Status Register can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register
non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile
Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write
Enable for Volatile Status Register instruction (Figure 3. will not set the Write Enable Latch (WEL) bit, it is
only valid for the Write Status Register instruction to change the volatile Status Register bit values.
Figure3. Write Enable for Volatile Status Register Instruction for SPI Mode
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Write Disable (04h)
The Write Disable instruction (Figure 4.) resets the Write Enable Latch (WEL) bit in the Status Register to 0.
The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the SI pin
and then driving /CS high.
Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status
Register, Erase/Program Security Registers, Page Program, Dual Page Program, Quad Page Program,
Page Erase, Sector Erase, Block Erase, Chip Erase and Reset instructions.
Figure 4. Write Disable Instruction for SPI Mode
Read Status Register-1 (05h), Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register -2
into the SI pin on the rising edge of SCLK. The status register bits are then shifted out on the SO pin at the
falling edge of SCLK with most significant bit (MSB) first as shown in Figure 5., Refer to section Status
Register for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 5. The instruction is completed by driving /CS high.
Figure5. Read Status Register Instruction
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Active Status Interrupt (25h)
To simplify the readout of the WIP bit, the Active Status Interrupt Instruction (25h) may be used. It is then
not necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If
the SO line is connected to an interrupt line on the host controller, the host controller may be in sleep mode
until the SO line indicates that the device is ready for the next Instruction
The WIP bit can be read at any time, including during an internally self-timed program or erase operation.
To enable the Active Status Interrupt instruction, the /CS pin must first be asserted and the instruction code
of 25h must be clocked into the device. The value of the SI line after the instruction code being clocked in is
of no significance to the operation.
The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the
/CS pin remains asserted. Additional clocks on the SCK pin are not required. That is, whether the additional
clock on the SCK pin exists is independent of the correct output of the value of WIP. (Figure 6. shows a
case where additional clocks exist). If the WIP bit changes from 1 to 0 while the /CS pin is asserted, the SO
line will change from 1 to 0. (The WIP bit cannot change from 0 to 1 during an operation, so if the SO line
already is 0, it will not change.)
De-asserting the /CS pin will terminate the Active Status Interrupt operation and put the SO pin into a
high-impedance state.
The sequence of issuing ASI instruction is: /CS goes low→ sending ASI instruction code→ WIP data out on
SO
Figure 6. Active Status Interrupt Instruction
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Write Status Register (01h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register
bits include: SRP0, BP[4:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register- 2. All other
Status Register bit locations are read-only and will not be affected by the Write Status Register instruction.
LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0.
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) or Write Enable For Volatile SR instruction must
previously have been executed After the Write Enable (WREN) instruction has been decoded and executed,
the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S15(SUS1), S10(SUS2), S1(WEL) and S0(WIP) of
the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched
in. If not, the Write Status Register (WRSR) command is not executed. If
/CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As
soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL)
is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table5 and Table6.The Write Status Register (WRSR) instruction also allows the user to set or reset the
Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The
Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in
the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware
Protected Mode is entered.
The sequence of issuing WRSR instruction is: /CS goes low→ sending WRSR instruction code→ Status
Register data on SI→/CS goes high.
The /CS must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be
rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip
Select (/CS) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status
Register cycle is in progress. The WIP is set 1 during the tW timing, and is set 0 when Write Status Register
Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Figure 7. Write Status Register Instruction
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Read Instructions
Normal Read Data (03H)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the
SCLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the SO pin at the falling edge of SCLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as the
clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 8. If a Read Data instruction is issued while an
Erase, Program or other Write cycle is in progress (WIP=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock frequency up to to a maximum of fR
(see AC Electrical Characteristics).
The Normal Read Data (03h) instruction is only supported in Standard SPI mode.
Figure 8. Read Data Instruction
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Fast Read (0BH)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of fC (see AC Electrical Characteristics). In standard SPI mode, this is accomplished by
adding eight “dummy” clocks after the 24-bit address as shown in Figure 9. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks the data
value on the SO pin is a “don’t care”.
Figure 9. Fast Read Instruction
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; SI and SO. This allows data to be transferred at twice the rate of standard
SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to
RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of fC (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24-bit address as shown in Figure 10. The dummy clocks allow the device's internal circuits
additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”.
However, the SI pin should be high-impedance prior to the falling edge of the first data out clock.
Figure10. Fast Read Dual Output Instruction
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Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on two pins, SI, SO, /WP, and /HOLD. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast
Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of fC (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as
shown in Figure 11. The dummy clocks allow the device's internal circuits additional time for setting up the
initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
Figure11. Fast Read Quad Output Instruction
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Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins,
SI and SO. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the
Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution
(XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can operate at the highest possible frequency of fC (see AC Electrical
Characteristics). The Fast Read Dual I/O instruction can further reduce instruction overhead through
setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23- 0), as shown in Figure 12.
The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure13. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFh on SI for the next instruction (16 clocks), to ensure M4 = 1 and return the
device to normal operation.
Figure12. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4≠10)
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Figure13. Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0))
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through two pins SI, SO, /WP and /HOLD and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can operate at the highest possible frequency of fC (see AC Electrical
Characteristics). The Fast Read Quad I/O instruction can further reduce instruction overhead through
setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14.
The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in Figure 15. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFh on SI for the next instruction (8 clocks), to ensure M4 = 1 and return the
device to normal operation.
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Figure14. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10)
Figure15. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10 )
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either
enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is
enabled, the data being accessed can be limited to an 8, 16, 32 or 64-byte section of a 256-byte page. The
output data starts at the initial address specified in the instruction, once it reaches the ending boundary of
the 8/16/32/64- byte section, the output will wrap around to the beginning boundary automatically until /CS
is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around
section within a page. Refer to Set Burst with Wrap (77h) for detail descriptions.
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Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O (EBh)”,
“instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure16. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
W4 =1 (DEFAULT)
W6
W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O (EBh)”,
instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should
be issued to set W4 = 1. The default value of W4 upon power on or after a software reset is 1.
Figure16. Set Burst with Wrap Instruction
ID and Power Instructions
Deep Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in DC
Characteristics.)The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h”
as shown in Figure 17.
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The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power- down state will entered within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down /
Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for
securing maximum write protection.
The device always powers-up in the normal operation with the standby current of ICC1
Figure17. Deep Power-down Instruction
Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power- down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in Figure 18.Release from power-down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal
operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time
duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first. The Device ID
value for the ACE25QC200GL is listed in Manufacturer and Device Identification table. The Device ID can
be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is the
same as previously described, and shown in Figure 18, except that after /CS is driven high it must remain
high for a time duration of tRES2 (See AC Characteristics) . After this time duration the device will resume
normal operation and other instructions will be accepted. If the Release from Power- down / Device ID
instruction is issued while an Erase, Program or Write cycle is in process (when WIP equals 1) the
instruction is ignored and will not have any effects on the current cycle.
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Figure18. Release Power-down Instruction
Figure19. Release Power-down / Device ID Instruction
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID
instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer / Device ID instruction can operate at the highest possible frequency of fC (see AC
Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction
code “90h” followed by a 24-bit address (A23-A0). After which, the Manufacturer ID for (68h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in
Figure20. The Device ID values for the ACE25QC200GL are listed in Manufacturer and Device
Identification table. The address A23-A1 is an unrelated item and has no effect on the result of the
instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then followed by
the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then followed by
the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving /CS high.
Figure20. Read Manufacturer / Device ID Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer
/ Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction can operate at the highest possible frequency of fC
(see AC Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “92h” followed by a 24-bit address (A23-A0) and four clock dummy cycles, but with the
capability to input the Address bits two bits per clock. After which, the Manufacturer ID for (68h) and the
Device ID are shifted out 2 bits per clock on the falling edge of SCLK with most significant bits (MSB) first
as shown in Figure21. The Device ID values for the ACE25QC200GL are listed in Manufacturer and Device
Identification table. The address A23-A1 and M7-M0 is an unrelated item and has no effect on the result of
the instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then
followed by the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then
followed by the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from
one to the other. The instruction is completed by driving /CS high.
Figure21. Read Manufacturer / Device ID Dual I/O Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at
4x speed.
The Read Manufacturer / Device ID Quad I/O instruction can operate at the highest possible frequency of
fC (see AC Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “94h” followed by a 24-bit address (A23-A0) and six clock dummy cycles, but with the
capability to input the Address bits four bits per clock. After which, the Manufacturer ID for (68h) and the
Device ID are shifted out four bits per clock on the falling edge of SCLK with most significant bit (MSB) first
as shown in Figure22. The Device ID values for the ACE25QC200GL are listed in Manufacturer and Device
Identification table. The address A23-A1 and M7-M0 is an unrelated item and has no effect on the result of
the instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then
followed by the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then
followed by the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from
one to the other. The instruction is completed by driving /CS high.
Figure22. Read Manufacturer / Device ID Quad I/O Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Read JEDEC ID (9Fh)
The Read JEDEC ID instruction can operate at the highest possible frequency of fC (see AC Electrical
Characteristics). For compatibility reasons, the ACE25QC200GL provides several instructions to
electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the
JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated
by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID
byte for (68h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted
out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. For memory type
and capacity values refer to Manufacturer and Device Identification table.
Figure23. Read JEDEC ID Instruction
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction can operate at the highest possible frequency of fC (see AC
Electrical Characteristics).The Read Unique ID Number instruction accesses a factory-set read-only
128-bit number that is unique to each ACE25QC200GL device. The ID number can be used in conjunction
with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction
is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of
dummy clocks. After which, the 128-bit ID is shifted out on the falling edge of SCLK as shown in Figure24.
VER 1.1
34
Figure24. Read Unique ID Sequence Diagram
ACE25QC200GL
2M BIT SPI NOR FLASH
Program / Erase and Security Instructions
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the SI pin. The /CS pin must be held low for the entire length of the instruction while data
is being sent to the device. The Page Program instruction sequence is shown in Figure25.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data
bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are
sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Page Program instruction is not executed.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tPP (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page Program cycle
and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After
the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.
The Page Program instruction will not be executed if the addressed page is protected by the Block Protect
(BP4, BP3, BP2, BP1, and BP0) bits
Figure25. Page Program Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Dual Page Program (A2h)
The Dual Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using two pins: SI, SO. The Dual Page Program can improve performance for
PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed
will not realize much benefit for the Dual Page Program instruction since the inherent page program time is
much longer than the time it take to clock-in the data.
A Write Enable instruction must be executed before the device will accept the Dual Page Program
instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “A2h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins.
The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.
All other functions of Dual input Page Program are identical to standard Page Program. The Dual Page
Program instruction sequence is shown in Figure26.
Figure26. Dual Page Program Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Quad Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using two pins: SI, SO, /WP, and /HOLD. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much longer than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must
be held low for the entire length of the instruction while data is being sent to the device. All other functions
of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction
sequence is shown in Figure27.
Figure27. Quad Input Page Program Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Page Erase (81h/DBh)
The Page Erase (PE) instruction is for erasing the data of the chosen Page to be "1". A Write Enable
(WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase
(PE). To perform a Page Erase with the standard page size (256 bytes), an instruction code of 81h or DBh
must be clocked into the device followed by three address bytes comprised of 2 page address bytes that
specify the page in the main memory to be erased. And A7-A0 is an unrelated item.
The sequence of issuing PE instruction is: /CS goes low → sending PE instruction code→ 3-byte address
on SI → /CS goes high.
Figure28. Page Erase Instruction
Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “20h” followed a 24-bit sector address. And the address A11-A0 is an unrelated
item and has no effect on the result of the instruction. The Sector Erase instruction sequence is shown in
Figure29.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle
is in progress, the Read Status Register instruction may still be accessed for checking the status of the WIP
bit. The WIP bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be
executed if the addressed page is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits.
Figure29. Sector Erase Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
32KB Block Erase (52h)
The 32KB Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the 32KB Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin
low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). And the address
A14-A0 is an unrelated item and has no effect on the result of the instruction. The Block Erase instruction
sequence is shown in Figure30.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
32KB Block Erase instruction will not be executed. After /CS is driven high, the self-timed 32KB Block
Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the 32KB
Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking
the status of the WIP bit. The WIP bit is a 1 during the 32KB Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the 32KB Block Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 32KB Block
Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits.
Figure30. 32KB Block Erase Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
64KB Block Erase (D8h)
The 64KB Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the 64KB Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin
low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). And the address
A15-A0 is an unrelated item and has no effect on the result of the instruction. The 64KB Block Erase
instruction sequence is shown in Figure31.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
64KB Block Erase instruction will not be executed. After /CS is driven high, the self- timed 64KB Block
Erase instruction will commence for a time duration of tBE2 (See AC Characteristics) . While the 64KB
Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking
the status of the WIP bit. The WIP bit is a 1 during the 64KB Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the 64KB Block Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 64KB Block
Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits.
Figure31. 64KB Block Erase Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure32.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is
a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other
instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits.
Figure32. Chip Erase Instruction for SPI Mode
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ACE25QC200GL
2M BIT SPI NOR FLASH
Program/Erase Suspend (75h)
The Program/Erase Suspend instruction “75h”, allows the system to interrupt a Page Program or a
Page/Sector/32K/64K Block Erase operation and then read data from any other sector or block. After the
program or erase operation has entered the suspended state, the memory array can be read except for the
page being programmed or the sector or block being erased. And after the erase operation has entered the
suspended state, the memory array can be programed except for the page being erased. Write status
register operation can't be suspended. Erase/Program security registers operation can't be suspended.
The Program/Erase Suspend instruction sequence is shown in Figure33.
Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended operation
Page Program
Readable Region Of Memory Array
All but the Page being programmed
All but the Page being programmed
All but the Page being programmed
All but the Page being Erased
Dual Page Program
Quad Page Program
Page Erase
Sector Erase(4KB)
Block Erase(32KB)
Block Erase(64KB)
All but the 4KB Sector being Erased
All but the 32KB Block being Erased
All but the 64KB Block being Erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the
Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after which the device is
ready to accept one of the commands listed in "Table Acceptable Commands During Program/Erase
Suspend after tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings.
"Table Acceptable instructions During Suspend (tPSL/tESL not required)" lists the Instructions for which the
tPSL and tESL latencies do not apply. For example, “05h”, “48h”, “66h” and “99h” can be issued at any time
after the Suspend instruction.
Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2
(Program Suspend Bit) sets to “1” when a program instruction is suspended. The SUS1 (Erase Suspend Bit)
sets to “1” when an erase operation is suspended. The SUS2 or SUS1 clears to “0” when the program or
erase instruction is resumed.
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ACE25QC200GL
2M BIT SPI NOR FLASH
Acceptable instructions During Program/Erase Suspend after tPSL/tESL
Suspend Type
Instruction Name
Instruction code
Program Suspend
Erase Suspend
Read Data
Fast Read
03H
0BH
3BH
6BH
BBH
EBH
5AH
9FH
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Dual Output Fast Read
Dual I/O Fast Read
Quad Output Fast Read
Quad I/O Fast Read
Read SFDP
Read JEDEC ID
Mftr./Device ID
90H
Mftr./Device ID Dual IO
Mftr./Device ID Quad IO
Read Securty Registers
Set Burst with Wrap
Write Enable
92H
94H
48H
77H
06H
Program/Erase Resume
Page Program
7AH
02H
*
Dual Page Program
Quad Page Program
Page Erase
A2H
32H
81H/DBH
20H
Sector Erase
32KB Block Erase
64KB Block Erase
Chip Erase
52H
D8H
C7H/60H
44H
Erase Security Registers
Program Security Registers
Write Status Register
42H
01H
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ACE25QC200GL
2M BIT SPI NOR FLASH
Acceptable Commands During Suspend (tPSL/tESL not required)
Suspend Type
Instruction Name
Instruction code
Program Suspend
Erase Suspend
Write Disable
Read Status Register-1
Read Status Register-2
Read Security Register
Active Status Interrupt
Release Powen-down/Device ID
Enable Reset
04H
05H
35H
48H
25H
ABH
66H
99H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Reset Device
tPSL : Program Suspend Latency; tESL : Erase Suspend Latency.
Figure33. Program/Erase Suspend Instruction
Program/Erase Resume (7Ah)
The Program/Erase Resume instruction “7Ah” must be written to resume the Program or Page / Sector
/Block Erase operation after the Program/Erase Suspend. The Program/Erase Resume instruction “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals
to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1
within 200ns and the Page, Sector or 32/64KBlock will complete the program/erase operation. If the SUS
bit equals to 0 or the WIP bit equals to 1, the Program/Erase Resume instruction “7Ah” will be ignored by
the device. The Program/Erase Resume instruction sequence is shown in Figure34.
Program/Erase Resume instruction is ignored if the previous Program/Erase Suspend operation was
interrupted by unexpected power off. It is also required that a subsequent Program/Erase Suspend
instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction.
VER 1.1
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ACE25QC200GL
2M BIT SPI NOR FLASH
Figure34. Program/Erase Resume Instruction
Erase Security Registers (44h)
The ACE25QC200GL offers three 512-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
Address
A23-16
00H
A15-12
0001
A11-8
0000
0000
0000
A8-0
Security Registers 1
Security Registers 2
Security Registers 3
Don’t Care
Don’t Care
Don’t Care
00H
0010
00H
0011
The Erase Security Register instruction sequence is shown in Figure35. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during
the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register
(LB3-1 corresponds to S13-11) will be permanently locked, Erase Security Register instruction to that
register will be ignored (Refer to section LB3/LB2/LB1 for detail descriptions).
VER 1.1
45
Figure35. Erase Security Registers Instruction
ACE25QC200GL
2M BIT SPI NOR FLASH
Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 512 bytes of security register data to be programmed by two times (one time program 256 bytes) at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is
initiated by driving the /CS pin low then shifting the instruction code “42h” followed by a 24- bit address
(A23-A0) and at least one data byte, into the SI pin. The /CS pin must be held low for the entire length of
the instruction while data is being sent to the device.
Address
A23-16
00H
A15-12
0001
A11-9
0000
0000
0000
A8-0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
0010
00H
0011
The Program Security Register instruction sequence is shown in Figure36. The Security Register Lock Bits
(LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to
1, the corresponding security register will be permanently locked, Program Security Register instruction to
that register will be ignored.
Figure36. Program Security Registers Instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight
“dummy” clocks into the SI pin. The code and address bits are latched on the rising edge of the SCLK pin.
After the address is received, the data byte of the addressed memory location will be shifted out on the SO
pin at the falling edge of SCLK with most significant bit (MSB) first. The byte address is automatically
incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches
the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and
continue to increment. The instruction is completed by driving /CS high. The Read Security Register
instruction sequence is shown in Figure37. If a Read Security Register instruction is issued while an Erase,
Program or Write cycle is in progress (WIP=1) the instruction is ignored and will not have any effects on the
current cycle. The Read Security Register instruction allows clock frequency up to to a maximum of fC (see
AC Electrical Characteristics).
Address
A23-16
00H
A15-12
0001
A11-9
0000
0000
0000
A8-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
0010
00H
0011
Figure37. Read Security Registers instruction
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ACE25QC200GL
2M BIT SPI NOR FLASH
Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the ACE25QC200GL provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any
on-going internal operations will be terminated and the device will return to its default power-on state and
lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status,
Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) , Wrap Bit setting (W6-W4).
To avoid accidental reset, both instructions must be issued in sequence. Any other instructions other than
“Reset (99h)” after the “Enable Reset (66h)” instruction will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
instruction is accepted by the device, the device will take tRST to reset. During this period, no instruction
will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset instruction sequence is accepted by the device. It is recommended to check the WIP bit and
the SUS bit in Status Register before issuing the Reset instruction sequence.
Figure38. Enable Reset and Reset instruction Sequence
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ACE25QC200GL
2M BIT SPI NOR FLASH
Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables.
These parameter tables can be interrogated by host system software to enable adjustments needed to
accommodate divergent features from multiple vendors. The concept is similar to the one found in the
Introduction of JEDEC Standard, JESD68 on CFI.
SFDP is a JEDEC Standard, JESD216B.
Figure39. Read Serial Flash Discoverable Parameter instruction Sequence Diagram
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ACE25QC200GL
2M BIT SPI NOR FLASH
Table 9. Signature and Parameter Identification Data Values
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
53H
46H
44H
50H
Data
53H
46H
44H
50H
00H
01H
02H
03H
07:00
15:08
23:16
31:24:
SFDP Signature
Fixed:50444653H
SFDP Minor Revision
Number
SFDP Major Revision
Number
Number of
Parameters Headers
Start from 00H
Start from 01H
Start from 00H
04H
05H
06H
07H
08H
07:00
15:08
23:16
31:24
07:00
00H
01H
01 H
FFH
00H
00H
01H
01 H
FFH
00H
Contains 0xFFH and can
never be changed
00H: It indicates a JEDEC
Unused
ID number (JEDEC)
specified header
Parameter Table
Minor Revision
Number
Parameter Table
Major Revision
Number
Parameter Table
Length (in double
word)
Start from 0x00H
Start from 0x01H
09H
0AH
0BH
15:08
23:16
31:24
00H
01H
09H
00H
01H
09H
How many DWORDs in the
Parameter table
0CH
0DH
0EH
07:00
15:08
23:16
30H
00H
00H
30H
00H
00H
Parameter Table
Pointer (PTP)
First address of JEDEC Flash
Parameter table
Contains 0xFFH and can
never be changed
Unused
0FH
10H
31:24
07:00
FFH
68H
FFH
68H
ID Number LSB
(Manufacturer ID)
Parameter Table
Minor Revision
Number
Parameter Table
Major Revision
Number
It is indicates Device
manufacturer ID
Start from 0x00H
Start from 0x01H
11 H
12H
13H
15:08
23:16
31:24
00H
01H
03H
00H
01H
03H
Parameter Table
Length (in double
word)
How many DWORDs in the
Parameter table
14H
15H
16H
07:00
15:08
23:16
60H
00H
00H
60H
00H
00H
Parameter Table
Pointer (PTP)
First address of Device Flash
Parameter table
Contains 0xFFH and can
never be changed
Unused
17H
31:24
FFH
FFH
VER 1.1
50
ACE25QC200GL
2M BIT SPI NOR FLASH
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
Data
00: Reserved; 01: 4KB erase;
10: Reserved; 11: not support
4KB erase
Block/Sector Erase
Size
01:00
01b
Write Granularity
0: 1Byte, 1: 64Byte or larger
02
0
1b
0b
Write Enable
Instruction
Requested for Writing
to Volatile Status
Registers
0: Nonvolatile status bit 1:
Volatile status bit (BP status
register bit)
30H
E5H
0: Use 50H Instruction code,
1: Use 06H Instruction code,
Note: If target flash status
register is Nonvolatile, then
bits 3 and 4 must be set to
00b.
Write Enable
Instruction code
Select for Writing to
Volatile Status
Registers
04
0b
Contains 111b and can never
Unused
07:05
111b
be changed
4KB Erase Instruction
code
31H
32H
15:08
16
20H
1b
20H
F1H
(1 -1 -2) Fast Read
0=Not support, 1=Support
Address Bytes
Number used in
addressing flash
array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
00b
Double Transfer Rate
0=Not support, 1=Support
19
0b
(DTR) clocking
(1 -2-2) Fast Read
(1 -4-4) Fast Read
(1 -1 -4) Fast Read
Unused
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
22
1b
23
1b
Unused
33H
31:24
FFH
FFH
44H
Flash Memory
Density
(1 -4-4) Fast Read
Number of Wait
states
37H:34H
31:00
04:00
003FFFFFH
00000b: Wait states (Dummy
Clocks) not support
00100b
38H
(1 -4-4) Fast Read
000b:Mode Bits not support
07:05
15:08
010b
EBH
Number of Mode Bits
(1 -4-4) Fast Read
Instruction code
(1 -1 -4) Fast Read
Number of Wait
states
39H
3AH
EBH
08H
00000b: Wait states (Dummy
Clocks) not support
20:16
01000b
VER 1.1
51
ACE25QC200GL
2M BIT SPI NOR FLASH
(1 -1 -4) Fast Read
Number of Mode Bits
(1 -1 -4) Fast Read
Instruction code
(1 -1 -2) Fast Read
Number of Wait
000b:Mode Bits not support
23:21
31:24
000b
3BH
3CH
3DH
3EH
3FH
6BH
6BH
08H
3BH
42H
BBH
00000b: Wait states (Dummy
Clocks) not support
04:00
01000b
states
(1 -1 -2) Fast Read
Number of Mode Bits
(1 -1 -2) Fast Read
Instruction code
(1 -2-2) Fast Read
Number of Wait
states
(1 -2-2) Fast Read
Number of Mode Bits
(1 -2-2) Fast Read
Instruction code
000b: Mode Bits not support
07:05
15:08
000b
3BH
0000b: Wait states (Dummy
Clocks) not support
20:16
00000b
000b: Mode Bits not support
23:21
31:24
010b
BBH
(2-2-2) Fast Read
Unused
0=not support 1=support
0=not support 1=support
00
0b
111b
0b
03:01
04
40H
FEH
(4-4-4) Fast Read
Unused
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read
Number of Wait
states
(2-2-2) Fast Read
Number of Mode Bits
(2-2-2) Fast Read
Instruction code
0 0000b: Wait states (Dummy
Clocks) not support
20:16
23:21
00000b
000b
46H
00H
000b: Mode Bits not support
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read
Number of Wait
states
0 0000b: Wait states (Dummy
Clocks) not support
20:16
00000b
4AH
44H
(4-4-4) Fast Read
Number of Mode Bits
(4-4-4) Fast Read
Instruction code
000b: Mode Bits not support
23:21
31:24
000b
FFH
4BH
4CH
4DH
4EH
4FH
EBH
0CH
20H
0FH
52H
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 1 Size
07:00
15:08
23:16
31:24
0CH
20H
0FH
52H
Sector Type 1 erase
Instruction code
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 2 Size
Sector Type 2 erase
Instruction code
VER 1.1
52
ACE25QC200GL
2M BIT SPI NOR FLASH
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 3 Size
50H
51H
52H
53H
07:00
15:08
23:16
31:24
10H
D8H
08H
81H
10H
D8H
00H
FFH
Sector Type 3 erase
Instruction code
Sector/block size=2^N bytes
0x00b: this sector type don’t
exist
Sector Type 4 Size
Sector Type 4 erase
Instruction code
Table11. Parameter Table (1): Device Flash Parameter Tables
Add(H)
DW
Add
(Bit)
Comment
Description
Data
Data
(Byte)
Vcc Supply Maximum 2000H=2.000V,2700H=2.700
61H:60H
15:00
2000H
1650H
2000H
Voltage
V,3600H=3.600V
1650H=1.650V,2250H=2.250
V,2350H=2.350V,2700H=2.7
00V
Vcc Supply Minimum
Voltage
63H:62H
31:16
1650H
HW Reset# pin
HW Hold# pin
0=not support 1=support
0=not support 1=support
00
01
0b
1b
Deep Power Down
Mode
0=not support 1=support
02
03
1b
1b
SW Reset
0=not support 1=support
Should be issue Reset
Enable(66H)before Reset
cmd.
SW Reset Instruction
code
11:04
12
99H
1b
65H:64H
F99EH
Program
Suspend/Resume
Erase
0=not support 1=support
0=not support 1=support
13
14
15
1b
1b
1b
Suspend/Resume
Unused
Wrap-Around Read
mode
0=not support 1=support
Wrap-Around Read
mode Instruction code
66H
67H
23:16
31:24
77H
64H
77H
64H
08H:support 8B wrap-around
read16H:8B&16B32H:8B&16
B&32B64H:8B&16B&32B&64
B
Wrap-Around Read
data length
VER 1.1
53
ACE25QC200GL
2M BIT SPI NOR FLASH
Individual block lock
bit(Volatile/Nonvolatil
e)
Individual block lock
Instruction code
Individual block lock
Volatile protect bit
default protect status
0=Volatile 1=Nonvolatile
0=protect 1=unprotect
01
09:02
10
0b
FFH
0b
CBFCH
6BH:68H
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
1b
15:14
31:16
11b
Unused
FFFFH
FFFFH
VER 1.1
54
ACE25QC200GL
2M BIT SPI NOR FLASH
Electrical Characteristics
Absolute Maximum Ratings
Parameters
Symbol
VCC
Conditions
Range
Unit
Supply Voltage
–0.6 to VCC+0.6
–0.6 to VCC+0.6
V
V
Voltage Applied to Any Pin
VIO
Relative to Ground
<20nS Transient Relative to
Ground
Transient Voltage on any Pin
VIOT
–1.0Vto VCC+1.0V
V
Storage Temperature
Lead Temperature
TSTG
TLEAD
VESD
–55 to 150
See Note (2)
–2000 to 2000
℃
℃
V
Electrostatic Discharge Voltage
Notes:
Human Body Model(3)
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond
absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the
European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms)
Operating Ranges
SPEC
Parameter
Symbol
Conditions
Unit
Min
Max
FR = 108MHz, fR =
50MHz
Supply Voltage
VCC
1.65
2.0
V
Ambient Temperature
Operating
TA
Industrial
-40
+85
℃
Power-up Timing
Symbol
Parameter
VCC(min) To /CS Low
Min
300
Max
Unit
us
tVSL
Notes: These parameters are characterized only.
VER 1.1
55
Figure40. Power-up Timing
ACE25QC200GL
2M BIT SPI NOR FLASH
DC Electrical Characteristics
Symbol
Parameter
Condition
Min.
Typ
Max.
Unit.
CIN(1)
Cout(1)
ILI
Input Capacitance
Output Capacitance
VIN = 0V(1)
VOUT = 0V(1)
6
8
pF
pF
µA
µA
Input Leakage Current
Output Leakage Current
All inputs at CMOS level
All inputs at CMOS level
±2
±2
ILO
/CS=VCC, VIN=VCC or
ICC1
ICC2
Standby Current
9
µA
µA
VSS
/CS=VCC, VIN=VCC or
VSS
Power-Down Current
0.8
1.0
mA
mA
mA
mA
mA
mA
V
F=1MHz;IOUT=0mA
F=33MHz;IOUT=0mA
F=50MHz;IOUT=0mA
F=85MHz;IOUT=0mA
/CS=VCC WIP=1
0.5
1.0
1.0
1.0
1.5
1.5
1.0
2.0
ICC3
ICC4
Normal read current (03h)
Read Current(0Bh)
2.0
2.0
ICC5
ICC6
VIL
Program Current
Erase Current
3.0
/CS=VCC WIP=1
3.0
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VCC*0.2
VIH
VCC*0.8
VCC-0.2
V
VOL
VOH
IOL =100µA
0.2
V
IOH =-100µA
V
Notes: Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V.
AC Measurement Conditions
Symbol
Parameter
Min
Tpy
Max
Unit
Cin
Cout
CL
Input Capacitance
Output Capacitance
6
6
pF
pF
pF
ns
V
Load Capacitance
30
5
TR, TF
VIN
Input Rise And Fall time
Input Pause Voltage
0.2VCC to 0.8VCC
0.5VCC
IN
Input Timing Reference Voltage
Output Timing Reference Voltage
V
OUT
0.5VCC
V
VER 1.1
56
Figure41.
AC Measurement I/O Waveform
ACE25QC200GL
2M BIT SPI NOR FLASH
AC Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit.
fR
Clock frequency for Normal Read Data instruction
Clock frequency for Read instruction except Normal
Read Data instruction (05h,35h,0Bh,3Bh, 6Bh,BBh,
EBh,90h,92h,94h,9Fh,4Bh,48h,5Ah)
33
MHz
fc, fc1
85
MHz
tCLH,
tCLL(1)
Clock High, Low Time
5.5
ns
tCLCH(2)
tCHCL(2)
Clock Rise Time peak to peak
0.1
0.1
5
V/ns
V/ns
ns
Clock Fall Time peak to peak
tSLCH, tCSS
tCHSL
/CS Active Setup Time relative to CLK
/CS Not Active Hold Time relative to CLK
Data In Setup Time
5
ns
tDVCH, tDSU
tCHDX, tDH
tSHQZ(2), ,tDIS
tCHSH, tCSS
tSHCH
2
ns
Data In Hold Time
3
ns
Output Disable Time
6
7
ns
/CS Active Hold Time relative to CLK
/CS Not Active Setup Time relative to CLK
Clock Low to Output Valid
5
5
ns
ns
tCLQV1, tV1
ns
/CS Deselect Time from read to next Read
/CS Deselect Time from Write, Erase, Program TO
Read status Register
15
30
ns
tSHSL, tCSH
ns
Clock Low to Output Valid loading 30pF
Clock Low to Output Valid loading 15pF
Output Hold Time
7
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
tCLQV, tV
tCLQX, tHO
tHLCH
0
5
5
5
5
/HOLD Active Setup Time relative to CLK
/HOLD Active Hold Time relative to CLK
/HOLD Not Active Setup Time relative to CLK
/HOLD Not Active Hold Time relative to CLK
/HOLD to Output Low-Z
tCHHH
tHHCH
tCHHL
tHHQX(2), tLZ
tHLQZ(2), tHZ
tWHSL(3)
tSHWL(3)
tDP(2)
6
6
/HOLD to Output High-Z
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Deep Power-down Mode
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
/CS High to next Instruction after Suspend
20
100
3
8
tRES1(2)
tRES2(2)
tSUS(2)
8
20
VER 1.1
57
ACE25QC200GL
2M BIT SPI NOR FLASH
Symbol
tRST(2)
tW
Parameter
/CS High to next Instruction after Reset
Write Status Register Cycle Time
Byte Program Time
Min.
Typ.
Max.
Unit.
µs
30
6.5
1
12
3
ms
ms
us
tBP1
tESL
tPSL
Erase Suspend Latency
30
30
Program Suspend Latency
Latency between Program Resume and next
Suspend
µs
tPRS
20
µs
tERS
tPP
Latency between Erase Resume and next Suspend
Page Program Time
20
2
us
ms
ms
ms
ms
ms
ms
3
tPE
Page Erase Time
8
12
12
12
12
12
tSE
Sector Erase Time (4KB)
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
8
tBE1
tBE2
tCE
8
8
8
Note:
1.
Clock high + Clock low must be less than or equal to 1/fC.
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
2.
3.
4.
Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V,
100% driver strength.
VER 1.1
58
ACE25QC200GL
2M BIT SPI NOR FLASH
Figure42. Serial Output Timing
Figure43. Serial Input Timing
Figure44. Hold Timing
Figure45. /WP Timing
VER 1.1
59
ACE25QC200GL
2M BIT SPI NOR FLASH
Packaging information
SOP-8
mm
Symbol
Min
Nom
Max
1.75
0.225
1.50
0.47
0.24
5.00
6.20
4.00
A
A1
A2
b
0.10
1.30
0.39
0.20
4.80
5.80
3.80
1.40
C
D
4.90
6.00
3.90
1.27
E
E1
e
L
0.50
0.41
0.80
L1
S
1.05
0.54
5
0.67
8
θ
VER 1.1
60
ACE25QC200GL
2M BIT SPI NOR FLASH
Packaging information
SOP-8L (208mil)
mm
Symbol
Min
Nom
Max
1.95
0.18
1.90
0.48
0.24
5.25
7.98
5.26
A
A1
A2
b
0.10
1.75
0.42
0.20
5.00
7.85
5.16
1.27
0.60
1.31
0.62
0.15
1.80
C
D
5.17
7.90
5.22
1.27
0.65
1.31
0.74
5
E
E1
e
L
0.70
1.41
0.88
8
L1
S
è
VER 1.1
61
ACE25QC200GL
2M BIT SPI NOR FLASH
Packaging information
TSSOP-8
mm
Symbol
Min
Nom
Max
1.20
0.15
1.05
0.49
0.28
0.25
0.17
0.14
3.10
6.60
4.50
A
A1
A2
A3
b
0.05
0.90
0.39
0.20
0.19
0.13
0.12
2.90
6.20
4.30
1.00
0.44
b1
c
0.22
c1
D
0.13
3.00
6.40
4.40
0.65
E
E1
e
L
0.45
0.75
8
L1
θ
1.00
VER 1.1
62
ACE25QC200GL
2M BIT SPI NOR FLASH
Packaging information
USON3*2-8
mm
Nom
0.50
Symbol
Min
0.45
0
Max
0.60
0.05
0.30
0.20
2.10
1.70
A
A1
b
0.02
0.20
0.10
1.90
1.50
0.25
c
0.15
D
2.00
D2
e
1.60
0.50BSC
1.50BSC
3.00
Nd
E
2.90
0.10
0.30
0.05
0.05
3.10
0.30
0.40
0.15
0.25
E2
L
0.20
0.35
L1
h
0.10
0.15
VER 1.1
63
ACE25QC200GL
2M BIT SPI NOR FLASH
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Technology Co., LTD. As
sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.1
64
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