ACE25AC200GLFMUH [ACE]
2M SPI NOR FLASH;型号: | ACE25AC200GLFMUH |
厂家: | ACE TECHNOLOGY CO., LTD. |
描述: | 2M SPI NOR FLASH |
文件: | 总23页 (文件大小:1162K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACE25AC200GL
2M SPI NOR FLASH
Description
The ACE25AC200GL is 2M-bit Serial flash supports the standard Serial Peripheral Interface (SPI).
SPI clock frequency of up to 40MHz is supported for fast read command.
Features
512K-bit Serial Flash
256 bytes per programmable page
Standard SPI
Standard SPI: SCLK, CS#, SI, SO,
High Speed Clock Frequency
40MHz for fast read with 30PF load
Program/Erase Speed
Page Program time: 2.0ms typical
Sector Erase time: 180ms typical
Block Erase time: 0.8s typical
Chip Erase time: 6s/3s typic
Flexible Architecture
Sector of 4K-byte
Block of 64k-byte
Low Power Consumption
10mA maximum active current
5uA maximum standby current
Single Power Supply Voltage: Full voltage range:1.65~1.95V
Minimum 100,000 Program/Erase Cycle
Absolute Maximum Ratings
Parameter
Value
-40 to 85
-65 to 150
200
Unit
℃
Ambient Operating Temperature
Storage Temperature
Output Short Circuit Current
Applied Input/Output Voltage
VCC
℃
mA
V
-0.5 to 4.0
-0.5 to 4.0
V
VER 1.2
1
ACE25AC200GL
2M SPI NOR FLASH
Packaging Type
SOP-8
SOP-8L
TSSOP-8
DIP-8
Pin Configurations
I/O
I
Pin Name
CS#
Functions
Chip Select Input
Data Output
Ground
SO
O
VSS
SI
I
I
Data Input
SCLK
VCC
Serial Clock Input
Power Supply
Ordering information
ACE25AC200GL XX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
TM: TSSOP-8
DP: DIP-8
VER 1.2
2
ACE25AC200GL
2M SPI NOR FLASH
Block Diagram
Uniform Block Sector Architecture
ACE25AC200GL 64K Bytes Block SectorArchitecture
Block
Sector
127
……
112
111
Address range
07F000H
……
07FFFFH
……
7
070000H
06F000H
……
070FFFH
06FFFFH
……
6
……
……
2
……
96
060000H
……
060FFFH
……
……
……
……
……
……
……
47
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
VER 1.2
3
ACE25AC200GL
2M SPI NOR FLASH
Device Operation
The ACE25AC200GL features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Data Protection
The ACE25AC200GL provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be
read but not change
SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the
SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Table 1.ACE25AC200GL Protected Area Sizes
Status bit
Protect level
Protect Block
BP2
0
BP1
0
BP0
0
0(none)
1 (1 block)
2 (2 blocks)
3 (4 blocks)
4 (8 blocks)
5 (All)
None
Block 7
Block 6-7
Block 4-7
All
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
All
1
1
0
6 (All)
All
1
1
1
7 (All)
All
VER 1.2
4
ACE25AC200GL
2M SPI NOR FLASH
Status Register
S7
S6
Reserved
S5
S4
S3
S2
S1
S0
SRWD
Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register
progress. When WIP bit sets 0, the device is not in program, erase or write status register.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1,
the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase command is accepted.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area
(as defined in Table1) becomes protected against Page Program (PP), Sector Erase (SE) and Block
Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block Protect (BP2,
BP1, BP0) bits are 1.
SRWD bit.
The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program (OTP) bit in the status
register that provide another software protection. Once it is set to 1, the Write Status Register (WRSR)
instruction is no longer accepted and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
SRWD
Status register
Memory
Status register can be written in (WEL bit is
0
set to "1") and the SRWD, BP2-BP0 bits can The protected area cannot be program or erase
be changed
The SRWD, BP2-BP0 of status register bits
The protected area cannot be program or erase
cannot be changed
1
VER 1.2
5
ACE25AC200GL
2M SPI NOR FLASH
Commands Description
All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code
must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges
of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on
the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be
driven high after the last bit of the command sequence has been shifted in. For the command of Read,
Fast Read, Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a
data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an
exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will
happen and WELwill not be reset.
Table2. Commands
Command Name
Write Enable
Byte1
06H
Byte2
Byte3
Byte4
Byte5
Byte6
n-Bytes
Write Disable
Read Status Register
Write Status Register
Read Data
04H
05H
(S7-S0)
(S7-S0)
(continuous)
(continuous)
01H
03H
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
(D7-D0)
(Next byte) (continuous)
Fast Read
0BH
02H
(D7-D0)
(continuous)
Page Program
Sector Erase
(Next byte)
20H
Block Erase
D8H
C7/60H
Chip Erase
Manufacturer/Device
ID
90H
9FH
dummy
dummy
00H
(MID7-MID0) (DID7-DID0) (continuous)
(continuous)
(JDID15-JDI (JDID7-JDID
Read Identification
(MID7-MID0)
D8)
0)
VER 1.2
6
ACE25AC200GL
2M SPI NOR FLASH
ID Definitions
Operation Code
M7-M0
0E
ID15-ID8
60
ID7-ID0
13
9FH
90H
0E
12
Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), and
Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command
sequence: CS# goes low→Send Write Enable command→CS# goes high.
Figure1. Write Enable Sequence Diagram
Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable
command sequence: CS# goes low Send Write Disable command CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector
Erase, Block Erase and Chip Erase commands.
Figure2. Write Disable Sequence Diagram
VER 1.2
7
ACE25AC200GL
2M SPI NOR FLASH
Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may
be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one
of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously.
Figure3. Read Status Register Sequence Diagram
Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After
the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) command has no effect on S6, S5, S1 and S0 of the Status Register.
CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status
Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect
(BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1.1 and 1.2. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP)
bit, the Write Status Register (WRSR) command allows the user to set the Status Register Write Disable
(SRWD) bit to 1. The Status Register Write Disable (SRWD) bit allow the device to be put in another
Software Protected Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is
not executed, and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Figure4. Write Status Register Sequence Diagram
VER 1.2
8
ACE25AC200GL
2M SPI NOR FLASH
Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address
after each byte of data is shifted out. Therefore, the whole memory can be read with a single Read Data
Bytes (READ) command. During an Erase, Program or Write cycle, Read Data Byte (READ) command
will be rejected without affecting the cycle in progress.
Figure5. Read Data Bytes Sequence Diagram
Read Data Bytes At Higher Speed (Fast Read)(0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed
by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency f , during the falling edge of SCLK. The first byte address can be at any location. The address
C
is automatically incremented to the next higher address after each byte of data is shifted out.
Figure6. Read Data Bytes at Higher Speed Sequence Diagram
VER 1.2
9
ACE25AC200GL
2M SPI NOR FLASH
Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the current page are programmed from the start
address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must
be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes
low sending Page Program command3-byte address on SI at least 1 byte data on SI
The command sequence is shown in Figure7. If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other bytes of the same page. CS# must be driven
high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP)
command is not executed.
CS# g
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated.
While the Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Page Program
Cycle..
Page Program (PP) command applied to a page which is protected by the Block Protect (BP2, BP1, BP0)
bit (see Table1) is not executed.
Figure7. Page Program Sequence Diagram
VER 1.2
10
ACE25AC200GL
2M SPI NOR FLASH
Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. AWrite Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase
(SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI.
Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven
low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low→sending Sector Erase command→3-byte address
on SI→CS# goes high. The command sequence is shown in Figure8. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not
executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated.
While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,
and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Sector Erase
cycle. Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1,
BP0) bit (see Table1) is not executed.
Figure8. Sector Erase Sequence Diagram
Block Erase (BE) (D8H)
The Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes
on SI. Any address inside the block is a valid address for the Block Erase (BE) command. CS# must be
driven low for the entire duration of the sequence.
The Block Erase command sequence: CS# goes low send Block Erase command 3-byte address on
SI
e dCrSiv#engoheigshhaigfthe.r Tthhee comma
eighth bit of the last address byte has been latched in; otherwise the Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is
initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Block
Erase cycle. Block Erase (BE) commands applied to a block which is protected by the Block Protect (BP2,
BP1, BP0) bits (see Table1) is not executed.
VER 1.2
11
Figure9. Block Erase Sequence Diagram
ACE25AC200GL
2M SPI NOR FLASH
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. AWrite Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)
command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS#
must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low send Chip Erase command CS# goes high. The
command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the command
code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven
high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in
progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write
In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. Write
Enable Latch (WEL) bit is reset to 0 at the end of the Chip Erase cycle. The Chip Erase (CE) command is
ignored if one or more sectors are protected by (BP2, BP1, BP0) bits.
Figure10. Chip Erase Sequence Diagram
Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is for reading both the JEDEC assigned Manufacturer ID
and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command
code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in
Figure11. If the 24-bit address is initially set to 000001H, the Device ID will be read first.
Figure11. Read Manufacture ID/ Device ID Sequence Diagram
VER 1.2
12
ACE25AC200GL
2M SPI NOR FLASH
Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed
by two bytes of device identification. The device identification indicates the memory type in the first byte,
and the memory capacity of the device in the second byte. Any Read Identification (RDID) command
while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is
shifted in.
This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is
shown in Figure12. The Read Identification (RDID) command is terminated by driving CS# to high at any
time during data output. After CS# is driven high, the device returns to Standby Mode and awaits for new
command.
Figure12. Read Identification ID Sequence Diagram
VER 1.2
13
ACE25AC200GL
2M SPI NOR FLASH
Electrical Characteristics
Power-On Timing
Table3. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
VCC(min) To CS# Low
Min
10
1
Max
Unit
us
t
VSL
t
Time Delay Before Write Instruction
Write Inhibit Voltage
10
ms
V
PUW
V
WI
1
2.5
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The
Status Register contains 00H (all Status Register bits are 0).
Data Retention and Endurance
Parameter
Test Condition
150℃
Min
10
Unit
Years
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
125℃
20
-40 to 85℃
100K
Latch up Characteristics
Parameter
Min
Max
Input Voltage Respect To VSS On I/O Pins
VCC Current
-1.0V
VCC+1.0V
100mA
-100mA
VER 1.2
14
ACE25AC200GL
2M SPI NOR FLASH
Capacitance Measurement Condition
Symbol
Parameter
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
VIN=0V
C
Input Capacitance
IN
C
Output Capacitance
8
VOUT=0V
OUT
C
L
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Figure13. Input Test Waveform and Measurement Level
VER 1.2
15
ACE25AC200GL
2M SPI NOR FLASH
DC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
±2
Unit
μA
I
LI
Input Leakage Current
Output Leakage Current
Standby Current
I
±2
μA
LO
CS#=VCC VIN=VCC or
VSS
I
1
5
μA
CC1
CLK=0.1VCC/0.9VCC at
120MHz for Fast Read
CLK=0.1VCC/0.9VCC at
40MHz for Read
15
13
20
I
Operating Current(Read)
mA
CC3
18
I
Operating Current(PP)
Operating Current(WRSR)
Operating Current(SE)
Operating Current(BE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
10
mA
mA
mA
mA
V
CC4
I
10
CC5
I
10
CC6
I
10
CC7
V
IL
-0.5
0.2VCC
VCC+0.4
0.4
V
IH
Input High Voltage
0.7VCC
V
V
Output Low Voltage
IOL=1.6mA
IOH=-100uA
V
OL
V
Output High Voltage
VCC-0.2
V
OH
VER 1.2
16
ACE25AC200GL
2M SPI NOR FLASH
AC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V,CL=30pf)
Symbol
Parameter
Serial Clock Frequency For:Fast Read(0BH),
Serial Clock Frequency For:Read(03H)
Serial Clock High Time
Min.
DC
DC
4
Typ
Max.
40
Unit
MHz
MHz
ns
f
C
R
f
40
t
CLH
t
CLL
Serial Clock Low Time
4
ns
t
t
CLCH
CHCL
Serial Clock Rise Time(Slew Rate)
Serial Clock Fall Time(Slew Rate)
CS# Active Setup Time
0.2
0.2
5
V/ns
V/ns
ns
t
SLCH
CHSH
SHCH
t
t
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
t
CHSL
SHSL
SHQZ
CLQX
DVCH
CHDX
CS# Not Active Hold Time
5
ns
t
CS# High Time (read/write)
20
ns
t
t
t
t
Output Disable Time
6
ns
Output Hold Time
1
2
2
5
5
5
5
ns
Data In Setup Time
ns
Data In Hold Time
ns
t
HLCH
HHCH
Hold# Low Setup Time(relative to Clock)
Hold# High Setup Time(relative to Clock)
Hold# High Hold Time(relative to Clock)
Hold# Low Hold Time(relative to Clock)
Hold# Low To High-Z Output
Hold# Low To Low-Z Output
Clock Low To Output Valid
ns
t
ns
t
CHHL
ns
t
CHHH
ns
t
HLQZ
HHQX
CLQV
WHSL
SHWL
6
6
ns
t
t
ns
6.5
ns
t
t
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
20
ns
100
ns
CS# High To Standby Mode With Electronic
Signature Read
t
RES2
0.1
us
t
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
100
1.8
180
0.8
6
200
2.6
360
1.5
10
ms
ms
ms
s
W
t
PP
SE
BE
CE
t
t
t
Block Erase Time
Chip Erase Time
s
VER 1.2
17
ACE25AC200GL
2M SPI NOR FLASH
Figure14. Serial Input Timing
Figure15. Output Timing
VER 1.2
18
ACE25AC200GL
2M SPI NOR FLASH
Packaging information
DIP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
B
3.710
0.510
3.200
0.380
4.310
0.146
0.020
0.126
0.015
0.170
3.600
0.570
0.142
0.022
B1
C
1.524(BSC)
0.060(BSC)
0.204
9.000
6.200
7.320
0.360
9.400
6.600
7.920
0.008
0.354
0.244
0.288
0.014
0.370
0.260
0.312
D
E
E1
e
2.540 (BSC)
0.100(BSC)
L
3.000
8.400
3.600
9.000
0.118
0.331
0.142
0.354
E2
VER 1.2
19
ACE25AC200GL
2M SPI NOR FLASH
Packaging information
SOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
0.053
0.004
0.053
0.013
0.006
0.185
0.150
0.228
0.069
0.010
0.061
0.020
0.010
0.200
0.157
0.244
c
D
E
E1
e
1.270 (BSC)
0.050 (BSC)
L
0.400
0°
1.270
8°
0.016
0°
0.050
8°
θ
VER 1.2
20
ACE25AC200GL
2M SPI NOR FLASH
Packaging information
SOP-8L (208mil)
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
2.150
0.250
1.900
0.500
0.250
5.330
8.100
5.380
0.085
0.010
0.075
0.020
0.010
0.210
0.319
0.212
0.050
1.700
0.350
0.100
5.130
7.700
5.180
0.002
0.067
0.014
0.004
0.202
0.303
0.204
c
D
E
E1
e
1.270 (BSC)
0.050 (BSC)
L
0.500
0°
0.850
8°
0.020
0°
0.033
8°
θ
VER 1.2
21
ACE25AC200GL
2M SPI NOR FLASH
Packaging information
TSSOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
D
E
2.900
4.300
0.190
0.090
6.250
3.100
4.500
0.300
0.200
6.550
1.200
1.000
0.150
0.114
0.169
0.007
0.004
0.246
0.122
0.177
0.012
0.008
0.258
0.047
0.039
0.006
b
c
E1
A
A2
A1
e
0.800
0.050
0.031
0.002
0.65 (BSC)
0.25 (TYP)
0.026 (BSC)
L
0.500
1°
0.700
7°
0.020
0.028
H
0.01 (TYP)
θ
1°
7°
VER 1.2
22
ACE25AC200GL
2M SPI NOR FLASH
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. Acritical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.2
23
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