S-8262AAA-I8T1U [ABLIC]
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK;
| 型号： | S-8262AAA-I8T1U |
| 厂家： | 
ABLIC |
| 描述： | BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK |
| 文件： | 总36页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8262A Series
BATTERY PROTECTION IC
FOR 2-SERIAL-CELL PACK
www.ablic.com
© ABLIC Inc., 2012-2016
Rev.1.0_03
S-8262A Series is a protection IC for 2-serial-cell lithium-ion / lithium polymer rechargeable batteries and includes high-
accuracy voltage detectors and delay circuits.
The S-8262A Series has an alarm signal output pin (AO pin) which outputs the alarm detection signal.
The alarm detection signal is output prior to the charge control FET signal by overcharge detection.
Features
High-accuracy voltage detection for each cell
Overcharge detection voltage n (n = 1, 2)
3.900 V to 4.500 V (5 mV steps)
Accuracy 20 mV (Ta = 25°C)
Accuracy 25 mV (Ta = 10°C to 60°C)
Accuracy 30 mV
Accuracy 50 mV
Accuracy 100 mV
Overcharge release voltage n (n = 1, 2)
Overdischarge detection voltage n (n = 1, 2) 2.000 V to 3.000 V (10 mV steps)
3.800 V to 4.500 V*1
Overdischarge release voltage n (n = 1, 2)
Discharge overcurrent 1 detection voltage
Discharge overcurrent 2 detection voltage
Load short-circuiting detection voltage
Charge overcurrent detection voltage
2.000 V to 3.400 V*2
0.050 V to 0.200 V (10 mV steps) Accuracy 10 mV
0.200 V to 0.400 V (20 mV steps)
0.700 V (fixed)
Accuracy 20 mV
Accuracy 100 mV
0.400 V to 0.050 V (25 mV steps) Accuracy 20 mV
Detection delay times are generated only by an internal circuit (external capacitors are unnecessary).
Accuracy 20%
High-withstand voltage (VM pin and CO pin: Absolute maximum rating = 28 V)
0 V battery charge function "available" / "unavailable" is selectable.
Wide operating temperature range
Low current consumption
During operation
Ta = 40°C to 85°C
8.0 A max. (Ta = 25°C)
0.1 A max. (Ta = 25°C)
During power-down
Lead-free (Sn 100%), halogen-free
*1. Overcharge release voltage = Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage n (n = 1, 2) can be selected as 0 V or from a range of 0.1 V to 0.4 V in 25 mV
steps.)
*2. Overdischarge release voltage = Overdischarge detection voltage Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage n (n = 1, 2) can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV
steps.)
Applications
Lithium-ion rechargeable battery packs
Lithium polymer rechargeable battery packs
Package
SNT-8A
1
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Block Diagram
Oscillator
control circuit
Divider control
circuit
0 V battery charge
circuit or 0 V battery
charge inhibition
circuit
DO
CO
VDD
VC
500 k
Charger
detection
circuit
VSS
VM
20 k
DP
2.5 M
AO
Remark All diodes shown in figure are parasitic diodes.
Figure 1
2
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Product Name Structure
1. Product name
S-8262A xx
-
I8T1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
I8T1: SNT-8A, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name
Dimension
Tape
Reel
Land
SNT-8A
PH008-A-P-SD
PH008-A-C-SD
PH008-A-R-SD
PH008-A-L-SD
3. Product name list
3. 1 SNT-8A
Table 2
Discharge
Discharge
Over-
Over-
discharge
Release
Voltage
Charge
Overcharge
Detection
Voltage
Overcharge
Release
Voltage
[VCL
Overcurrent 1 Overcurrent 2
discharge
Overcurrent
Detection
Voltage
0 V Battery
Power-down
Function
Delay Time
Detection
Voltage
Detection
Voltage
Product Name
Detection
Voltage
Charge
Combination*1
Function
[VCU
]
]
[VDIOV1
]
[VDIOV2]
[VDL
]
[VDU
]
[VCIOV]
Available
Available
Available
Available
(1)
(2)
0.100 V
0.100 V
S-8262AAA-I8T1U
S-8262AAB-I8T1U
4.225 V
4.225 V
4.100 V
4.100 V
2.000 V
2.000 V
2.000 V
2.000 V
0.100 V
0.100 V
0.300 V
0.300 V
*1. Refer to Table 3 about the details of the delay time combinations.
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
3
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Table 3 (1 / 2)
Overcharge Alarm
Release
Overcharge
Detection
Delay Time
Overcharge
Release
Delay Time
[tCL]
Overcharge Alarm
Detection
Overdischarge
Detection
Delay Time
[tDL]
Delay Time
Combination
Delay Time
Delay Time
[tAL]
[tCU
]
[tAU]
(1)
(2)
8.2 s
8.2 s
2 ms
2 ms
8 ms
8 ms
128 ms
128 ms
128 ms
128 ms
Table 3 (2 / 2)
Discharge Overcurrent 1
Detection
Discharge Overcurrent 2
Detection
Load Short-circuiting
Detection
Charge Overcurrent
Detection
Delay Time
Delay Time
Delay Time
Delay Time
Delay Time
Combination
[tDIOV1
]
[tDIOV2
]
[tSHORT
]
[tCIOV]
128 ms
64 ms
(1)
(2)
8 ms
4 ms
280 s
280 s
8 ms
8 ms
Remark The delay times can be changed within the range listed Table 4. For details, please contact our sales office.
Table 4
Delay Time
Symbol
tCU
Selection Range
4.1 ms
Remark
Overcharge detection delay time
2.1 s
1 ms
4 ms
8.2 s*1
4 ms
Select a value from the left.
Select a value from the left.
Select a value from the left.
Overcharge release delay time
tCL
2 ms*1
Overcharge alarm detection delay time
Overcharge alarm release delay time
Overdischarge detection delay time
Discharge overcurrent 1 detection delay time
Discharge overcurrent 2 detection delay time
Load short-circuiting detection delay time
Charge overcurrent detection delay time
tAU
8 ms*1
16 ms
tAL
128 ms*1
32 ms
64 ms
4 ms
256 ms
64 ms
128 ms*1
8 ms*1
512 ms Select a value from the left.
128 ms*1 Select a value from the left.
256 ms Select a value from the left.
tDL
tDIOV1
tDIOV2
tSHORT
tCIOV
16 ms
1 ms
Select a value from the left.
Select a value from the left.
Select a value from the left.
280 s*1
500 s
8 ms*1
4 ms
16 ms
*1. This value is the delay time of the standard products.
4
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Pin Configuration
1. SNT-8A
Table 5
Top view
1
2
3
4
8
7
6
5
Pin No.
1
Symbol
CO
Description
Connection pin of charge control FET gate
(CMOS output)
Connection pin of discharge control FET gate
(CMOS output)
2
3
4
5
DO
AO
VSS
VC
Figure 2
Overcharge alarm signal output pin
(Nch open drain output)
Input pin for negative power supply,
connection pin for negative voltage of battery 2
Connection pin for negative voltage of battery 1,
connection pin for positive voltage of battery 2
Input pin for positive power supply,
connection pin for positive voltage of battery 1
Test mode switching pin (shortening delay time)
Voltage detection pin between VM pin and VSS pin
(Overcurrent / charger detection pin)
6
7
8
VDD
DP
VM
5
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Absolute Maximum Ratings
Table 6
(Ta = 25°C unless otherwise specified)
Item
Input voltage between VDD pin and VSS pin
VC pin input voltage
Symbol
VDS
Applied pin
Absolute Maximum Rating
VSS 0.3 to VSS 12
VSS 0.3 to VDD 0.3
VSS 0.3 to VSS 12
VDD 28 to VDD 0.3
VSS 0.3 to VDD 0.3
VVM 0.3 to VDD 0.3
VSS 0.3 to VSS 12
450*1
Unit
V
VDD
VC
DP
VM
DO
CO
AO
VVC
VDP
VVM
VDO
VCO
VAO
PD
V
DP pin input voltage
V
VM pin input voltage
V
DO pin output voltage
V
CO pin output voltage
V
AO pin output voltage
V
Power dissipation
mW
C
C
Operating ambient temperature
Storage temperature
Topr
Tstg
40 to 85
55 to 125
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Board name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
800
600
400
200
0
100
150
50
0
Ambient temperature (Ta) [C]
Figure 3 Package Power Dissipation (When Mounted on Board)
6
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Electrical Characteristics
1. Ta = 25°C
Table 7 (1 / 2)
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
VCUn
Condition
Min.
Typ.
Max.
Unit
DETECTION VOLTAGE
VCU
VCU
VCL
VDL
VDU
0.020
VCU
VCU
VCL
VDL
VDU
VCU
0.020
V
V
V
V
V
V
V
V
V
1
1
1
2
2
2
2
2
2
Overcharge detection voltage n (n = 1, 2)
Ta =
10°C to
60°C*1
0.025
0.030
0.050
0.100
VCU
VCL
VDL
VDU
0.025
0.030
0.050
0.100
VCLn
Overcharge release voltage n (n = 1, 2)
Overdischarge detection voltage n (n = 1, 2)
Overdischarge release voltage n (n = 1, 2)
Discharge overcurrent 1 detection voltage
Discharge overcurrent 2 detection voltage
Load short-circuiting detection voltage
Charge overcurrent detection voltage
0 V BATTERY CHARGE FUNCTION
VDLn
VDUn
VDIOV1
VDIOV2
VSHORT
VCIOV
VDIOV1
VDIOV2
0.010 VDIOV1 VDIOV1
0.020 VDIOV2 VDIOV2
0.010
0.020
0.600
0.700
0.800
0.020
VCIOV 0.020 VCIOV VCIOV
0 V battery charge function
"available"
V0CHA
0.0
0.4
0.7
0.8
1.0
1.1
V
V
0 V battery charge starting charger voltage
0 V battery charge inhibition battery voltage
2
2
0 V battery charge function
"unavailable"
V0INH
INTERNAL RESISTANCE
Resistance between VM pin and VDD pin
Resistance between VM pin and VSS pin
INPUT VOLTAGE
RVMD
RVMS
V1 = V2 = 1.8 V, V3 = 0 V
V1 = V2 = 3.5 V, V3 = 1.0 V
k
160
10
500
20
1500
40
3
3
k
Operating voltage between VDD pin and
VSS pin
VDSOP1
1.5
10
V
VDPH
VDPL
VDS
VDS
0.6
0.1
VDS
VDS
0.9
0.4
V
V
4
4
DP pin voltage "H"
V1 = V2 = 3.5 V
V1 = V2 = 3.5 V
DP pin voltage "L"
INPUT CURRENT
IOPE
IPDN
IVC
V1 = V2 = 3.5 V, V3 = 0 V
V1 = V2 = 1.5 V, V3 = 3.0 V
V1 = V2 = 3.5 V, V3 = 0 V
0.2
4.0
0.7
8.0
0.1
1.5
A
A
A
2
2
2
Current consumption during operation
Current consumption during power-down
VC pin current
OUTPUT RESISTANCE
V1 = V2 = 3.5 V,
V3 = 0 V, V5 = 6.5 V
V1 = V2 = 4.7 V,
V3 = 0 V, V5 = 0.5 V
V1 = V2 = 3.5 V,
V3 = 0 V, V6 = 6.5 V
V1 = V2 = 1.8 V,
RCOH
RCOL
RDOH
RDOL
2.5
2.5
5
5
5
10
10
20
20
k
k
k
k
CO pin resistance "H"
CO pin resistance "L"
DO pin resistance "H"
DO pin resistance "L"
4
4
4
4
10
10
5
V3 = 3.6 V, V6 = 0.5 V
OUTPUT CURRENT
AO pin sink current
AO pin leak current
IAOL
IAOH
10
A
A
V1 = V2 = 4.7 V, V4 = 0.5 V
V4 = 10.0 V
4
4
0.1
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
7
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Table 7 (2 / 2)
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
DELAY TIME
tCU
tCU
0.8
tCU
tCL
tCU
1.2
Overcharge detection delay time
5
5
5
5
5
5
5
5
5
tCL
tCL
tAU
tAL
tDL
0.8
0.8
0.8
0.8
tCL
tAU
tAL
tDL
1.2
1.2
1.2
1.2
Overcharge release delay time
tAU
tAU
Overcharge alarm detection delay time
Overcharge alarm release delay time
Overdischarge detection delay time
Discharge overcurrent 1 detection delay time
Discharge overcurrent 2 detection delay time
Load short-circuiting detection delay time
Charge overcurrent detection delay time
tAL
tAL
tDL
tDL
tDIOV1
tDIOV2
tSHORT
tCIOV
tDIOV1
tDIOV2
tSHORT
0.8
0.8
0.8
tDIOV1
tDIOV2
tSHORT
tCIOV
tDIOV1
tDIOV2
tSHORT
1.2
1.2
1.2
tCIOV
0.8
tCIOV 1.2
8
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
2. Ta = 40°C to 85°C
Table 8 (1 / 2)
(Ta = 40°C to 85°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
DETECTION VOLTAGE
VCUn
VCU
VCL
VDL
VDU
0.045
VCU
VCL
VDL
VDU
VCU
0.030
V
V
V
V
V
V
V
V
1
1
2
2
2
2
2
2
Overcharge detection voltage n (n = 1, 2)
Overcharge release voltage n (n = 1, 2)
Overdischarge detection voltage n (n =1, 2)
Overdischarge release voltage n (n =1, 2)
Discharge overcurrent 1 detection voltage
Discharge overcurrent 2 detection voltage
Load short-circuiting detection voltage
Charge overcurrent detection voltage
0 V BATTERY CHARGE FUNCTION
VCLn
0.070
0.085
0.140
VCL
VDL
VDU
0.040
0.060
0.110
VDLn
VDUn
VDIOV1
VDIOV2
VSHORT
VCIOV
VDIOV1
VDIOV2
0.015 VDIOV1 VDIOV1
0.030 VDIOV2 VDIOV2
0.015
0.030
0.550
0.700
0.850
0.030
VCIOV
0.030 VCIOV VCIOV
0 V battery charge function
"available"
V0CHA
V0INH
0.0
0.3
0.7
0.8
1.5
1.3
V
V
0 V battery charge starting charger voltage
0 V battery charge inhibition battery voltage
2
2
0 V battery charge function
"unavailable"
INTERNAL RESISTANCE
Resistance between VM pin and VDD pin
Resistance between VM pin and VSS pin
INPUT VOLTAGE
RVMD
RVMS
V1 = V2 = 1.8 V, V3 = 0 V
V1 = V2 = 3.5 V, V3 = 1.0 V
k
30
7.2
500
20
2190
44
3
3
k
Operating voltage between VDD pin and
VSS pin
VDSOP1
1.5
10
V
VDPH
VDPL
VDS
VDS
0.55
0.05
VDS
VDS
0.95
0.45
V
V
4
4
DP pin voltage "H"
V1 = V2 = 3.5 V
V1 = V2 = 3.5 V
DP pin voltage "L"
INPUT CURRENT
IOPE
IPDN
IVC
V1 = V2 = 3.5 V, V3 = 0 V
V1 = V2 = 1.5 V, V3 = 3.0 V
V1 = V2 = 3.5 V, V3 = 0 V
0.2
4.0
0.7
8.5
A
A
A
2
2
2
Current consumption during operation
Current consumption during power-down
VC pin current
0.15
2.0
OUTPUT RESISTANCE
V1 = V2 = 3.5 V,
V3 = 0 V, V5 = 6.5 V
V1 = V2 = 4.7 V,
V3 = 0 V, V5 = 0.5 V
V1 = V2 = 3.5 V,
V3 = 0 V, V6 = 6.5 V
V1 = V2 = 1.8 V,
RCOH
RCOL
RDOH
RDOL
1.2
1.2
2.4
2.4
5
5
15
15
30
30
k
k
k
k
CO pin resistance "H"
CO pin resistance "L"
DO pin resistance "H"
DO pin resistance "L"
4
4
4
4
10
10
V3 = 3.6 V, V6 = 0.5 V
OUTPUT CURRENT
AO pin sink current
AO pin leak current
IAOL
IAOH
10
A
A
V1 = V2 = 4.7 V, V4 = 0.5 V
V4 = 10.0 V
4
4
0.15
9
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Table 8 (2 / 2)
(Ta = 40°C to 85°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
DELAY TIME
tCU
tCU
0.3
tCU
tCL
tCU
2.0
Overcharge detection delay time
5
5
5
5
5
5
5
5
5
tCL
tCL
tAU
tAL
tDL
0.3
0.3
0.3
0.3
tCL
tAU
tAL
tDL
2.0
2.0
2.0
2.0
Overcharge release delay time
tAU
tAU
Overcharge alarm detection delay time
Overcharge alarm release delay time
Overdischarge detection delay time
Discharge overcurrent 1 detection delay time
Discharge overcurrent 2 detection delay time
Load short-circuiting detection delay time
Charge overcurrent detection delay time
tAL
tAL
tDL
tDL
tDIOV1
tDIOV2
tSHORT
tCIOV
tDIOV1
tDIOV2
tSHORT
0.3
0.3
0.3
tDIOV1
tDIOV2
tSHORT
tCIOV
tDIOV1
tDIOV2
tSHORT
2.0
2.0
2.0
tCIOV
0.3
tCIOV 2.0
10
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Test Circuits
1. Overcharge detection voltage, overcharge release voltage
(Test circuit 1)
Overcharge detection voltage (VCU1) is defined as the voltage V1 at which VCO goes from "H" to "L" when the
voltage V1 is gradually increased from the set conditions of V1 = V2 = VCU 0.05 V, V3 = 0 V. After that,
overcharge release voltage (VCL1) is defined as the voltage V1 at which VCO goes from "L" to "H" when the voltage
V1 is gradually decreased after setting V2 = 3.5 V. Overcharge hysteresis voltage (VHC1) is defined as the
difference between VCU1 and VCL1
.
Overcharge detection voltage (VCU2) is defined as the voltage V2 at which VCO goes from "H" to "L" when the
voltage V2 is gradually increased from the set conditions of V1 = V2 = VCU 0.05 V, V3 = 0 V. After that,
overcharge release voltage (VCL2) is defined as the voltage V2 at which VCO goes from "L" to "H" when the voltage
V2 is gradually decreased after setting V1 = 3.5 V. Overcharge hysteresis voltage (VHC2) is defined as the
difference between VCU2 and VCL2
.
2. Overdischarge detection voltage, overdischarge release voltage
(Test circuit 2)
Overdischarge detection voltage (VDL1) is defined as the voltage V1 at which VDO goes from "H" to "L" when the
voltage V1 is gradually decreased from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V. After that, overdischarge
release voltage (VDU1) is defined as the voltage V1 at which VDO goes from "L" to "H" when the voltage V1 is
gradually increased. Overdischarge hysteresis voltage (VHD1) is defined as the difference between VDU1 and VDL1
.
Overdischarge detection voltage (VDL2) is defined as the voltage V2 at which VDO goes from "H" to "L" when the
voltage V2 is gradually decreased from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V. After that, overdischarge
release voltage (VDU2) is defined as the voltage V2 at which VDO goes from "L" to "H" when the voltage V2 is
gradually increased. Overdischarge hysteresis voltage (VHD2) is defined as the difference between VDU2 and VDL2
.
3. Discharge overcurrent 1 detection voltage
(Test circuit 2)
Discharge overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V3 whose delay time for changing VDO
from "H" to "L" is discharge overcurrent 1 detection delay time (tDIOV1) when the voltage V3 is increased from the
set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
4
Discharge overcurrent 2 detection voltage
(Test circuit 2)
Discharge overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V3 whose delay time for changing VDO
from "H" to "L" is discharge overcurrent 2 detection delay time (tDIOV2) when the voltage V3 is increased from the
set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
5. Load short-circuiting detection voltage
(Test circuit 2)
Load short-circuiting detection voltage (VSHORT) is defined as the voltage V3 whose delay time for changing VDO
from "H" to "L" is load short-circuiting delay time (tSHORT) when the voltage V3 is increased from the set conditions
of V1 = V2 = 3.5 V, V3 = 0 V.
6. Charge overcurrent detection voltage
(Test circuit 2)
Charge overcurrent detection voltage (VCIOV) is defined as the voltage V3 whose delay time for changing VCO from
"H" to "L" is charge overcurrent delay time (tCIOV) when the voltage V3 is decreased from the set conditions of V1 =
V2 = 3.5 V, V3 = 0 V.
7. Current consumption during operation
(Test circuit 2)
Current consumption during operation (IOPE) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = V2 = 3.5 V, V3 = 0 V.
11
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
8. VC pin current
(Test circuit 2)
The VC pin current (IVC) is the current that flows through the VC pin (IVC) under the set conditions of V1 = V2 =
3.5 V, V3 = 0 V.
9. Current consumption during power-down
(Test circuit 2)
Current consumption during power-down (IPDN) is the current that flows through the VSS pin (ISS) under the set
conditions of V1 = V2 = 1.5 V, V3 = 3.0 V.
10. Resistance between VM pin and VDD pin
(Test circuit 3)
RVMD is the resistance between VM pin and VDD pin under the set conditions of V1 = V2 = 1.8 V, V3 = 0 V.
11. Resistance between VM pin and VSS pin
(Test circuit 3)
RVMS is the resistance between VM pin and VSS pin under the set conditions of V1 = V2 = 3.5 V, V3 = 1.0 V.
12. CO pin resistance "H"
(Test circuit 4)
The CO pin resistance "H" (RCOH) is the resistance between VDD pin and CO pin under the set conditions of V1 = V2 =
3.5 V, V3 = 0 V, V5 = 6.5 V.
13. CO pin resistance "L"
(Test circuit 4)
The CO pin resistance "L" (RCOL) is the resistance between VM pin and CO pin under the set conditions of V1 = V2 =
4.7 V, V3 = 0 V, V5 = 0.5 V.
14. DO pin resistance "H"
(Test circuit 4)
The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 =
V2 = 3.5 V, V3 = 0 V, V6 = 6.5 V
15. DO pin resistance "L"
(Test circuit 4)
The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = V2 =
1.8 V, V3 = 0 V, V6 = 0.5 V.
16. AO pin sink current
(Test circuit 4)
The AO pin sink current (IAOL) is the current that flows through the AO pin (IAO) under the set conditions of V1 = V2 =
4.7 V, V3 = 0 V, V4 = 0.5 V.
17. AO pin leak current
The AO pin leak current (IAOH) is the current that flows through the AO pin (IAO) under the set conditions of V1 = V2 =
3.5 V, V3 = 0 V, V4 = 10.0 V.
12
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
18. Overcharge detection delay time, overcharge release delay time
(Test circuit 5)
The overcharge detection delay time (tCU) is the time needed for VCO to go to "L" just after the voltage V1 increases
and exceeds VCU from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V. After that, the overcharge release delay
time (tCL) is the time needed for VCO to go to "H" after the voltage V1 decreases and falls below VCL.
19. Overcharge alarm detection delay time, overcharge alarm release delay time
(Test circuit 5)
The overcharge alarm detection delay time (tAU) is the time needed for VAO to go to "L" just after the voltage V1
increases and exceeds VCU from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V, V4 = V1 V2. After that, the
overcharge alarm release delay time (tAL) is the time needed for VAO to go to "H" after the voltage V1 decreases
and falls below VCL before VCO goes to "L".
20. Overdischarge detection delay time
(Test circuit 5)
The overdischarge detection delay time (tDL) is the time needed for VDO to go to "L" after the voltage V1 decreases
and falls below VDL from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
21. Discharge overcurrent 1 detection delay time
(Test circuit 5)
The discharge overcurrent 1 detection delay time (tDIOV1) is the time needed for VDO to go to "L" after the voltage V3
increases and exceeds VDIOV1 from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
22. Discharge overcurrent 2 detection delay time
(Test circuit 5)
The discharge overcurrent 2 detection delay time (tDIOV2) is the time needed for VDO to go to "L" after the voltage V3
increases and exceeds VDIOV2 from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
23. Load short-circuiting detection delay time
(Test circuit 5)
The load short-circuiting detection delay time (tSHORT) is the time needed for VDO to go to "L" after the voltage V3
increases and exceeds VSHORT from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
24. Charge overcurrent detection delay time
(Test circuit 5)
The charge overcurrent detection delay time (tCIOV) is the time needed for VCO to go to "L" after the voltage V3
decreases and falls below VCIOV from the set conditions of V1 = V2 = 3.5 V, V3 = 0 V.
25. 0 V battery charge starting charger voltage (0 V battery charge function "available")
(Test circuit 2)
The 0 V battery charge starting charger voltage (V0CHA) is defined as the voltage V3 at which VCO goes to "H" (VCO
= VDD) when the voltage V3 is gradually decreased under the set conditions of V1 = V2 = V3 = 0 V.
26. 0 V battery charge inhibition battery voltage (0 V battery charge function "unavailable")
(Test circuit 2)
The 0 V battery charge inhibition battery voltage (V0INH) is defined as the voltage V1 at which VCO goes to "L" (VVM
0.1 V or lower) when the voltage V1 is gradually decreased from the set conditions of V1 = V2 = 1.5 V, V3 = 6.0 V.
13
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
R1 = R2 = 470 , C1 = C2 = 0.1 F
RAO = 47 k
R1
AO
CO
DO
VM
VDD
VC
C1
R2
V1
V2
V VAO
V4
S-8262A Series
C2
V
VSS
DP
VDO
VCO
V
V3
COM
Figure 4 Test Circuit 1
RAO = 47 k
AO
CO
A
A
A
VDD
VC
V1
V2
VAO
V
V4
S-8262A Series
DO
V
VSS
DP
VDO
VCO
V
VM
V3
COM
Figure 5 Test Circuit 2
AO
VDD
V1
V2
CO
DO
VM
VC
S-8262A Series
VSS
DP
A
IVM
ISS
A
V3
COM
Figure 6 Test Circuit 3
14
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
IAO
AO
CO
DO
VM
VDD
VC
A
V1
V2
ICO
A
S-8262A Series
A
IDO
VSS
DP
V4
V5
V7
V6
V3
COM
Figure 7 Test Circuit 4
RAO = 47k
AO
CO
VDD
V1
V2
VC
V4
S-8262A Series
DO
VSS
DP
VM
V3
Oscilloscope
COM
Figure 8 Test Circuit 5
15
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Operation
Remark Refer to " Battery Protection IC Connection Example".
1. Normal status
The S-8262A Series monitors the voltage of the battery connected between the VDD pin and VSS pin and the
voltage difference between the VM pin and VSS pin to control charging and discharging. When the battery voltage
is in the range from overdischarge detection voltage (VDL) to overcharge detection voltage (VCU), and the VM pin
voltage is in the range from the charge overcurrent detection voltage (VCIOV) to discharge overcurrent 1 detection
voltage (VDIOV1), the S-8262A Series turns both the charge and discharge control FETs on. This condition is called
the normal status, and in this condition charging and discharging can be carried out freely. In the normal status the
AO pin output becomes "High-Z". The resistance (RVMD) between the VM pin and VDD pin, and the resistance
(RVMS) between the VM pin and VSS pin are not connected in the normal status.
Caution When the battery is connected for the first time, discharging may not be enabled. In this case,
Short the VM pin and VSS pin, or
Set the VM pin’s voltage at the level of VCIOV or more and VDIOV1 or less by connecting the charger
The IC returns to the normal status.
2. Overcharge status
When the battery voltage becomes higher than VCU during charging in the normal status and detection continues
for the overcharge alarm detection delay time (tAU) or longer, the AO pin output becomes 'L". Moreover, when the
detection continues for the detection delay time (tCU) or longer, the S-8262A Series turns the charge control FET off
to stop charging. This condition is called the overcharge status. In the overcharge status the AO pin output
maintains "L", and RVMD and RVMS are not connected.
When the AO pin output is "L", the AO pin output becomes "High-Z" after the overcharge alarm release delay time
(tAL) if the battery voltage decreases and falls below VCU during tCU
.
The overcharge status is released in the following two cases ((1) and (2)). The AO pin output becomes "High-Z"
simultaneously with the release of the overcharge status.
(1) In the case that the VM pin voltage is lower than VDIOV2, the S-8262A Series releases the overcharge status
when the battery voltage falls below VCL.
(2) In the case that the VM pin voltage is higher than or equal to VDIOV2, the S-8262A Series releases the
overcharge status when the battery voltage falls below VCU
.
When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises
more than the voltage at VSS pin due to the Vf voltage of the parasitic diode, because the discharge current
flows through the parasitic diode in the charge control FET. If this VM pin voltage is higher than or equal to
VDIOV2, the S-8262A Series releases the overcharge status when the battery voltage is lower than or equal to
VCU
.
Caution 1. If the battery is charged to a voltage higher than VCU and the battery voltage does not fall to
VCU or lower even when a heavy load is connected, discharge overcurrent 1 detection,
discharge overcurrent 2 detection and load short-circuiting detection do not function until the
battery voltage falls below VCU. However, since an actual battery has an internal impedance of
tens of m, the battery voltage drops immediately after a heavy load that causes overcurrent
is connected, and discharge overcurrent 1 detection, discharge overcurrent 2 detection and
load short-circuiting detection function.
2. If a charger is connected after the overcharge detection, the overcharge status is not released
even when the battery voltage falls below VCL. The S-8262A Series releases the charge
overcurrent status when the voltage at the VM pin returns to VCIOV or higher by removing the
charger.
16
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
3. Overdischarge status
When the battery voltage falls below overdischarge detection voltage (VDL) during discharging in the normal status
and the detection continues for the overdischarge detection delay time (tDL) or longer, the S-8262A Series turns the
discharge control FET off to stop discharging. This condition is called the overdischarge status. In the
overdischarge status the AO pin output becomes "High-Z".
Under the overdischarge status, the VM pin and VDD pin are shorted by RVMD in the IC. The VM pin voltage is
pulled up by RVMD
.
When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is lower
than 0.7 V typ., the S-8262A Series releases the overdischarge status when the battery voltage reaches VDL or
higher.
When VM pin voltage is not lower than 0.7 V typ., the S-8262A Series releases the overdischarge status when the
battery voltage reaches VDU or higher.
RVMS is not connected in the overdischarge status.
3. 1 With power-down function
Under the overdischarge status, when voltage difference between the VM pin and VDD pin is 0.8 V typ. or lower,
the current consumption is reduced to the power-down current consumption (IPDN).
4. Discharge overcurrent status
(Discharge overcurrent 1, discharge overcurrent 2, load short-circuiting)
When a battery in the normal status is in the status where the voltage of the VM pin is equal to or higher than
VDIOV1 because the discharge current is equal to or higher than the specified value and the status lasts for the
discharge overcurrent 1 detection delay time (tDIOV1) or longer, the discharge control FET is turned off and
discharging is stopped. This status is called the discharge overcurrent status. In the discharge overcurrent status
the AO pin output becomes "High-Z".
In the discharge overcurrent status, the VM pin and VSS pin are shorted by the RVMS in the IC. However, the
voltage of the VM pin is at the VDD potential due to the load as long as the load is connected. When the load is
disconnected, the VM pin returns to the VSS potential.
If the voltage at the VM pin returns to VDIOV1 or lower, the S-8262A Series releases the discharge overcurrent
status.
RVMD is not connected in the discharge overcurrent detection status.
5. Charge overcurrent status
When a battery in the normal status is in the status where the voltage of the VM pin is equal to or lower than VCIOV
because the charge current is equal to or higher than the specified value and the status lasts for the charge
overcurrent detection delay time (tCIOV) or longer, the charge control FET is turned off and charging is stopped. This
status is called the charge overcurrent status. In the charge overcurrent status the AO pin output becomes "High-
Z".
The S-8262A Series releases the charge overcurrent status when the voltage at the VM pin returns to VCIOV or
higher by removing the charger.
The charge overcurrent detection function does not work in the overdischarge status.
RVMD and RVMS are not connected in the charge overcurrent status.
6. 0 V battery charge function "available"
This function is used to recharge a connected battery whose voltage is 0 V due to self-discharge. When the 0 V
battery charge starting charger voltage (V0CHA) or a higher voltage is applied between the EB and EB pins by
connecting a charger, the charge control FET gate is fixed to the VDD potential.
When the voltage between the gate and source of the charge control FET becomes equal to or higher than the
threshold voltage due to the charger voltage, the charge control FET is turned on to start charging. At this time, the
discharge control FET is off and the charging current flows through the internal parasitic diode in the discharge
control FET. When the battery voltage becomes equal to or higher than VDU, the S-8262A Series enters the normal
status.
Caution 1. Some battery providers do not recommend recharging for a completely self-discharged
battery. Please ask the battery provider to determine whether to enable or inhibit the 0 V
battery charge function.
2. The 0 V battery charge function has higher priority than the charge overcurrent detection
function. Consequently, a product in which use of the 0 V battery charge function is enabled
charges a battery forcibly and the charge overcurrent cannot be detected when the battery
voltage is lower than VDL
.
17
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
7. 0 V battery charge function "unavailable"
This function inhibits charging when a battery that is internally short-circuited (0 V battery) is connected. When the
battery voltage is the 0 V battery charge inhibition battery voltage (V0INH) or lower, the charge control FET gate is
fixed to the EB pin voltage to inhibit charging. When the battery voltage is V0INH or higher, charging can be
performed.
Caution Some battery providers do not recommend recharging for a completely self-discharged battery.
Please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge
function.
8. Delay circuit
The detection delay times are determined by dividing a clock of approximately 4 kHz by the counter.
Remark tDIOV1 and tDIOV2 start when VDIOV1 is detected. Therefore, when VDIOV2 is detected over tDIOV2 after VDIOV1
the S-8262A Series turns the discharge control FET off during 0 tD tDIOV2 from the time of detecting
VDIOV2
,
.
VDD
DO Pin
tD
0 tD tDIOV2
VSS
Time
tDIOV2
VDD
VDIOV2
VM Pin
VDIOV1
VSS
Time
Figure 9
9. DP pin
The S-8262A Series has a DP pin (Test mode switching pin). The S-8262A Series becomes test mode by raising
the voltage which is input to the DP pin to VDPH or higher.
Table 9
DP Pin
Open (VDP = VSS
"H" (VDPVDPH
"L" (VDPVDPL
Status
Normal operation mode
Test mode
)
)
)
Normal operation mode
Under test mode, the overcharge detection delay time (tCU) and the overcharge alarm release delay time (tAL) are
shortened to 1 /128 of normal delay time.
Except during the above test of shortening delay time, set the DP pin OPEN or short-circuit it to VSS. When the DP
pin is OPEN, it is pulled down to VSS by the internal resistance.
18
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Timing Charts
1. Overcharge alarm detection, overcharge alarm release
VCUn
VCLn
Battery voltage
VDUn
VDLn
High-Z
AO pin voltage
VSS
VDD
CO pin voltage
VEB
DO pin voltage
t
Overcharge detection delay time (tCU
)
Charger connection
Status*1
Overcharge alarm detection delay time (tAU
)
Overcharge alarm release delay time (tAL)
(1)
(2)
(1)
*1. (1): Normal status
(2): Overcharge alarm status
Remark The charger is assumed to charge with a constant current.
Figure 10
19
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
2. Overcharge detection, overcharge alarm detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
High-Z
AO pin voltage
VSS
VDD
CO pin voltage
VEB
DO pin voltage
Charger connection
Overcharge detection delay time (tCU
)
Overcharge alarm detection delay time (tAU)
(1)
Status*1
(2)
(3)
*1. (1): Normal status
(2): Overcharge alarm status
(3): Overcharge status
Remark The charger is assumed to charge with a constant current.
Figure 11
20
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
3. Overcharge release, overdischarge detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
High-Z
AO pin voltage
VSS
VDD
CO pin voltage
VEB
DO pin voltage
Load connection
Overcharge release delay time (tCL
)
Overdischarge detection delay time (tDL
)
(1)
(2)
(3)
Status*1
*1. (1): Overcharge status
(2): Normal status
(3): Overdischarge status
Remark The charger is assumed to charge with a constant current.
Figure 12
21
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
4. Discharge overcurrent detection
VCUn
VCLn
Battery voltage
DUn (VDLn
(VCUn
VHCn
)
V
VHDn
VDLn
)
VDD
DO pin voltage
VSS
VDD
CO pin voltage
VM pin voltage
VSS
VDD
VSHORT
VDIOV2
VDIOV1
VSS
Load connection
Discharge overurrent 2 detection delay time (tDIOV2
)
Load short-circuiting detection delay time (tSHORT
)
Discharge overcurrent 1 detection delay time (tDIOV1
)
(2)
(1)
(1)
(1)
(2)
(2)
(1)
Status*1
*1. (1): Normal status
(2): Discharge overcurrent status
Remark The charger is assumed to charge with a constant current.
Figure 13
22
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
5. Charge overcurrent detection
VCUn
V
CLn (VCUn
Battery voltage
DUn (VDLn VHDn
VDLn
VHCn)
V
)
VDD
DO pin voltage
VSS
VDD
CO pin voltage
VM pin voltage
VSS
VEB
VDD
VSS
VCIOV
VEB
Charger connection
Load connection
Overdischarge detection delay time (tDL
)
Charge overcurrent detection delay time (tCIOV
)
Charge overcurrent detection delay time (tCIOV
)
(2)
(2)
(3)
(1)
(1)
(1)
Status*1
*1. (1): Normal status
(2): Charge overcurrent status
(3): Overdischarge status
Remark The charger is assumed to charge with a constant current.
Figure 14
23
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Battery Protection IC Connection Example
EB
R1
VDD
R4
C1
AO
DP
Battery 1
R2
S-8262A Series
CO
VC
C2
Battery 2
VSS
DO
VM
R3
FET1
FET2
EB
Figure 15
Table 10 Constants for External Components
Symbol
FET1
Part
Nch
Purpose
Typ.
Min.
Max.
Remark
Threshold voltage Overdischarge
detection voltage*2
Gate to source withstanding voltage
Charger voltage*3
Discharge control
Charge control
MOS FET
Threshold voltage Overdischarge
detection voltage*2
Gate to source withstanding voltage
Charger voltage*3
Nch
MOS FET
FET2
Resistance should be as small as
possible to avoid lowering the
overcharge detection accuracy due to
current consumption.*4
ESD protection,
For power fluctuation
R1, R2 Resistor
C1, C2 Capacitor
470
0.1 F
150 *1
1 k*1
Connect a capacitor of 0.068 F or
higher between VDD pin and VSS pin.*5
Select as large a resistance as possible
to prevent current when a charger is
connected in reverse.*6
For power fluctuation
0.068 F*1 1.0 F*1
Protection for
reverse connection
of a charger
R3
R4
Resistor
Resistor
2 k
300 *1
4 k*1
Pull up resistor
47 k
*1. Please set up a filter constant to be R1 C1 = R2 C2.
*2. If the threshold voltage of a FET is low, the FET may not cut the charging current. If a FET with a threshold voltage
equal to or higher than the overdischarge detection voltage is used, discharging may be stopped before overdischarge
is detected.
*3. If the withstanding voltage between the gate and source is equal to or lower than the charger voltage, the FET may be
destroyed.
*4. An accuracy of overcharge detection voltage is guaranteed by R1 = 470 . Connecting resistors with other values
worsen the accuracy. In case of connecting larger resistor to R1, the voltage between the VDD pin and VSS pin may
exceed the absolute maximum rating because the current flows to the IC from the charger due to reverse connection
of charger. Connect a resistor of 150 or more to R1 for ESD protection.
*5. When connecting a resistor of 150 or less to R1 or R2 or a capacitor of 0.068 F or less to C1 or C2, the IC may
malfunction when power dissipation is largely fluctuated.
*6. When a resistor of 4 k or more is connected to R3, the charge current may not be cut.
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do not
guarantee proper operation. Perform thorough evaluation using the actual application to set the
constant.
3. Do not connect a resistor to the DP pin during normal use.
24
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
25
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs. Ta
1. 2 IPDN vs. Ta
8
1.00
6
4
2
0
0.75
0.50
0.25
0
−40 −25
0
25
50
75 85
−40 −25
0
25
50
75 85
Ta [°C]
Ta [°C]
1. 3 IOPE vs. VDD
6
5
4
3
2
1
0
0
2
4
6
8
10
VDD [V]
26
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
2. Overcharge detection / release voltage, overdischarge detection / release voltage,
overcurrent detection voltage, charge overcurrent detection voltage, and delay time
2. 1 VCU vs. Ta
2. 2 VCL vs. Ta
4.28
4.26
4.24
4.22
4.20
4.18
4.16
4.14
4.12
4.10
4.08
4.06
4.04
−40 −25
0
0
0
25
50
50
50
75 85
75 85
75 85
−40 −25
0
0
0
25
50
50
50
75 85
75 85
75 85
Ta [°C]
Ta [°C]
2. 3 VDL vs. Ta
2. 4 VDU vs. Ta
2.06
2.10
2.04
2.02
2.00
1.98
1.96
1.94
2.05
2.00
1.95
1.90
−40 −25
25
−40 −25
25
Ta [°C]
Ta [°C]
2. 5 tCU vs. Ta
2. 6 tCL vs. Ta
12
3.0
10
8
2.5
2.0
1.5
1.0
6
4
−40 −25
25
−40 −25
25
Ta [°C]
Ta [°C]
2. 7 tAU vs. Ta
2. 8 tAL vs. Ta
12
200
175
150
125
100
75
10
8
6
4
50
−40 −25
0
25
50
75 85
−40 −25
0
25
50
75 85
Ta [°C]
Ta [°C]
27
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
2. 9 tDL vs. Ta
2. 10 VDIOV1 vs. Ta
200
0.110
0.105
0.100
0.095
0.090
175
150
125
100
75
50
−40 −25
0
25
50
75 85
−40 −25
0
25
50
75 85
Ta [°C]
Ta [°C]
2. 11 tDIOV1 vs. VDD
2. 12 tDIOV1 vs. Ta
200
175
150
125
100
75
200
175
150
125
100
75
50
4
50
−40 −25
0
25
50
75 85
5
6
7
8
9
V
DD [V]
Ta [°C]
2. 13 VDIOV2 vs. Ta
2. 14 tDIOV2 vs. VDD
0.32
12
0.31
0.30
0.29
10
8
6
0.28
4
4
−40 −25
0
25
50
75 85
5
6
7
8
9
Ta [°C]
VDD [V]
2. 15 tDIOV2 vs. Ta
2. 16 VCIOV vs. Ta
−0.08
12
10
8
−0.09
−0.10
−0.11
6
4
−0.12
−40 −25
0
25
50
75 85
−40 −25
0
25
Ta [°C]
50
75 85
Ta [°C]
28
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
2. 17 tCIOV vs. VDD
2. 18 tCIOV vs. Ta
12
10
8
12
10
8
6
6
4
4
−40 −25
0
25
50
75 85
4
5
6
7
8
9
V
DD [V]
Ta [°C]
2. 19 VSHORT vs. Ta
2. 20 tSHORT vs. VDD
0.80
400
350
300
250
200
150
0.75
0.70
0.65
0.60
−40 −25
0
25
50
75 85
4
5
6
7
8
9
Ta [°C]
VDD [V]
2. 21 tSHORT vs. Ta
400
350
300
250
200
150
−40 −25
0
25
50
75 85
Ta [°C]
29
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
3. CO pin / DO pin
3. 1 RCOH vs. VCO
3. 2 RCOL vs. VCO
10
10
8
6
4
2
0
8
6
4
2
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
VCO [V]
VCO [V]
3. 3 RDOH vs. VDO
3. 4 RDOL vs. VDO
30
30
20
10
0
20
10
0
0
0
1
2
3
4
5
6
7
1
2
3
4
VDO [V]
V
DO [V]
4. AO pin
4. 1 IAOL vs. VAO
4. 2 IAOH vs. VAO
20
0.10
0.08
0.06
0.04
0.02
15
10
5
0
0
0
0
2
4
6
8
10
2
4
6
8
10
VAO [V]
VAO [V]
30
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-8262A Series
Rev.1.0_03
Marking Specification
1. SNT-8A
Top view
(1):
Blank
8
7
6
5
(2) to (4):
(5), (6):
Product code (Refer to Product name vs. Product code)
Blank
(1) (2) (3) (4)
(5) (6) (7) (8)
(7) to (11):
Lot number
(9) (10) (11
)
1
2
3
4
Product name vs. Product code
Product Code
(3)
Product Name
(2)
W
W
(4)
A
S-8262AAA-I8T1U
S-8262AAB-I8T1U
9
9
B
31
1.97±0.03
6
5
8
7
+0.05
-0.02
0.08
1
2
3
4
0.5
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
-0
4.0±0.1
2.0±0.05
0.25±0.05
ø1.5
0.65±0.05
ø0.5±0.1
4.0±0.1
2.25±0.05
4 3 2 1
5 6 7 8
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
PH008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
SNT-8A-A-Reel
TITLE
No.
PH008-A-R-SD-1.0
5,000
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
0.52
2
2.01
0.52
1
0.2
0.3
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
0.03 mm
3.
4.
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
SNT-8A-A
-Land Recommendation
TITLE
No.
No. PH008-A-L-SD-4.1
PH008-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
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