IMP8980D [A1PROS]
PCM Digital Switch; PCM数字开关
| 型号： | IMP8980D |
| 厂家： | 
A1 PROS CO., LTD. |
| 描述： | PCM Digital Switch |
| 文件： | 总14页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ISO 9001 Registered
IMP8980D
PCM Digital Switch
General Description
Functional Description
This CMOS device is designed for
switching PCM-encoded voice or data,
The ST-BUS architecture can be used
both in software-controlled digital voice
under microprocessor control, in a modern
digital exchange, PBX or Central Office. It
provides simultaneous connections for up
to 256 64kbit/s channels. Each of the eight
serial inputs and outputs consist of 32
64kbit/s channels multiplexed to form a
2048kbit/s ST-BUS stream. In addition,
the IMP8980D provides microprocessor
read and write access to individual
and data switching.
The ST-Bus serial streams operate
continuously at 2048kbit/s and are
arranged in 125µs wide frames which
contain 32 8-bit channels.
The IMP8980D can switch data from
channels on ST-BUS inputs to channels on
ST-BUS outputs and simultaneously
allows its controlling microprocessor to
read channels on ST-BUS inputs or write
to channels on ST-BUS outputs (Message
Mode). To the microprocessor, the
IMP8980D looks like a memory periph-
eral. The microprocessor can write to the
IMP8980D to establish switched connec-
tions between input ST-BUS channels and
output ST-BUS channels or to transmit
messages on output ST-BUS channels. By
reading from the IMP8980D, the micro-
processor can receive messages from
ST-BUS (Serial Telecom Bus) channels.
Features
♦ ST-BUS compatible
♦ 8-line x 32-channel inputs
♦ 8-line x 32-channel outputs
♦ 256 ports non-blocking switch
♦ Single power supply (+5V)
♦ 30mW power consumption
♦ Microprocessor-control interface
♦ Pin-compatible with Mitel MT8980
ST-BUS input channels or check which
Figure 1 Functional Block Diagram
C4i
F0i
VSS
VDD
ODE
Frame
Counter
Output
MUX
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Parallel
to
Serial
Serial
to
Parallel
Converter
Data
Memory
Converter
Control Register
Control Interface
Connection
Memory
DS CS
R/W A5/
A0
DTA D7/
D0
CSTo
switched connections have already been
established.
handles the microprocessor control signals
CS, DTA, R/W and DS. There are two
parts to any address in the Data Memory
or Connection 2-7 Memory. The higher
order bits come from the Control Register,
which may be written to or read from via
the Control Interface. The lower order bits
come from the address lines directly.
By integrating both switching and
interprocessor communications, the
IMP8980D allows systems to use distrib-
uted processing and to switch voice or data
in an ST-BUS architecture.
Hardware Description
The Control Register also allows the
chip to broadcast messages on all ST-BUS
outputs (i.e., to put every channel into
Message Mode), or to split the memory so
that reads are from the Data Memory and
writes are to the Connection Memory Low.
The Connection Memory High determines
whether individual output channels are in
Message Mode, and allows individual
output channels to go into a high-
impedance state, which enables arrays of
IMP8980D s to be constructed. It also
controls the CSTo pin.
All ST-BUS timing is derived from the
C4i and F0i signals.
Serial data at 2048 kbit/s is received at
the eight ST-BUS inputs (STi0 to STi7),
and serial data is transmitted at the eight
ST-BUS outputs (STo0 to STo7). Each
serial input accepts 32 channels of digital
data, each channel containing an 8-bit
word which may represent a PCM-encoded
analog/voice sample as provided by a
codec.
This serial input word is converted into
parallel data and stored in the 256 X 8
Data Memory. Locations in the Data
Memory are associated with particular
channels on particular ST-BUS input
streams. These locations can be read by the
microprocessor which controls the chip.
Software Control
The address lines on the Control
Interface give access to the Control
Register directly or, depending on the
contents of the Control Register, to the
High or Low sections of the Connection
Memory or to the Data Memory.If address
line A5 is low, then the Control Register is
addressed regardless of the other address
lines (see Figure 3). If A5 is high, then the
address lines A4-A0 select the memory
location corresponding to channel 0-31 for
the memory and stream selected in the
Control Register.
The data in the Control Register
consists of mode control bits, memory
select bits, and stream address bits (see
Figure 4). The memory select bits allow the
Connection Memory High or Low or the
Data Memory to be chosen, and the
stream address bits define one of the
ST-BUS input or output streams.
Locations in the Connection Memory,
which is split into high and low parts, are
associated with particular ST-BUS output
streams. When a channel is due to be
transmitted on an ST-BUS output, the
data for the channel can either be switched
from an ST-BUS input or it can originate
from the microprocessor. If the data is
switched from an input, then the contents
of the Connection Memory Low location
associated with the output channel is used
to address the Data Memory. This Data
Memory address corresponds to the
channel on the input ST-BUS stream on
which the data for switching arrived. If the
data for the output channel originates
from the microprocessor (Message Mode),
then the contents of the Connection
Memory Low location associated with the
output channel are output directly, and
this data is output repetitively on the
channel once every frame until the
Bit 7 of the Control Register allows split
memory operation - reads are from the
Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts
every output channel on every output
microprocessor intervenes.
The Connection Memory data is
received, via the Control Interface, at D7
to D0. The Control Interface also receives
address information at A5 to A0 and
2
© IMP, Inc.
IMP8980D DS-5-00
stream into active Message Mode; i.e., the
contents of the Connection Memory Low
are output on the ST-BUS output streams
once every frame unless the ODE pin is
low. In this mode the chip behaves as if
bits 2 and 0 of every Connection Memory
High location were 1, regardless of the
actual values.
High location function normally (see
Figure 5). If bit 2 is 1, the associated ST-
BUS output channel is in Message Mode;
i.e., the byte in the corresponding Connec-
tion Memory Low location is transmitted
on the stream at that channel. Otherwise,
one of the bytes received on the serial
inputs is transmitted and the contents of
the Connection Memory Low define the
ST-BUS input stream and channel where
the byte is to be found (see Figure 6).
If bit 6 of the Control Register is 0, then
bits 2 and 0 of each Connection Memory
Figure 3- Address Memory Map
A5 A4
A3
X
0
A2 A1
A0 HEX ADDRESS
LOCATION
0
1
1
ꢀ
ꢀ
ꢀ
1
X
0
0
ꢀ
ꢀ
ꢀ
1
X
0
0
ꢀ
ꢀ
ꢀ
1
X
0
0
ꢀ
ꢀ
ꢀ
1
X
0
1
ꢀ
ꢀ
ꢀ
1
00-1F
20
21
ꢀ
Control Register*
Channel 0†
0
Channel 1†
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
3F
Channel 31†
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 4 - Control Register Bits
Mode
Control
Bits
Stream
Address
Bits
Memory
Select
Bits
(Unused)
7
6
5
4
3
2
1
0
BIT
NAME
DESCRIPTION
7
Split
When 1, all subsequent reads are from the Data Memory
and writes are to the Connection Memory Low, except when
the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In
either case, the Stream Address Bits select the subsection of
the memory which is made available.
Memory
6
Message
Mode
When 1, the contents of the Connection Memory Low are output
on the Serial Output streams except when the ODE pin is low.
When 0, the Connection Memory bits for each channel determine
what is output.
5
(unused)
Memory
4-3
0-0 - Not to be used
Select Bits
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0
Stream
Address
Bits
The number expressed in binary notation on these bits refers to
the input or output ST-BUS stream which corresponds to the
subsection of memory made accessible for subsequent operations.
3
Figure5 - Connection Memory High Bits
No Corresponding Memory
- These bits give 0s if read.
Per Channel
Control Bits
7
6
5
4
3
2
1
0
BIT
NAME
DESCRIPTION
2
Message
Channel
When 1, the contents of the corresponding location in Connection
Memory Low are output on the location’s channel and stream.
When 0, the contents of the corresponding location in Connection
Memory Low act as an address for the Data Memory and so
determine the source of the connection to the location’s channel
and stream.
1
0
CSTo
This bit is output on the CSTo pin one channel early. The CSTo bit
for stream 0 is output first.
Output
Enable
If the ODE pin is high and bit 6 of the Control Register is 0, then
this bit enables the output driver for the location’s channel and
stream. This allows individual channels on individual streams to
be made high-impedance, allowing switching matrices to be
constructed. A "1" enables the driver and a "0" disables it.
If the ODE pin is low, then all serial
outputs are high-impedance. If it is high
and bit 6 in the Control Register is 1, then
all outputs are active. If the ODE pin is
high and bit 6 in the Control Register is 0,
then the bit 0 in the Connection Memory
High location enables the output drivers
for the corresponding individual ST-BUS
output stream and channel. Bit 0=1
enables the driver and bit 0=0 disables it
(see Figure 5).
interface between the IMP8980D’s and the
filter/codecs. Figure 8 shows the position of
these components in an example architec-
ture.
The Mitel MT8964 filter/codec in
Figure 7 receives and transmits digitized
voice signals on the ST-BUS input DR,
and ST-BUS output DX, respectively.
These signals are routed to the ST-BUS
inputs and outputs on the top IMP8980D,
which is used as a digital speech switch.
Bit 1 of each Connection Memory High
location (see Figure 5) is output on the
CSTo pin once every frame. To allow for
delay in any external control circuitry the
bit is output one channel before the
corresponding channel on the ST-BUS
streams, and the bit for stream 0 is output
first in the channel; e.g., bit 1’s for
channel 9 of streams 0-7 are output
synchronously with ST-BUS channel 8
bits 7-0.
The MT8964 is controlled by the
ST-BUS input DC originating from the
bottom IMP8980D , which generates the
appropriate signals from an output channel
in Message Mode. This architecture
optimizes the messaging capability of the
line circuit by building signalling logic, e.g.,
for on-off hook detection, which commu-
nicates on an ST-BUS output. This
signalling ST-BUS output is monitored by
a microprocessor (not shown) through an
ST-BUS input on the bottom IMP8980D.
Applications
Figure 8 shows how a simple digital
switching system may be designed using the
ST-BUS architecture. This is a private
telephone network with 256 extensions
which uses a single IMP8980D as a speech
Digital Switching Systems
Figures 7 and 8 show how IMP8980Ds
and MT8964s form a simple digital
switching system. Figure 7 shows the
4
© IMP, Inc.
IMP8980D DS-5-00
switch and a second IMP8980D for
communication with the line interface
circuits.
A larger digital switching system may be
designed by cascading a number of
IMP8980Ds. Figure 9 shows four
IMP8980Ds arranged in a non-blocking
configuration which can switch any
channel on any of the ST-BUS inputs to
any channel on the ST-BUS outputs.
For convenience, a 4MHz crystal
oscillator has been used rather than a
4.096MHz clock, as both are within the
limits of the chip’s specifications. The RC
delay used with the 393 counters ensures a
sufficient hold time for the FP signal, but
the values used may have to be changed if
faster 393 counters become available.The
chip is shown as memory mapped into the
MEK6802D3 system. Chip addresses
00-3F correspond to processor addresses
2000-203F. Delay through the address
decoder requires the VMA signal to be
used twice to remove glitches. The
Application Circuit with 6802
Processor
Figure 10 shows an example of a
complete circuit which may be used to
evaluate the chip.
MEK6802D3 board uses a 10KΩ pullup
on the MR pin, which would have to be
incorporated into the circuit if the board
was replaced by a processor.
Figure 6 - Connection Memory Low Bits
Stream
Address
Bits
Channel
Address
Bits
7
6
5
4
3
2
1
0
BIT
NAME
DESCRIPTION
7-5*
Stream *
Address
Bits
The number expressed in binary notation on these 3 bits is
the number of the ST-BUS stream for the source of the connection.
Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5
is 0, then the source of the connection is a channel on STi4.
The number expressed in binary notation on these 5 bits is
the number of the channel which is the source of the connection
(The ST-BUS stream where the channel lies is defined by bits 7,
6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is
0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the
connection is channel 19.
4-0*
Channel
Address
Bits*
* If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1,
then the entire 8 bits are output on the channel and stream associated with this location.
Otherwise, the bits are used as indicated to define the source of the connection which is
output on the channel and stream associated with this location.
5
Figure 7 Typical Simple Digital Switching System
STo0
STi0
8980 used
as
speed
switch
IMP8980
Dx
Dr
Dr
MT9964
Filter/Codec
Line Divider
and
2- to 4-
Wire
Signalling
Logic
STo0
Converter
STi0
8980 used
in message
Line Interface Circuit with Filter/Codec
IMP8980
mode for
control and
signalling
Figure 8 Simple Digital Switching System
Line Interface Circuit
with Codec (e.g. 8964)
Line 1
8
Speech
Switch
STi0-7
STo0-7
STi0-7
STo0-7
8
8980
.
.
.
.
.
.
Controlling
µprocessor
8
Repeated for Lines
2 to 255
Repeated for Lines
2 to 255
8
Control &
Signalling
8980
Line Interface Circuit
with Codec (e.g. 8964)
Line 256
Figure 9 Non-Blocking 16x16 Switch
8980
#1
STi0/7 STo0/7
OUT 0/7
IN 0/7
8980
#2
STi0/7 STo0/7
OUT 8/15
8980
#3
STi0/7 STo0/7
IN 8/15
8980
#4
STi0/7 STo0/7
6
© IMP, Inc.
IMP8980D DS-5-00
Figure 10 Application Circuit
D7-D0
5V
1
2
3
4
5
6
7
8
A15
A14
A13
0V
16
15
14
13
12
11
10
9
MD
74
HCT
138
A15-A0
0V
VMA
R/W
MEK6802D3
0V
System
MR
VMA
E
1
2
3
4
5
6
7
8
5V
16
15
14
13
12
11
10
9
A12
A11
A10
0V
MD
74
HCT
138
0V
0V
1
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
SRo7
VSS
D0
DTA
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
5V
0V
2
STi0
3
STi1
16
1
2
3
4
5
6
7
8
5V
4
STi2
A9
A8
A7
0V
0V
909Ω
15
14
13
12
11
10
9
5
STi3
1/4W
MD
74
HCT
138
6
STi4
7
STi5
5V
5V
8
STi6
STi7
VDD
F0i
9
IMP
8980
10
11
12
13
14
15
16
17
18
19
20
0V
C4i
A0
D1
D2
A1
D3
A2
D4
5V
A3
16
15
14
13
12
11
10
9
A6
1
2
3
4
5
6
7
8
D5
A4
VMA
0V
MD
74
HCT
138
D6
A5
D7
ADS
R/W
0V
0V
CS
0V
1
2
3
4
5
6
7
8
9
10
5V
0V
MR
20
19
18
17
16
15
14
13
12
11
C4i
14
5V
0V
1
2
3
4
5
6
7
DTA
CS
0V
0V
13
12
11
10
9
510Ω
SN
74
HCT
393
MD
74
HCT
240
C4i
0V
F0i
0V
0V
8
5V
0V
14
13
12
11
10
9
1
5V
100pF
0V
0V
2
3
4
5
6
7
4MHz
SN
74
HCT
393
8
2MΩ
7
Absolute Maximum Ratings*
Parameter
Symbol
Min
-0.3
Max
7
Units
V
1
2
3
4
5
6
VDD - VSS
Voltage on Digital Inputs
Voltage on Digital Outputs
Current at Digital Outputs
Storage Temperature
Package Power Dissipation
VI
VO
IO
VSS-0.3
VSS-0.3
VDD+0.3
VDD+0.3
40
V
V
mA
°C
W
TS
PD
-65
+150
2
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated.
Characteristics
Sym
Min Typ ‡ Max
Units
°C
V
Test Conditions
1
2
3
Operating Temperature TOP
-40
4.75
0
+85
5.25
VDD
Positive Supply
Input Voltage
VDD
VI
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (V SS ) unless otherwise stated.
Characteristics
Sym
Min Typ‡ Max Units Test Conditions
Inputs
1
2
3
4
5
Supply Current
Input High Voltage
Input Low Voltage
Input Leakage
Input Pin Capacitance
IDD
VI H
VI L
II L
6
10
mA
V
Outputs unloaded
2.0
0.8
5
V
µA
pF
VI between VSS and VDD
CI
8
Outputs
6
7
8
9
Output High Voltage
Output High Current
Output Low Voltage
Output Low Current
VOH
IOH
VOL
IOL
2.4
10
V
IOH = 10 mA
15
10
8
mA
V
Sourcing. VOH=2.4V
IOL = 5 mA
0.4
5
5
mA
µA
pF
Sinking. VOL = 0.4V
VO between VSS and VDD
10 High Imp. Leakage
IOZ
11 Output Pin Capacitance CO
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Figure 11 Output Load Test
Test Point
VDD
S1 is open circuit except
when testing output levels
or high impedance states.
RL
Output
Pin
S1
S2 is switched to VDD or
VSS when testing output
levels or high impedance
states.
S2
CL
VSS
VSS
8
© IMP, Inc.
IMP8980D DS-5-00
AC Electrical Characteristics † - Clock Timing (Figures 12 and 13)
Characteristics
Sym
Min Typ ‡ Max
Units
ns
Test Conditions
1
2
3
4
5
6
7
Clock Period*
tCLK
220
95
244
122
122
20
300
150
150
Clock Width High
Clock Width Low
t
CH
ns
t
CL
110
ns
Clock Transition Time
Frame Pulse Setup TIme
Frame Pulse Hold Time
Frame Pulse Width
t
CTT
ns
t
CCT
20
ns
t
FPH
0.020
670
µs
ns
t
FPW
244
†† Timing is over recommended temperature & power supply voltages.
‡
*
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high
impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i
.
Figure 12 Frame Allignment
C4i
FOi
Bit
Cells
Channel 31
Bit 0
Channel 0
Bit 7
Figure 13 Clock Timing
t
CLK
t
t
CH
t
CTT
CL
2.0V
0.8V
C4i
F0i
t
t
CTT
CHL
t
t
FPS
FPH
t
t
FPH
FPS
2.0V
0.8V
t
FPW
9
AC Electrical Characteristics † - Serial Streams (Figures 11, 14, 15 and 16)
Characteristics
Sym
Min Typ ‡ Max Units
Test Conditions
Inputs
1
2
3
4
5
6
7
STo0/7 Delay-Active to High Z
STo0/7 Delay-High Z to Active
STo0/7 Delay-Active to Active
STo0/7 Hold Time
t
SAZ
SZA
20
25
30
25
50
60
65
45
45
50
75
80
ns
ns
ns
ns
ns
ns
ns
RL=1 KΩ*, CL=150 pF
CL=150 pF
t
125
125
tSAA
CL=150 pF
tSOH
CL=150 pF
Output Driver Enable Delay
External Control Hold Time
External Control Delay
Outputs
t
OED
125
110
-20
RL=1 KΩ*, CL=150 pF
CL=150 pF
t
XCH
0
t
XCD
CL=150 pF
8
9
Serial Input Setup Time
Serial Input Hold Time
t
SIS
-40
ns
ns
t
SIH
90
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
High Impedance is measured by pulling to the appropriate rail with RL , with timing corrected to cancel time taken to discharge C
*
.
L
Figure 14 Serial Outputs and External
Control
Figure 15 Output Driver Enable
2.0V
ODE
0.8V
Bit Cell Boundary
2.0V
C4i
2.4V
STo0
0.8V
to
ST o7
0.4V
t
SOH
t
t
OED
OED
STo0
to
STo7
2.4V
0.4V
t
SAZ
STo0 2.4V
to
STo7 0.4V
Figure 16 Serial Inputs
t
SZA
t
SOH
Bit Cell Boundaries
STo0
to
STo7
2.4V
0.4V
2.0V
0.8V
C4i
t
SAA
t
SIH
t
XCH
2.0V
0.8V
STo0
2.4V
0.4V
to
CSTo
STo7
t
SIS
t
XCD
10
© IMP, Inc.
IMP8980D DS-5-00
AC Electrical Characteristics † - Processor Bus (Figures 11 and 17)
Characteristics
Sym
Min Typ ‡ Max
Units
ns
Test Conditions
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
tCSS
20
25
25
40
2.7
20
0
5
5
t
RWS
ns
t
ADS
ns
A
cknowledgement
Fast
t
AKD
100
7.2
ns
CL=150 pF
Delay
Slow
t
AKD
cycles
ns
C4i cycles ➀
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
Data Hold Time Read
Write
t
FWS
SWD
RDS
t
2.0
1.7
0.5
cycles C4i cycles ➀
t
cycles C4i cycles ➀, CL= 150 pF
t
DHT
DHT
RDZ
20
20
ns
ns
ns
ns
ns
ns
ns
RL=1 KΩ * , CL=150 pF
t
10
50
9
Read Data To High Imp.
t
t
90
RL=1 KΩ * , CL=150 pF
10 Chip Select Hold Time
11 Read/Write Hold Time
12 Address Hold Time
13 Acknow. Hold Time
t
CSH
0
0
RWH
t
ADH
AKH
0
t
10
60
80
RL=1 KΩ * , CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.
*
➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
Figure 17 Processor Bus
2.0V
0.8V
DS
2.0V
CS
0.8V
t
t
CSS
CSH
2.0V
0.8V
R/W
t
t
RWS
RWH
2.0V
0.8V
A5
to
A0
t
t
ADH
ADS
t
AKD
t
AKH
2.4V
0.4V
DTA
t
RDS
t
DHT
D7
to
D0
2.4V (Read) 2.0V (Write)
0.8V (Read) 0.8V (Write)
t
t
t
SWD
FWS
RDZ
11
Pin Description
Pin #
Name
Description
40
DIP
1
44
PLCC
2
DTA
Data Acknowledgement (Open Drain Output). This is
the data acknowledgement on the microprocessor
interface. This pin is pulled low to signal that the chip
has processed the data. A 909 Ω, 1/4W, resistor is
recommended to be used as a pullup.
2
-4
5
3
-5
7
STi0
-STi2
STi3
-STi7
ST-BUS Input 0 to 2 (Inputs). These are the inputs for
the 2048 kbit/s ST-BUS input streams.
ST-BUS Input 3 to 7 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS
input streams.
-9
-11
10
11
12
13
VDD Power Input. Positive Supply.
F0i
C4i
Framing 0-Type (Input). This is the input for the frame
synchronization pulse for the 2048 kbit/s ST-BUS
streams. A low on this input causes the internal
counter to reset on the next negative transition of C4i
4.096 MHz Clock (Input). ST-BUS bit cell boundaries
lie on the alternate falling edges of this clock.
Address 0 to 2 (Inputs). These are the inputs for the
address lines on the microprocessor interface.
Address 3 to 5 (Inputs). These are the inputs for the
address lines on the microprocessor interface.
Data Strobe (Input). This is the input for the active
high data strobe on the microprocessor interface.
12
14
13
-15
16
-18
19
15
-17
19
-21
22
A0
-A2
A3
-A5
DS
20
21
23
24
R/W
CS
Read or Write (Input). This is the input for the
read/write signal on the microprocessor interface
- high for read, low for write.
Chip Select (Input). This is the input for the active low
chip select on the microprocessor interface
Data 7 to 5 (Three-state I/O Pins). These are the
bidirectional data pins on the microprocessor interface.
Data 4 to 0 (Three-state I/O Pins). These are the
bidirectional data pins on the microprocessor interface.
Power Input. Negative Supply (Ground).
ST-BUS Output 7 to 3 (Three-state Outputs). These
are the pins for the eight 2048 kbit/s ST-BUS output
streams.
22
-24
25
-29
30
31
25
-27
29
-33
34
D7
-D5
D4
-D0
VSS
35
-39
STo7
-ST03
-35
36
-38
41
-43
STo2
- STo0
ST-BUS Output 2 to 0 (Three-state Outputs). These
are the pins for the eight 2048 kbit/s ST-BUS output
streams.
39
40
44
ODE
Output Drive Enable (Input). If this input is held high,
the STo0-STo7 output drivers function normally. If this
input is low, the STo0-STo7 output drivers go into their
high impedance state. NB: Even when ODE is high,
channels on the STo0-STo7 outputs can go high
impedance under software control.
Control ST-BUS Output (Complementary Output).
Each frame of 256 bits on this ST-BUS output contains
the values of bit 1 in the 256 locations of the
Connection Memory High.
1
CSTo
NC
6,
No Connection.
18,
28,
40
12
© IMP, Inc.
IMP8980D DS-5-00
Figure 2 Pin Connections
39
38
37
36
35
34
33
32
31
30
29
STi3
7
8
9
STo3
ST04
ST05
STo6
STo7
VSS
D0
D1
D2
D3
D4
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
10
11
12
13
14
15
16
17
44 Pin PLCC
DTA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
ST04
ST05
STo6
STo7
VSS
D0
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
D1
A1
D2
A2
D3
A3
D4
A4
D5
A5
D6
DS
D7
R/W
CS
40 Pin CERDIP/Plastic DIP
Ordering Information
Ordering Part Number
IMP8980DC
Package Type
40 Pin Ceramic DIP
40 Pin Plastic DIP
IMP8980DE
IMP8980DP
44 Pin PLCC
IMP8980DP/T
Tape and Reel, 44 Pin PLCC
13
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Information furnished by IMP, Inc. is believed to be accurate and reliable. No responsibility is assumed
by IMP for use of this product nor for any infringements of patents or trademarks or other rights of third
parties resulting from its use. IMP reserves the right to make changes in specifications at any time
without notice. IMP does not authorize or warrant any IMP products for use in life support devices and/
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All other company and product names are trademarks of their respective owners.
© 2000 IMP, Inc.
Printed in USA
Part No.:
Document Number: IMP8980D DS 05/00
14
© IMP, Inc.
IMP8980D DS-5-00
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