TP358-SR1 [3PEAK]
General Purpose, 1MHz, Micro-Power CMOS Op-Amps;
| 型号： | TP358-SR1 |
| 厂家： | 
3PEAK |
| 描述： | General Purpose, 1MHz, Micro-Power CMOS Op-Amps |
| 文件： | 总12页 (文件大小：1025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP321/TP358/TP324
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Features
Description
TP321/358/324 are general purpose single, dual
and quad CMOS op-amps with low offset, high
frequency response, low power, low supply voltage,
and rail-to-rail inputs and outputs. They incorporate
3PEAK’s proprietary and patented design
techniques to achieve best in-class performance
with low cost among all micro-power CMOS
amplifiers.
General Purpose, Low Cost
Gain Bandwidth Product: 1MHz
Low Quiescent Current: 45μA/Amplifier
Offset Voltage: 5.0mV Maximum
Offset Voltage Temperature Drift: 2uV/°C
Input Bias Current: 10pA
The TP321/358/324 are unity gain stable with a
constant 1MHz gain-bandwidth product, 1V/μs slew
rate while consuming only 45μA of supply current
per amplifier. The rail-to-rail input and output
characteristics allow the full power-supply voltage to
be used for signal range.
CMRR/PSRR: 90dB
Unity Gain Stable
Rail-to-Rail Input and Output
No Phase Reversal for Overdriven Inputs
Supply Voltage Range: 2.1V to 6.0V
Operation Range: –40°C to 125°C
This combination of features makes the TP321/358
/324 superior and cost-effective among RRIO
CMOS op-amps. The TP321/358/324 are ideal
choices for battery-powered applications because
they minimize errors due to power supply voltage
variations over the lifetime of the battery and
maintain high CMRR even for a rail-to-rail input
op-amp.
ESD Rating:
8kV – HBM, 2kV – CDM and 500V – MM
Popular Type Package
Applications
Audio Output
The TP321/358/324 can be used as cost-effective
plug-in replacements for many commercially
available op amps to reduce power and improve
input/output range and performance.
Battery and Power Supply Control
Smoke/Gas/Environment Sensors
Medical Equipment
Portable Instruments and Mobile Device
Active Filters
3PEAK and the 3PEAK logo are registered trademarks of
3PEAK INCORPORATED. All other trademarks are the property
of their respective owners.
Piezo Electrical Transducer Amplifier
Sensor Interface
ASIC Input or Output Amplifier
Pin Configuration(Top View)
TP321
TP358
TP324
5-Pin SOT23
(-T Suffix)
8-Pin SOIC
(-S Suffix)
14-Pin SOIC
(-S Suffix)
1
2
3
5
4
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
+In
-VS
-In
+VS
Out
Out A
-In A
+In A
-VS
+VS
Out A
-In A
Out D
-In D
+In D
-VS
Out B
-In B
+In B
A
A
D
C
+In A
B
+VS
+In B
+In C
-In C
Out C
B
-In B
8
Out B
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REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Note 1
Absolute Maximum Ratings
Supply Voltage: V+ – V–....................................6.6V
Input Voltage............................. V– – 0.1 to V+ + 0.1
Input Current: +IN, –IN, SHDN Note 2.............. ±10mA
Output Current: OUT.................................... ±40mA
Output Short-Circuit Duration Note 3…......... Indefinite
Operating Temperature Range.......–40°C to 125°C
Maximum Junction Temperature................... 150°C
Storage Temperature Range.......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any
Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 300mV beyond the power
supply, the input current should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply
voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The
specified values are for short traces connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
HBM
Parameter
Human Body Model ESD
Charged Device Model ESD
Machine Model ESD
Condition
Minimum Level
Unit
kV
MIL-STD-883H Method 3015.8
JEDEC-EIA/JESD22-C101E
JEDEC-EIA/JESD22-A115
8
CDM
MM
2
kV
V
500
Order and MSL Information
Model
Transport Media,
Quantity
Marking
Information
AT4YW (1)
MSL
Level
Order Number
Package
Name
TP321
TP358
TP358
TP324
TP321-TR
TP358-SR
TP358-SR1
TP324-SR
5-Pin SOT23
Tape and Reel, 3000
Tape and Reel, 4000
Tape and Reel, 4000
Tape and Reel, 2500
MSL 3
MSL 3
MSL 3
MSL 3
8-Pin SOIC
8-Pin SOIC
14-Pin SOIC
A42S
A42S
A44S
Note (1): ‘YW’ is date coding scheme. 'Y' stands for calendar year, and 'W' stands for single workweek coding scheme.
REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
5V Electrical Characteristics
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 27° C.
VSUPPLY = 5V, VCM = VOUT = VSUPPLY/2, RL = 100KΩ, CL =100pF
SYMBOL
VOS
PARAMETER
CONDITIONS
MIN
-5.0
0.3
TYP
MAX
UNITS
mV
Input Offset Voltage
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
VCM = VSUPPLY/2
●
●
± 0.8 +5.0
VOS
CH_A in TP358-SR1, VCM = VSUPPLY/2
+5.0
mV
μV/° C
pA
VOS TC
IB
2
10
1.0
IOS
pA
f = 1kHz
f = 10kHz
45
29
en
Input Voltage Noise Density
Input Resistance
nV/√Hz
GΩ
RIN
CIN
>100
Differential
Common Mode
VCM = 0.1V to 4.9V
1.5
3.0
90
Input Capacitance
pF
dB
V
CMRR
VCM
Common Mode Rejection Ratio
Common-mode Input Voltage
Range
●
●
80
-0.1
5.1
PSRR
AVOL
Power Supply Rejection Ratio
●
●
●
80
80
72
90
97
95
5
40
45
63
-15
1.0
2.3
2.8
0.33
0.38
dB
dB
VOUT = 2.5V, RLOAD = 100kΩ
VOUT = 0.1V to 4.9V, RLOAD = 100kΩ
RLOAD = 100kΩ
Open-Loop Large Signal Gain
VOL
ISC
IQ
PM
GM
GBWP
Output Swing from Supply Rail
Output Short-Circuit Current
Quiescent Current per Amplifier
Phase Margin
mV
mA
μA
°
dB
Sink or source current
●
87
RLOAD = 100kΩ, CLOAD = 100pF
RLOAD = 100kΩ, CLOAD = 100pF
f = 1kHz
0.1%
0.01%
0.1%
0.01%
Gain Margin
Gain-Bandwidth Product
Settling Time, 1.5V to 3.5V,
Unity Gain
Settling Time, 2.45V to 2.55V,
Unity Gain
MHz
tS
μs
AV = 1, VOUT = 1.5V to 3.5V, CLOAD
100pF, RLOAD = 100kΩ
=
SR
Slew Rate
1.0
V/μs
Total Harmonic Distortion and
Noise
f=1kHz, AV=1, RL=100kΩ, VOUT = 2VPP
f=10kHz, AV=1, RL=100kΩ, VOUT = 2VPP
-105
-90
THD+N
dB
Note: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to
the device. Exposure to any Absolute Maximum Rating
condition for extended periods may affect device
reliability and lifetime.
A heat sink may be required to keep the junction
temperature below the absolute maximum rating when
the output is shorted indefinitely.
Thermal resistance varies with the amount of PC
board metal connected to the package. The specified
values are for short traces connected to the leads.
The inputs are protected by ESD protection diodes to
each power supply. If the input extends more than
300mV beyond the power supply, the input current
should be limited to less than 10mA.
Full power bandwidth is calculated from the slew rate
FPBW = SR/π • VP-P.
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REV A.02
3
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Typical Performance Characteristics
Small-Signal Step Response, 100mV Step
Large-Signal Step Response, 2V Step
Open-Loop Gain and Phase
Phase Margin vs. CLOAD (Stable for Any CLOAD)
Input Voltage Noise Spectral Density
Common-Mode Rejection Ratio
REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Typical Performance Characteristics
Over-Shoot Voltage, CLOAD = 40nF, Gain = +1
Over-Shoot Voltage, CLOAD=40nF, Gain= -1, RFB=100kΩ
Power-Supply Rejection Ratio
Over-Shoot % vs. CLOAD, Gain = -1, RFB = 20kΩ
Small-Signal Over-Shoot % vs. CLOAD, Gain = +1
VIN = -0.2V to 5.7V, No Phase Reversal
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REV A.02
5
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Typical Performance Characteristics
Quiescent Supply Current vs. Supply Voltage
Quiescent Supply Current vs. Temperature
Short-Circuit Current vs. Supply Voltage
Open-Loop Gain vs. Temperature
Closed-Loop Output Impedance vs. Frequency
THD+Noise, Gain = +1, VIN = 1kHz, VPP = 2V
REV A.02
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TP321/TP358/TP324
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Vos vs. Common Mode Input Voltage
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REV A.02
7
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Pin Functions
–IN: Inverting Input of the Amplifier. Voltage range
of this pin can go from V– – 0.1V to V+ + 0.1V.
between power supply pins or between supply pins
and ground.
+IN: Non-Inverting Input of Amplifier. This pin has
the same voltage range as –IN.
–VS: Negative Power Supply. It is normally tied to
ground. It can also be tied to a voltage other than
ground as long as the voltage between V+ and V– is
from 2.1V to 5.25V. If it is not connected to ground,
bypass it with a capacitor of 0.1μF as close to the
part as possible.
+VS: Positive Power Supply. Typically the voltage is
from 2.1V to 5.25V. Split supplies are possible as
long as the voltage between V+ and V– is between
2.1V and 5.25V. A bypass capacitor of 0.1μF as
close to the part as possible should be used
OUT: Amplifier Output. The voltage range extends
to within millivolts of each supply rail.
Operation
The TP321/358/324 input signal range extends
beyond the negative and positive power supplies.
The output can even extend all the way to the
negative supply. The input stage is comprised of
two CMOS differential amplifiers, a PMOS stage
and NMOS stage that are active over different
ranges of common mode input voltage. The
Class-AB control buffer and output bias stage uses
a proprietary compensation technique to take full
advantage of the process technology to drive very
high capacitive loads. This is evident from the
transient over shoot measurement plots in the
Typical Performance Characteristics.
Applications Information
Low Supply Voltage and Low Power Consumption
The TP321/358/324 of operational amplifiers can operate with power supply voltages from 2.1V to 6.0V. Each
amplifier draws only 45μA typical quiescent current. The low supply voltage capability and low supply current are
ideal for portable applications demanding high capacitive load driving capability and wide bandwidth. The
TP321/358/324 is optimized for wide bandwidth low power applications. They have an industry leading high
GBWP to power ratio and are unity gain stable. When the load capacitance increases, the increased capacitance
at the output pushed the non-dominant pole to lower frequency in the open loop frequency response, lowering the
phase and gain margin. Higher gain configurations tend to have better capacitive drive capability than lower gain
configurations due to lower closed loop bandwidth and hence better phase margin.
Low Input Referred Noise
The TP321/358/324 provides a low input referred noise density of 45nV/√Hz at 1kHz. The voltage noise will
grow slowly with the frequency in wideband range.
Positive Input Offset Voltage
The TP321/358/324 has a low offset voltage of 5.0mV maximum which is essential for precision applications.
Low Input Bias Current
The TP321/358/324 is a CMOS OPA family and features very low input bias current in pA range. The low input
bias current allows the amplifiers to be used in applications with high resistance sources. Care must be taken to
minimize PCB Surface Leakage. See below section on “PCB Surface Leakage” for more details.
PCB Surface Leakage
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to
be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low
humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of
REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
current to flow, which is similar to the TP321/358/324 OPA’s input bias current at +27°C (±10pA, typical). It is
recommended to use multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface.
The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 1 for
Inverting Gain application.
1. For Non-Inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface.
b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage.
2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors):
a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as
the op-amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface.
Guard Ring
VIN+
VIN-
+VS
Figure 1
Ground Sensing and Rail to Rail Output
The TP321/358/324 has excellent output drive capability, delivering over 10mA of output drive current. The output
stage is a rail-to-rail topology that is capable of swinging to within 10mV of either rail. Since the inputs can go
100mV beyond either rail, the op-amp can easily perform ‘True Ground Sensing’.
The maximum output current is a function of total supply voltage. As the supply voltage to the amplifier increases,
the output current capability also increases. Attention must be paid to keep the junction temperature of the IC
below 150°C when the output is in continuous short-circuit. The output of the amplifier has reverse-biased ESD
diodes connected to each supply. The output should not be forced more than 0.3V beyond either supply,
otherwise current will flow through these diodes.
ESD
The TP321/358/324 has reverse-biased ESD protection diodes on all inputs and output. Input and out pins cannot
be biased more than 100mV beyond either supply rail.
Feedback Components and Suppression of Ringing
Care should be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at
the inverting input does not degrade stability. For example, in a gain of +2 configuration with gain and feedback
resistors of 10k, a poorly designed circuit board layout with parasitic capacitance of 5pF (part +PC board) at the
amplifier’s inverting input will cause the amplifier to ring due to a pole formed at 3.2MHz. An additional capacitor
of 5pF across the feedback resistor as shown in Figure 2 will eliminate any ringing.
Careful layout is extremely important because low power signal conditioning applications demand
high-impedance circuits. The layout should also minimize stray capacitance at the OPA’s inputs. However some
stray capacitance may be unavoidable and it may be necessary to add a 2pF to 10pF capacitor across the
feedback resistor. Select the smallest capacitor value that ensures stability.
5pF
10kΩ
VOUT
VIN
10kΩ
CPAR
Figure 2
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REV A.02
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TP321/TP358/TP324
General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Driving Large Capacitive Load
The TP321/358/324 of OPA is designed to drive large capacitive loads. Refer to Typical Performance
Characteristics for “Phase Margin vs. Load Capacitance”. As always, larger load capacitance decreases overall
phase margin in a feedback system where internal frequency compensation is utilized. As the load capacitance
increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This
produces gain peaking in the frequency response, with overshoot and ringing in output step response. The
unity-gain buffer (G = +1V/V) is the most sensitive to large capacitive loads.
When driving large capacitive loads with the TP321/358/324 (e.g., > 200 pF when G = +1V/V), a small series
resistor at the output (RISO in Figure 3) improves the feedback loop’s phase margin and stability by making the
output load resistive at higher frequencies.
RISO
VOUT
VIN
CLOAD
Figure 3
Power Supply Layout and Bypass
The TP321/358/324 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e.,
0.01μF to 0.1μF) within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or
larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts.
Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s
inputs and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place
external components as close to the op amps’ pins as possible.
Proper Board Layout
To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid
leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates
a barrier to moisture accumulation and helps reduce parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances
due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be
connected as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and
the inputs of the amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize
coupling.
A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and
other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these
thermocouple effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain
matching numbers and types of components, where possible to match the number and type of thermocouple
junctions. For example, dummy components such as zero value resistors can be used to match real resistors in
the opposite input path. Matching components should be located in close proximity and should be oriented in the
same manner. Ensure leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources
on the PCB as far away from amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain
a constant temperature across the circuit board.
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REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Package Outline Dimensions
SOT23-5
Dimensions
Dimensions In
Inches
Symbol
In Millimeters
Min
Max
Min
Max
A
1.050
0.000
1.050
0.300
0.100
2.820
1.500
2.650
0.950TYP
1.800
0.700REF
0.300
0°
1.250
0.100
1.150
0.400
0.200
3.020
1.700
2.950
0.041
0.000
0.041
0.012
0.004
0.111
0.059
0.104
0.037TYP
0.071
0.028REF
0.012
0°
0.049
0.004
0.045
0.016
0.008
0.119
0.067
0.116
A1
A2
b
C
D
E
E1
e
e1
L
2.000
0.079
L1
θ
0.460
8°
0.024
8°
SOIC-8
Dimensions
Dimensions In
Inches
In Millimeters
Symbol
Min
Max
Min
Max
A
1.350
0.100
1.350
0.330
0.190
4.780
3.800
5.800
1.270TYP
0.400
0°
1.750
0.250
1.550
0.510
0.250
5.000
4.000
6.300
0.053
0.004
0.053
0.013
0.007
0.188
0.150
0.228
0.050TYP
0.016
0°
0.069
0.010
0.061
0.020
0.010
0.197
0.157
0.248
A1
A2
B
C
D
E
E1
e
L1
θ
1.270
8°
0.050
8°
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REV A.02
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General Purpose, 1MHz, Micro-Power CMOS Op-Amps
Package Outline Dimensions
SOIC-14
Dimensions
In Millimeters
Symbol
MIN
1.35
NOM
1.60
0.15
1.45
0.65
MAX
A
1.75
0.25
1.65
0.75
0.49
0.45
0.25
0.25
8.73
6.20
4.00
A1
A2
A3
b
0.10
1.25
0.55
0.36
0.35
0.16
0.15
8.53
5.80
3.80
b1
c
0.40
c1
D
0.20
8.63
E
6.00
E1
e
3.90
1.27 BSC
0.60
L
0.45
0.80
L1
L2
R
1.04 REF
0.25 BSC
0.07
0.07
0.30
0°
R1
h
0.40
0.50
8°
θ
θ1
θ2
θ3
θ4
6°
8°
8°
7°
7°
10°
10°
9°
6°
5°
5°
9°
REV A.02
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